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Csa Project

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Uploaded by

rbtemp1149
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© © All Rights Reserved
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Aim:- To design and implement half adder using VHDL language

Software used:- Xilnix ise

Theory:-
Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic
circuit that adds two numbers and produces a sum bit (s) and carry bit © both as output.
The addition of 2 bits is done using a combination circuit called a Half adder. The input
variables are augend and addend bits and output variables are sum & carry bits. A and B are
the two input bits.
Let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident
from the function of a half adder that it requires one X-OR gate and one AND gate for its
construction.
Truth table:-
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logical expression:-
For sum:- For carry:-

Sum= A xor B. Carry= A and B

Implementation:-
VHDL code:-
Design.vhd:-
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port( a,b: in std_logic;
s: out std_logic;
c: out std_logic);
end half_adder;

architecture half_arch of half_adder is


begin
process(a,b) is
begin
s<= a xor b;
c<= a and b;
end process;
end half_arch;

testbench.vdh:-
library ieee;
use ieee.std_logic_1164.all;
entity half_add is
end half_add;
architecture half_add_arch of half_add is
component half_adder
port( a,b: in std_logic;
s,c: out std_logic);
end component;

signal a,b,s,c:std_logic;
begin
dut: half_adder port map(a,b,s,c);
process
begin
a<=’0’;
b<=’0’;
wait for 5 ns;
a<=’0’;
b<=’1’;
wait for 5 ns;
a<=’1’;
b<=’0’;
wait for 5 ns;
a<=’1’;
b<=’1’;
wait for 5 ns;
wait;
end process;
end half_add_arch;
Output waveform:-

Result:-
Half adder is studied and implemented successfully using VHDL language

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