ATmega32A

Figure 23-12. Integral Non-linearity (INL)

Output Code

INL
Ideal ADC

Actual ADC

VREF Input Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two
adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 23-13. Differential Non-linearity (DNL)

Output Code
0x3FF

1 LSB

DNL
0x000

0 VREF Input Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of Offset, Gain Error, Differential Error, Non-linearity, and Quantization
Error. Ideal value: ±0.5 LSB.

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23.8 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers
(ADCL, ADCH).
For single ended conversion, the result is

V IN  1024
ADC = --------------------------
V REF

where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 23-3 on page
214 and Table 23-4 on page 214). 0x000 represents analog ground, and 0x3FF represents the selected reference
voltage minus one LSB.
If differential channels are used, the result is
 V POS – V NEG   GAIN  512
ADC = ------------------------------------------------------------------------
V REF

where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, GAIN the selected
gain factor, and VREF the selected voltage reference. The result is presented in two’s complement form, from 0x200
(-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the results, it is suf-
ficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result is negative, and if this bit is zero,
the result is positive. Figure 23-14 shows the decoding of the differential input range.
Table 23-2 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a
gain of GAIN and a reference voltage of VREF.

Figure 23-14. Differential Measurement Range

Output Code
0x1FF

0x000

- V REF/GAIN 0 VREF/GAIN Differential Input

0x3FF
Voltage (Volts)

0x200

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Table 23-2. Correlation between Input Voltage and Output Codes

VADCn Read code Corresponding Decimal Value
VADCm + VREF/GAIN 0x1FF 511
VADCm + 511/512 VREF/GAIN 0x1FF 511
VADCm + 510/512 VREF/GAIN 0x1FE 510
:. :. :.
VADCm + 1/512 VREF/GAIN 0x001 1
VADCm 0x000 0
VADCm - 1/512 VREF/GAIN 0x3FF -1
:. :. :.
VADCm - 511/512 VREF/GAIN 0x201 -511
VADCm - VREF/GAIN 0x200 -512

Example:
ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result:
ADCL = 0x70, ADCH = 0x02.

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 ATmega32A

23.9 Register Description

23.9.1 ADMUX – ADC Multiplexer Selection Register

Bit 7 6 5 4 3 2 1 0
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 23-3. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal
voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
Table 23-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection
0 0 AREF, Internal Vref turned off
0 1 AVCC with external capacitor at AREF pin
1 0 Reserved
1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to
ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC
Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see
“ADCL and ADCH – The ADC Data Register” on page 216.

• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also
select the gain for the differential channels. See Table 23-4 for details. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 23-4. Input Channel and Gain Selections
Single Ended Positive Differential Negative Differential
MUX4:0 Input Input Input Gain
00000 ADC0
00001 ADC1
00010 ADC2
00011 ADC3 N/A
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7
01000 ADC0 ADC0 10x
01001 ADC1 ADC0 10x
01010 ADC0 ADC0 200x
01011 ADC1 ADC0 200x

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Table 23-4. Input Channel and Gain Selections (Continued)

Single Ended Positive Differential Negative Differential
MUX4:0 Input Input Input Gain
01100 ADC2 ADC2 10x
01101 ADC3 ADC2 10x
01110 ADC2 ADC2 200x
01111 ADC3 ADC2 200x
10000 ADC0 ADC1 1x
10001 ADC1 ADC1 1x
10010 N/A ADC2 ADC1 1x
10011 ADC3 ADC1 1x
10100 ADC4 ADC1 1x
10101 ADC5 ADC1 1x
10110 ADC6 ADC1 1x
10111 ADC7 ADC1 1x
11000 ADC0 ADC2 1x
11001 ADC1 ADC2 1x
11010 ADC2 ADC2 1x
11011 ADC3 ADC2 1x
11100 ADC4 ADC2 1x
11101 ADC5 ADC2 1x
11110 1.22V (VBG) N/A
11111 0V (GND)

23.9.2 ADCSRA – ADC Control and Status Register A

Bit 7 6 5 4 3 2 1 0
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a con-
version is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode, write this bit to
one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled,
or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal
13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.
Writing zero to this bit has no effect.

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• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive
edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in
SFIOR.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion
Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies
if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

Table 23-5. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor
0 0 0 2
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128

23.9.3 ADCL and ADCH – The ADC Data Register

23.9.3.1 ADLAR = 0

Bit 15 14 13 12 11 10 9 8
– – – – – – ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

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23.9.3.2 ADLAR = 1

Bit 15 14 13 12 11 10 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – – – – – – ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

When an ADC conversion is complete, the result is found in these two registers. If differential channels are used,
the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read
first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 212.

23.9.4 SFIOR – Special FunctionIO Register

Bit 7 6 5 4 3 2 1 0
ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 SFIOR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of
the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching
to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 23-6. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event

• Bit 4 – Reserved Bit

This bit is reserved for future use in the ATmega32A. For ensuring compability with future devices, this bit must be
written zero when SFIOR is written.

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24. JTAG Interface and On-chip Debug System

24.1 Features
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
• Debugger Access to:
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– Extensive On-chip Debug Support for Break Conditions, Including
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Breakpoints on Single Address or Address Range
– Data Memory Breakpoints on Single Address or Address Range
• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• On-chip Debugging Supported by Atmel Studio

24.2 Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip Debugging
A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface,
and using the Boundary-scan Chain can be found in the sections “Programming via the JTAG Interface” on page
274 and “IEEE 1149.1 (JTAG) Boundary-scan” on page 224, respectively. The On-chip Debug support is consid-
ered being private JTAG instructions, and distributed within Microchip and to selected third party vendors only.
Figure 24-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a
state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction
Register or one of several Data Registers as the scan chain (Shift Register) between the TDI input and TDO out-
put. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used for board-level test-
ing. The JTAG Programming Interface (actually consisting of several physical and virtual Data Registers) is used
for JTAG Serial Programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are
used for On-chip Debugging only.

24.3 TAP – Test Access Port

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the
Test Access Port – TAP. These pins are:
• TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).

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• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in
reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left float-
ing in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up
resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The
device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debug-
ger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the whole
system, assuming only open collectors on the reset line are used in the application.

Figure 24-1. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

BOUNDARY SCAN CHAIN

TDI
JTAG PROGRAMMING
TDO TAP INTERFACE
TCK CONTROLLER
TMS
AVR CPU
INTERNAL
FLASH Address SCAN PC
INSTRUCTION MEMORY Data CHAIN Instruction
REGISTER

ID
REGISTER BREAKPOINT
UNIT
M FLOW CONTROL

PERIPHERIAL
BYPASS

Analog inputs
U UNIT

ANALOG
X REGISTER DIGITAL

UNITS
PERIPHERAL
UNITS
BREAKPOINT
SCAN CHAIN
JTAG / AVR CORE
COMMUNICATION
ADDRESS INTERFACE

Control & Clock lines

DECODER OCD STATUS
AND CONTROL

I/O PORT n

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Figure 24-2. TAP Controller State Diagram

1 Test-Logic-Reset

0 1 1 1
Run-Test/Idle Select-DR Scan Select-IR Scan

0 0

1 1
Capture-DR Capture-IR

0 0

Shift-DR 0 Shift-IR 0

1 1

1 1
Exit1-DR Exit1-IR

0 0

Pause-DR 0 Pause-IR 0

1 1

0 0
Exit2-DR Exit2-IR

1 1

Update-DR Update-IR

1 0 1 0

24.4 TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry,
JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 24-2 depend on
the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The ini-
tial state after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register
– Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction Register
from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in
order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting
TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the

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TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls
the circuitry surrounding the selected Data Register.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel
output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only
used for navigating the state machine.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-
DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the
JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,
the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when
this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to
the Data Register captured in the Capture-DR state is shifted out on the TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched
parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states
are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction
and using Data Registers, and some JTAG instructions may select certain functions to be performed in the Run-
Test/Idle, making it unsuitable as an Idle state.
Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS
high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 223.

24.5 Using the Boundary-scan Chain

A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-
scan” on page 224.

24.6 Using the On-chip Debug System

As shown in Figure 24-1, the hardware support for On-chip Debugging consists mainly of:
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units
• Break Point unit
• Communication interface between the CPU and JTAG system
All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions
via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part
of the communication interface between the CPU and the JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, 2 Program Memory Break
Points, and 2 combined Break Points. Together, the 4 Break Points can be configured as either:
• 4 single Program Memory Break Points
• 3 Single Program Memory Break Point + 1 single Data Memory Break Point
• 2 single Program Memory Break Points + 2 single Data Memory Break Points
• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”)
• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”)
A debugger, like the Atmel Studio, may however use one or more of these resources for its internal purpose, leav-
ing less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on
page 222.

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The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must
be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the On-
chip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would have pro-
vided a back-door into a secured device.
The AVR JTAG ICE is a powerful development tool for On-chip Debugging of all AVR 8-bit RISC Microcontrollers
with IEEE 1149.1 compliant JTAG interface. The JTAG ICE and the Atmel Studio user interface give the user com-
plete control of the internal resources of the microcontroller, helping to reduce development time by making
debugging easier. The JTAG ICE performs real-time emulation of the micrcontroller while it is running in a target
system.
Refer to the Support Tools section on the AVR pages on www.microchip.com for a full description of the AVR
JTEG ICE. Atmel Studio can be downloaded free from Software section on the same web site.
All necessary execution commands are available in Atmel Studio, both on source level and on disassembly level.
The user can execute the program, single step through the code either by tracing into or stepping over functions,
step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execu-
tion, and reset the execution target. In addition, the user can have an unlimited number of code breakpoints (using
the BREAK instruction) and up to two data memory breakpoints, alternatively combined as a mask (range) Break
Point.

24.7 On-chip Debug Specific JTAG Instructions

The On-chip Debug support is considered being private JTAG instructions, and distributed within Microchip and to
selected third party vendors only. Instruction opcodes are listed for reference.

24.7.1 PRIVATE0; $8
Private JTAG instruction for accessing On-chip Debug system.

24.7.2 PRIVATE1; $9
Private JTAG instruction for accessing On-chip Debug system.

24.7.3 PRIVATE2; $A
Private JTAG instruction for accessing On-chip Debug system.

24.7.4 PRIVATE3; $B
Private JTAG instruction for accessing On-chip Debug system.

24.8 Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI and TDO. These are
the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not
required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUSR Register
must be cleared to enable the JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming and verifying
• EEPROM programming and verifying
• Fuse programming and verifying
• Lock bit programming and verifying
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the
OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no
back-door exists for reading out the content of a secured device.

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 ATmega32A

The details on programming through the JTAG interface and programming specific JTAG instructions are given in
the section “Programming via the JTAG Interface” on page 274.

24.9 Register Description

24.9.1 OCDR – On-chip Debug Register

Bit 7 6 5 4 3 2 1 0
MSB/IDRD LSB OCDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The OCDR Register provides a communication channel from the running program in the microcontroller to the
debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an Internal
Flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When
the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The
debugger clears the IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only
be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all
other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.

24.10 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992

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25. IEEE 1149.1 (JTAG) Boundary-scan

25.1 Features
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the JTAG Standard
• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
• Supports the Optional IDCODE Instruction
• Additional Public AVR_RESET Instruction to Reset the AVR

25.2 Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well
as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level,
all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An
external controller sets up the devices to drive values at their output pins, and observe the input values received
from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan
provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using
the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and
EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Cir-
cuit Board. Initial scanning of the Data Register path will show the ID-code of the device, since IDCODE is the
default JTAG instruction. It may be desirable to have the AVR device in Reset during Test mode. If not reset, inputs
to the device may be determined by the scan operations, and the internal software may be in an undetermined
state when exiting the Test mode. Entering reset, the outputs of any Port Pin will instantly enter the high imped-
ance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the
shortest possible scan chain through the device. The device can be set in the reset state either by pulling the exter-
nal RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the
output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-Register.
Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damag-
ing the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for
taking a snapshot of the external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR must be cleared to enable
the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal
chip frequency is possible. The chip clock is not required to run.

25.3 Data Registers

The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 224

 ATmega32A

25.3.1 Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path
between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Regis-
ter can be used to shorten the scan chain on a system when the other devices are to be tested.

25.3.2 Device Identification Register

Figure 25-1 shows the structure of the Device Identification Register.

Figure 25-1. The Format of the Device Identification Register

MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Version Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1 bit

25.3.2.1 Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the revision
of the device. Revision A is 0x0, revision B is x1 and so on.

25.3.2.2 Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for ATmega32A is listed in
Table 25-1.

Table 25-1. AVR JTAG Part Number

Part Number JTAG Part Number (Hex)
ATmega32A 0x9502

25.3.2.3 Manufacturer ID
The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID is listed in Table 25-
2.

Table 25-2. Manufacturer ID

JTAG Manufacturer ID (Hex)
0x01F

25.3.3 Reset Register

The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port Pins when reset,
the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there
is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will
remain reset for a Reset Time-Out Period (refer to “Clock Sources” on page 32) after releasing the Reset Register.
The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 25-2.

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 225