Design and Simulation of Inverter

Exp No: Date:

Aim: To design an inverter using Mentor Graphics - Tanner Tools v2021.2

and to verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
An inverter (also called a NOT gate) is a basic logic gate in digital circuits that
performs logical inversion. It converts a logical "1" (high voltage) to a logical "0"
(low voltage) and vice versa. The CMOS inverter (Complementary Metal-Oxide-
Semiconductor inverter) is one of the most fundamental building blocks in digital
circuits, especially in CMOS technology, due to its high efficiency and low power
consumption.
A CMOS inverter consists of two types of transistors:
• PMOS (P-type Metal-Oxide-Semiconductor) transistor.
• NMOS (N-type Metal-Oxide-Semiconductor) transistor.
These transistors are connected in a complementary arrangement:
• The PMOS transistor is placed between the output node and the positive power
supply (VDD).
• The NMOS transistor is placed between the output node and ground (GND).
Both transistors share the same input node, which is the gate terminal of the
transistors, and the output node is the point where their drains are connected.
Basic configuration:
• Input (A): Connected to the gates of both the PMOS and NMOS transistors.
• Output (Z): Taken from the connection of the drains of the PMOS and NMOS.
• VDD: Connected to the source of the PMOS transistor.
• GND: Connected to the source of the NMOS transistor.
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of NAND GATE
Exp No: Date:

Aim: To design a NAND GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A NAND gate (Not AND) is a fundamental digital logic gate that outputs a logical 0
only when all of its inputs are logically 1. Otherwise, the output is 1. It is one of the
basic building blocks in digital electronics and is used in many combinational and
sequential logic circuits. The operation of the NAND gate is the inverse of an AND
gate.
A NAND gate can be implemented at the transistor level using complementary metal-
oxide-semiconductor (CMOS) technology, which consists of:
• PMOS transistors: Used for pulling the output to the high voltage (logic 1).
• NMOS transistors: Used for pulling the output to the low voltage (logic 0).
• The PMOS transistors are connected in parallel between the output and the
power supply (VDD).
• The NMOS transistors are connected in series between the output and ground
(GND).
• • When both inputs are 1 (high), the NMOS transistors conduct, and the output is
pulled to 0 (low).

Input A Input B Output (Y)

0 0 1
0 1 1
1 0 1
1 1 0
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of NOR GATE
Exp No: Date:

Aim: To design a NOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A NOR gate (Not OR) is another fundamental digital logic gate. It outputs a logical 1
only when all of its inputs are 0. Otherwise, the output is 0. It is the inverse of an OR
gate and is used widely in combinational logic circuits.
Transistor-Level Design: A NOR gate can be implemented using CMOS technology
with the following components:
• PMOS transistors: Used to pull the output to the high voltage (logic 1).
• NMOS transistors: Used to pull the output to the low voltage (logic 0).
For a 2-input NOR gate:
• The PMOS transistors are connected in series between the output and the
power supply (VDD).
• The NMOS transistors are connected in parallel between the output and
ground (GND).
• When both inputs are 0, both PMOS transistors conduct, pulling the output to 1
(high).

Input A Input B Output (Y)

0 0 1
0 1 0
1 0 0
1 1 0
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of AND GATE
Exp No: Date:

Aim: To design a AND GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
An AND gate is a basic digital logic gate that performs a logical multiplication
operation. The output of an AND gate is 1 (high) only when all its inputs are 1 (high).
If any input is 0 (low), the output will be 0 (low). The AND gate plays a fundamental
role in digital circuits, including arithmetic operations, control systems.
An AND gate can be implemented using CMOS technology. It consists of:
• PMOS transistors: These transistors pull the output to the high (logic 1).
• NMOS transistors: These transistors pull the output to the low (logic 0).
• The PMOS transistors are connected in parallel between the output and the
power supply (VDD).
• The NMOS transistors are connected in series between the output and ground.
• An inverter is connected to the output of the NAND gate thus it becomes an
AND gate
• When both inputs are 1 (high), both NMOS transistors conduct, pulling the
output to 0 (low).
• If either input is 0 (low), at least one PMOS transistor will conduct, pulling the
output to 1 (high).

Input A Input B Output (Y)

0 0 0
0 1 0
1 0 0
1 1 1
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of OR GATE
Exp No: Date:

Aim: To design a OR GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
An OR gate is a fundamental digital logic gate that outputs a logical 1 (high) when at
least one of its inputs is 1 (high). If all inputs are 0 (low), the output is 0 (low). OR
gates are essential components in digital circuits, allowing for various functionalities
like decision-making, data routing, and signal processing.
In CMOS technology, an OR gate can be implemented using PMOS and NMOS
transistors:
• PMOS transistors connect in series between the output and the power supply
(VDD).
• NMOS transistors connect in parallel between the output and ground (GND).
• An inverter is connected to the output of the NOR gate thus it becomes an OR
gate
• • When either input is 1, at least one PMOS transistor will conduct, pulling the
output to 1.
• • If both inputs are 0, both NMOS transistors conduct, pulling the output to 0.

Input A Input B Output (Y)

0 0 0
0 1 1
1 0 1
1 1 0
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of XOR GATE
Exp No: Date:

Aim: To design a XOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
The XOR (exclusive OR) gate is a fundamental digital logic gate that outputs
true or 1 when the number of true inputs is odd, i.e., when the inputs are different.
The XOR gate is widely used in digital circuits, such as arithmetic logic units, error
detection, and cryptography, due to its unique behavior of distinguishing between
identical and different inputs.
The XOR gate is a type of binary gate with two inputs and one output. It performs a
logical operation where the output is high (1) when the inputs are different (one input
is high, and the other is low), and the output is low (0) when the inputs are the same
(both high or both low).
The XOR gate is often referred to as a parity checker. In circuits, XOR is commonly
used to check whether an even or odd number of inputs are high. When multiple XOR
gates are combined, they can perform parity checks on binary data streams, which is
critical for error detection and correction in communication systems.
For example, if we XOR all the bits in a binary number, the result will be:
• 0 if the number of 1’s is even (even parity).
• 1 if the number of 1’s is odd (odd parity)

Input A Input B Output (Y)

0 0 0
0 1 1
1 0 1
1 1 0
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of XNOR GATE
Exp No: Date:

Aim: To design a XNOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
The XNOR (exclusive NOR) gate is a fundamental digital logic gate that outputs true
or 1 when the number of true inputs is even, i.e., when the inputs are the same. The
XNOR gate is widely used in digital circuits such as equality checkers, data
comparators, and certain types of error detection due to its behavior of identifying
when inputs are identical.
The XNOR gate is a binary gate with two inputs and one output. It performs a logical
operation where the output is high (1) when the inputs are the same (both high or both
low), and the output is low (0) when the inputs are different (one input is high, and the
other is low). Essentially, the XNOR gate is the complement of the XOR gate, as it
produces the opposite output for the same input conditions.
The XNOR gate is commonly referred to as an equality gate or equivalence gate
because it checks for the equivalence of the inputs. In digital circuits, XNOR gates are
often used in comparison operations, as they indicate when two binary values are
identical.
An example of XNOR output in a binary number would be:
• 1 if the number of 1’s is even (even parity).
• 0 if the number of 1’s is odd (odd parity).

Input A Input B Output (Y)

0 0 1
0 1 0
1 0 0
1 1 1
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of Half Adder
Exp No: Date:

Aim: To design a Half Adder using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A Half Adder is one of the basic building blocks in digital electronics, used for the
addition of two single-bit binary numbers. The half adder is a combinational logic
circuit, meaning its output depends only on the present input values and not on any
previous history or state.

The primary purpose of a half adder is to add two binary digits and provide two
results:
• Sum: The result of the addition (without considering the carry).
• Carry: The overflow from the sum, which is carried to the next more significant
bit in case of multi-bit addition.
Since NAND gates are universal gates, any logic circuit, including a half adder, can be
implemented using only NAND gates. This is significant in the design of integrated
circuits because NAND gates are often more efficient to manufacture.

Input A Input B Sum (S) Carry(C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of Full Adder
Exp No: Date:

Aim: To design a Full Adder using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A full adder is a combinational logic circuit used to add three binary bits, producing a
sum and a carry. The three bits are the two input bits to be added and a carry bit from a
previous addition. A full adder is composed of two half adders and an OR gate when
using basic logic gates. However, the full adder can also be implemented using only
NAND gates, which are considered universal gates because any logic gate can be
constructed using just NAND gates.
A full adder takes three inputs:
• A: First binary input
• B: Second binary input
• Cin: Carry input (from the previous stage of addition)
And produces two outputs:
• Sum: The sum bit
• Cout: The carry output, which is passed to the next stage.
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of D Flip Flop
Exp No: Date:

Aim: To design a D Flip Flop using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A D flip-flop (Data or Delay flip-flop) is one of the most commonly used types of flip-
flops in digital circuits. It captures the value of the data input (D) on the rising or
falling edge of a clock signal (CLK) and stores that value until the next clock cycle.
1. D Input: The input to the D flip-flop is the D (Data) input. It represents the
value that needs to be stored in the flip-flop.
2. Clock Input (CLK): The flip-flop changes its state only when there is a
transition in the clock signal (typically on the rising or falling edge).
3. Q Output: The flip-flop's output is Q, which holds the value that was sampled
at the D input when the clock transitioned.
4. Q' Output: This is the complement (inverse) of the Q output.
The D flip-flop is designed such that the output Q takes the value of D only when the
clock signal allows it to do so.
When the clock signal is low, the master latch is transparent, and the D input is passed
to the master latch.
When the clock signal is high, the slave latch updates to hold the value that was stored
in the master latch, and the output Q is updated.

D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of JK Flip Flop
Exp No: Date:

Aim: To design a JK Flip Flop using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A JK flip-flop is a versatile and widely used type of flip-flop in digital circuits,
functioning as an enhancement of the SR flip-flop. Unlike the SR flip-flop, the JK
flip-flop eliminates the invalid state, making it more reliable in practical applications.
It can toggle, set, reset, or hold its state based on the inputs and clock signal.
• The JK flip-flop has two inputs, J and K.
• J acts like the Set input, while K acts like the Reset input.
• Unlike the SR flip-flop, if both J and K are high (1), the JK flip-flop will
toggle its current state, instead of producing an undefined state.
• Similar to other flip-flops, the JK flip-flop operates based on the clock
signal (CLK).
• The state of the JK flip-flop changes only during the active edge of the
clock signal (either rising or falling, depending on the design).
• On each clock edge, the flip-flop checks the values of J and K and
determines the next state of the output based on the following conditions.
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result:
 Design and Simulation of 4-Bit Counter
Exp No: Date:

Aim: To design a 4-bit counter using Mentor Graphics - Tanner Tools v2021.2 and to
verify it’s timing simulation.
Software Required:
Mentor Graphics - Tanner Tools v2021.2
Hardware Required:
Personal Computer
Theory:
A 4-bit asynchronous counter, also known as a ripple counter, is a sequential
digital circuit that counts in binary from 0 to 15 (for a 4-bit counter) and then resets
back to 0. Asynchronous counters are called "ripple counters" because the clock signal
is applied only to the first flip-flop, and the toggling of other flip-flops happens
asynchronously in a ripple-like fashion as the output of one flip-flop triggers the next.
• A 4-bit asynchronous counter is typically built using 4 D or JK flip-flops, each
representing one bit of the counter (Q0, Q1, Q2, Q3).
• The flip-flops are connected in such a way that each flip-flop toggles when the
previous one makes a transition from 1 to 0 (falling edge).
• The clock signal is applied only to the first flip-flop (LSB flip-flop, Q0).
Subsequent flip-flops get their clock from the output of the previous flip-flop.
• The counter produces a 4-bit binary output, represented by Q3 (MSB), Q2,
Q1, and Q0 (LSB).
• The count starts from 0000 (0 in decimal) and continues up to 1111 (15 in
decimal), after which it resets back to 0000.

Clock
Q3 Q2 Q1 Q0 Binary Decimal
Pulse
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 10 2
3 0 0 1 1 11 3
4 0 1 0 0 100 4
... ... ... ... ... ... ...
15 1 1 1 1 1111 15
16 0 0 0 0 0 0
Procedure:
1. Create a New Cell for the Schematic Design
2. Design the required Schematic
3. Attach Input and Output Ports
4. Generate the Symbol for the Schematic Design
5. Create a Test Bench for Simulation
6. Insert the Design Symbol into the Test Bench
7. Connect Input and Output Ports to the Design Symbol
8. Add a DC Voltage Source (VDC)
9. Add VPULSE Source for Input Simulation
10. Set Parameters for Transient Analysis in the simulation setup
11. Add the Library File Path for simulation
12. Run the Simulation and Verify Timing Waveforms

Result: