IEEE SENSORS JOURNAL, VOL. 20, NO.

19, OCTOBER 1, 2020 11283

Residual Offset in Silicon Hall-Effect Sensor:

Analytical Formula, Stress Effects, and
Implications for Octagonal Hall
Plate Geometry
Arup Polley , Senior Member, IEEE, Srinath M. Ramaswamy, and Baher S. Haroun, Fellow, IEEE

Abstract —The Hall-effect magnetic sensors suffer from

large offset that is described by the resistance mismatch in
the Wheatstone bridge-like equivalent electrical circuit model
of the Hall plate. After a first order cancellation of the raw
offset using spinning current technique, a residual offset still
exists, significantly limiting the accuracy of the Hall sensor in
the detection of low magnetic field. In this paper we analyzed
the residual offset in silicon Hall sensor using a nonlinear
lumped resistor network model to derive a closed form expres-
sion. We further analyzed the residual offset in silicon Hall
sensor under the influence of stress. Using these results,
we show that eight-terminal, octagonal-shaped silicon Hall
sensors employing eight-phase spinning current technique
provide greater immunity to stress effects on residual offset
due to a second order cancellation compared to the conven-
tional four-phase spinning. The measurement results suggest
superior offset performance of eight-terminal silicon Hall
sensor.
Index Terms — Silicon Hall-effect sensor, offset voltage, continuous spinning current method, mechanical stress, piezo-
resistive effect.

I. I NTRODUCTION of an extremely low offset Hall magnetic sensor is critical to

address the market need.
T HE integrated Hall-effect sensors are by far the most
widely used magnetic sensor in the industry due to its
low cost, robustness and easy integration in CMOS processes.
Offset depends on multiple parameters such as temperature,
packaging stress, process variation and ageing. In literature,
According to [1], as of the year 2017, the size of the magnetic some of the reported low offset performances of integrated
sensing market is $1.756B with a compound annual growth silicon Hall sensor with signal processing chain are 40μT
rate of 7%. Hall-effect sensor dominates the magnetic sensors [2], 10μT [3], 3.65μT (3σ ) [4]. For standalone Hall sensor a
market with a share of ∼71%. There is an urgent need for residual offset of 2μT at 0.5V supply voltage has been reported
highly accurate, linear Hall magnetic sensors for current and [5]. The datasheet specification for offset in a Hall sensor-
position sensing applications for the power, automotive, indus- based current sensor shows a maximum offset of ∼75μT
trial market. There are two critical components of the Hall over temperature and ageing [6]. The residual offset has been
sensor accuracy – a) offset i.e. output at zero magnetic field investigated for vertical Hall sensors [7], 2DEG Hall sensors
and b) gain or sensitivity accuracy. Therefore, the development [8], anti-Hall bars [9], and three-terminal Hall sensors [5].
In silicon IC processes, Hall-effect sensors are built using
Manuscript received May 1, 2020; revised May 20, 2020; accepted lightly doped thin layer known as Hall plate. The Hall sensor
May 20, 2020. Date of publication May 25, 2020; date of current version
September 3, 2020. The associate editor coordinating the review of
is typically biased with constant voltage (Vbias ) or current
this article and approving it for publication was Prof. Boby George. (Ibias ) and a Hall voltage V H is developed across the sensing
(Corresponding author: Arup Polley.) terminal proportional to the magnetic field Bz perpendicular
The authors are with Texas Instruments Inc., Dallas, TX 75243 USA
(e-mail: [email protected]; [email protected]; [email protected]).
to the plane of the sensor (Fig. 1).
This article has supplementary downloadable material available at Hall absolute sensitivity S H is given by S H = ∂∂VBH =
http://ieeexplore.ieee.org, provided by the authors. SI Ibias = SV Vbias , where the current-related sensitivity SI is
Digital Object Identifier 10.1109/JSEN.2020.2997292
1558-1748 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 11284 IEEE SENSORS JOURNAL, VOL. 20, NO. 19, OCTOBER 1, 2020

Fig. 1. Schematic of Hall-effect sensor.

given by SI = G qnt r
[10], [11]. Here, G is a geometric factor
Fig. 2. Equivalent electrical circuit of 4-terminal Hall sensor.
that depends on the shape of the Hall plate and the relative
size of the contact regions and r is the Hall scattering factor,
a number close to unity [8], [10]. Moreover, n is the density of The magnetic field induced by the bias current through the
carriers, t is the thickness of the Hall plate and q is electronic Hall sensor leads (self-induced Hall voltage) and the thermo-
charge.  voltage-related sensitivity SV is given by SV =
 The electric effect due to the temperature gradient from resistive
Gr μ W L e f f [8], [10] where μ is the mobility of carriers heating in the Hall plate (Seebeck effect) also result in addi-
(electrons for n-type Hall plate), W and L are  width and length tional offset [16] (pp.32-33), [20]. However, a fourfold SCT
of the Hall plate as shown in Fig. 1 and W L e f f is the effective results in a complete cancellation of the induced offset due to
width to length ratio in an arbitrary Hall plate geometry. thermo-electric effect and partial cancellation of self-induced
Compared to SI which depends on Ibias due to junction Hall voltage [20]. In the specific case of [20], 26μT offset
thickness modulation, SV is quite independent of the bias. is induced for a bias current of 5mA per Hall device which
The equivalent electrical circuit model for four-terminal implies that quantitatively self-induced Hall voltage becomes
Hall sensor is given by a Wheatstone bridge-like network significant only at very high bias current. Furthermore, these
of 6 resistors (Fig. 2) [12], [13]. In spite of the geometrical effects can be reduced through careful and symmetric layout
symmetry, Hall sensors suffer from large offset voltage due considerations [16], [20]. However, in this paper we focus
to inevitable reasons such as doping gradient, lithographic on the effect of electrical nonlinearity on residual offset and
mismatch, and stress etc. and these effects can be modeled ignore the thermal effects.
as the mismatch in the resistances of the equivalent circuit. Stress in the Hall plate induces mismatches in the resistors
Two widely-employed offset cancelling techniques in typical of the Wheatstone bridge model through piezo-resistive effect
Hall sensors with 90◦ rotational symmetry are orthogonal cou- and the induced resistor mismatch results in offset [14], [16],
pling (OC) and spinning current technique (SCT) [14]. Both [21], [22]. It has also been shown in these references, that
these techniques use the fact that for a linear resistor mismatch, to a first order, the stress-induced offsets cancel when a SCT
offsets of two orthogonal current directions exactly cancel each is employed. However, the effect of stress on residual offset
other. OC uses spatial averaging by electrically connecting in the presence of nonlinearity of the Hall plate resistance
multiple (typically four) Hall elements for orthogonal current has not been investigated. The primary reason for stress in
directions. SCT uses time averaging where current directions silicon Hall sensor devices is the thermo-mechanical stress in
are switched at a constant frequency called spinning frequency the package due to the difference in the coefficients of thermal
( f spin ) and the corresponding outputs are averaged to obtain expansion of the packaging materials [23]. The stress in the
the final Hall output. The offset obtained after applying SCT molded Hall sensors changes over time due the temperature
is known as the residual offset (RO). effects as well as humidity affecting the material properties
The origin of offset and the factors affecting the residual of the mold materials [24], [25]. Thus, the offset drifts over
offset have been investigated previously in many literatures the lifetime of the packaged Hall sensor degrading the overall
[12]–[22]. It has been shown that in Hall sensors employing offset performance.
SCT, the voltage nonlinearity of the Hall plate resistance and The shape of the Hall plate influences the Hall sensitivity
the mismatch in the resistors of the equivalent circuit result through the geometrical factor G. There have also been
in residual offset. The voltage nonlinearity may arise due to simulation and experimental studies to understand the impact
the PN junction thickness variation between the Hall plate and of Hall plate geometry, size and contacts on the residual offset
substrate [10], [13]. This origin of RO has been demonstrated [8], [26], [27]. However, the results on the effects of Hall
via simulation of both physics-based model [13], [17], [18] and geometry remain mostly inconclusive and further lack any
statistical model [19]. It has also been shown that the SCT is insight. Octagon-shaped Hall sensor employing eight-phase
more effective in the constant current bias (Ibias ) mode [17], spinning has been demonstrated to obtain low offset [4], [28].
[19]. However, no closed form expression of residual offset However, octagonal Hall sensor has not been popular in the
exists in the literature that provides a 1st -order dependence on industry and literature due a few reasons. Firstly, the geometric
the key contributing factors. factor G of octagonal Hall sensor is slightly smaller and results

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 POLLEY et al.: RESIDUAL OFFSET IN SILICON HALL-EFFECT SENSOR: ANALYTICAL FORMULA, STRESS EFFECTS, AND IMPLICATIONS 11285

in lower sensitivity. More importantly, the 8-phase spinning at zero terminal voltages (i.e. R120 , R230 , R340 , and R140 ) is
reduces the bandwidth available from an octagonal Hall sensor Rs0 whereas the nominal value of the diagonal resistances
to half of that from a four-phase spinning Hall sensor. Finally, at zero terminal voltage (i.e. R130 , and R240 ) is Rd0 . The
in spite of the experimental evidence, the reasons for better equivalent circuit is valid for single Hall device as well as
offset performance of octagonal Hall sensors have not been for typical composite Hall sensor with multiple Hall devices
addressed. connected in parallel. In the case of composite Hall sensor,
In this paper we have addressed the above three issues – the equivalent resistor between terminals of the composite
a) a closed-from expression for residual offset due to electrical Hall sensor is simply the parallel equivalent of the resistors
non-linearity b) an analysis of residual offset in the presence of constituent Hall devices. The nominal values scale and the
of stress and c) an explanation for the superior residual offset mismatches statistically reduce in the case of a composite Hall
performance of octagonal Hall sensor. We perform a paper- sensor in comparison to the single Hall device.
pencil analysis of the residual offset using the Hall sensor The network of nonlinear resistors is solved for terminal
equivalent circuit with six nonlinear resistors and provide a voltages for the case of constant current bias (Ibias ). Initially,
closed-form expression for the residual offset. The results are the solution is found for α = 0. The 0th order (α = 0) offset
described in section II. In section III, we describe measure- V42,0 for the example configuration shown in Fig. 2 is given by
ment results and modeling efforts to validate the analytical R130 R240 (R140 R230 − R120 R340 )
results of section II. Then we further extend the analysis to V42,0 = Ibias (3)
D0
incorporate the effect of stress on residual offset in section
IV. In section V, we use the results in section IV to show where the denominator D0 is given by
that the RO of octagonal Hall sensor employing eight-phase
D0 = R130 R240 (R120 + R230 + R340 + R140 )
spinning provides significant immunity to the stress effects.
In section VI we show the measurement results demonstrating + R130 (R120 + R140 ) (R230 + R340 )
superior offset performance of octagonal Hall sensors with + R240 (R120 + R230 ) (R140 + R340 )
eight-phase spinning compared to four-phase spinning. The + (R120 R230 R340 + R230 R340 R140 + R340 R140 R120
paper is concluded in section VII.
+R140 R120 R230 )
II. R ESIDUAL O FFSET IN S EMICONDUCTOR ≈ 4Rs0 (Rs0 + Rd0 )2 (4)
H ALL S ENSOR It is evident from Eq. (3) that the residual offset with zero
The 6 nonlinear resistors in the Hall sensor equivalent circuit nonlinearity is zero as expected from any network of linear
(Fig. 2) are R12 , R23 , R34 , R14 , R13 , and R24 . The terminal resistors.
voltages are V1 , V2 , V3 and V4 . The output V42 (= V4 -V2 ) is The 0th order (α = 0) results are used to find the changes in
sensed across terminals 4 and 2 for the bias current input Ibias the terminal voltages (V 42 ) due to the nonlinearity (α =0) to
at terminal 3 and ground reference at terminal 1. The residual a 1st order approximation. Using these changes in the terminal
offset voltage, V R O , is defined as, voltages, the 1st order approximate solution of residual offset
(V42 + V13 + V24 + V31 ) V R O with α =0 is obtained.
VR O = (1)
4 α Ibias
2 R
1
where, V24 , V13 , V31 are the sensed differential voltages corre- VR O = (5)
4D02
sponding to bias currents at terminals 1, 4 and 2 respectively
(Fig. 2). where R1 is a resistance mismatch factor given by
One of the sources of nonlinearity of the resistors in the R1 = R130 R240 (R140 R 230 − R 120 R340 )
Hall model is the PN junction thickness variation along the
Hall plate. The exact expression for that type of nonlinearity × [R130 R 240 (R140 − R230 ) (R120 − R340 )
can be obtained from the physics-based model incorporating + (R130 − R240 ) (R120 R230 R340 + R230 R340 R140
the junction thickness dependence on voltage as given by +R340 R140 R 120 + R140 R 120 R230 )] . (6)
Eq. (10)-(12) in [13]. However, to simplify the analysis and
to obtain a tractable result, a 1st order nonlinearity coefficient Eq. (5) and (6) constitute the first reported closed-form expres-
α is assumed [19]. Eq. (2) shows the form of nonlinearity for sion for the residual offset of a silicon Hall-effect sensor.
all resistors in the network A few illuminating facts can be readily observed. Firstly,
   it shows that the residual offset in voltage is proportional to
Rab = Rab0 1 + α (Va + Vb ) 2 (2) the nonlinearity factor and square of the bias current. For a
where Rab is the resistance between terminals a and b with perfectly matched Hall sensor (R0 = 0), the residual offset
terminal voltages Va and Vb respectively. Rab0 is the resistance even in the presence of nonlinearity is zero. Therefore, residual
for zero terminal voltages. Guided by Eq. (2) the resistances offset can be significantly improved by careful layout practices
at zero terminal voltages are R120 , R230 , R340 , R140 , R130 , that reduce the overall mismatch effects.
and R240 for the corresponding resistors in Fig. 2. The exact The voltage bias Vbias = Ibias Rin , where Rin is the Hall
resistor values include deviations due to mismatch from the biasing resistance. Using (2) the zero terminal
 voltage value of
Rin0
nominal resistances. The nominal value for the side resistances Rbias can be rewritten as Rin ≈ Rin0 1 + α 2 Ibias where

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 11286 IEEE SENSORS JOURNAL, VOL. 20, NO. 19, OCTOBER 1, 2020

Fig. 3. Experimental setup.

Rin0 = Rs0 Rd0 /(Rs0 + Rd0 ). Thus the offset in magnetic field
unit can be written as: Fig. 4. Representative residual offset vs. bias current/voltage.
α Ibias R1 TABLE I
BR O =  . (7)
E XTRACTED M ODEL PARAMETERS OF H ALL S ENSOR
4D02 SV R in0 1 + α Rin0
2 I bias

For the range of current bias Ibias constrained by the available

voltage headroom and the minimum detectable magnetic field,
the residual offset in magnetic field units is approximately
proportional to the bias current. Thus there is also a trade-off
between Hall sensitivity and residual offset that influences the
optimum range of bias current.
It is noted that both the nonlinearity coefficient α and
resistance mismatch have positive temperature coefficients consistent with Eq. (5). The square-law dependence of the RO
and result in increasing RO at higher temperature. This effect has been reported previously [15]. The sign and amplitude of
can be easily included in the residual offset expression of the RO is dependent on the mismatch parameter R1 and is
Eq. (5) with appropriate form of temperature dependence of specific to each device.
α and R1 . The I-V characteristics of each device are used in IC-CAP
(Integrated Circuit Characterization and Analysis Program)
III. M EASUREMENT R ESULTS – R ESIDUAL O FFSET device modeling software to extract the optimum values of
We designed and fabricated Hall sensor devices in 0.35μm the parameters α, R120 , R230 , R340 , R140 , R130 , and R240
CMOS process to verify the validity of the residual offset corresponding to the equivalent circuit of Hall sensor device
model described in section II. The conventional design of the as shown in Fig. 2. The average extracted parameters obtained
Hall sensor comprised of four parallel, orthogonally coupled for 10 devices are summarized in Table I.
individual Hall devices is implemented. The individual Hall The resistor mismatch parameters for diagonal (δ Rd0 /Rd0 )
devices are of cross-type geometry (Fig. 1) with a width (W ) and side resistor (δ Rs0 /Rs0 ) in Table I are the standard devi-
of 36.4μm and length (L) of 73.5μm. ation from the average extracted value. The Hall plate used
The schematic of the measurement setup is shown in Fig. 3. in the design is a thin NWELL in P-type substrate. The
The Hall sensors are characterized for both electrical offset and nonlinearity coefficient and the resistor mismatch value of the
resistance (Rin ) at room temperature inside a magnetically Hall model obtained are closely correlated to the nonlinearity
shielded (zero-Gauss) chamber. The zero-Gauss chamber is coefficients and resistance mismatch of the corresponding
fully heat-treated mu-metal chamber with three layers and NWELL resistors with similar value and area.
provides >53dB attenuation from external magnetic field. For Using Eq. (5) and (6) and performing a sensitivity analysis,
each bias direction, the biasing current of the Hall sensor an expression for the standard deviation of RO (δV R O ) is
is increased from 0 to 1.6mA and all terminal voltages are obtained.
measured accurately giving both bias and offset voltages. The α Ibias
2
δ Rd0 δ Rs0 3 R3
Rs0 d0
measurements are repeated for all four bias directions. For high δV R O = (8)
2 Rd0 Rs0 (Rs0 + Rd0 )4
and low temperature measurements, the zero-Gauss chamber
is placed inside a thermal chamber. This equation provides a good estimate of the expected RO
The RO is calculated for each bias current using Eq. (1). from a nominal Hall sensor design parameter. For example,
Fig. 4 shows the RO for 3 representative devices along with using the parameters of Table I and a bias current (Ibias )
the nominal bias voltages for the applied bias currents. The RO of 1.2mA provides an expected δV R O of 1.5μV which is
shows a nominal square-law dependence on the bias current commensurate with the measurement results.

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 POLLEY et al.: RESIDUAL OFFSET IN SILICON HALL-EFFECT SENSOR: ANALYTICAL FORMULA, STRESS EFFECTS, AND IMPLICATIONS 11287

Fig. 5. Crystal surface and current direction in silicon.

TABLE II Fig. 6. Hall sensor on [001] silicon and corresponding equivalent

P IEZO -R ESISTIVE C OEFFICIENTS IN L IGHTLY circuit.
D OPED S ILICON AT 300K [30]
i.e. R(ϕ) = R(ϕ + π). Therefore, resistance change is same
for both current directions along a resistor. This ensures that
for all spinning directions the resistance change is same for a
Hall sensor with 90◦ rotational symmetry.
We consider the layout of a typical cross-shaped Hall sensor
with bias current directions along [100] and [010] as shown
IV. S TRESS E FFECTS IN S ILICON H ALL S ENSORS in Fig. 6. The diagonal resistors R24 and R13 are along [100]
The offset of silicon Hall-effect sensor is affected by stress and [010] respectively. The side resistors R23 and R14 are
through piezo-resistance effect [21]. Although the current along [110], while R12 and R34 are along [1̄10]. The lumped
distribution in a Hall device is non-uniform and dependent resistor model of the Hall-effect sensor does not replicate
on magnetic field, the piezo-resistive effect can be approxi- quantitatively accurately the current flow in the actual device.
mately incorporated by introducing the stress-induced change Apart from the angle dependence, the stress response of the
in the resistors of the equivalent circuit. These stress-induced equivalent resistors is also dependent on the geometry of the
resistance mismatches create the raw offset. To quantify the Hall plate and the size of contacts [31]. For typical Hall plate
resistance changes, the piezo-resistance tensor formalism is geometries and medium contact sizes, the piezo-resistive
used [21], [29]. behavior of the equivalent resistors is similar to that of a
In typical silicon processes, the devices are developed on rectangular resistor with appropriate orientation [31]. The
the [001] surface and the current flows along [100] and [110] spatial angle ϕ the resistors make with axis [110] following
and orthogonal directions to them. The axes system is shown the Fig. 5 is shown Table III. Substituting the angle ϕ
in Fig. 5. Apart from the stress, the change in resistivity in Eq. (9), the changes in resistors are obtained in the
ρ (ϕ) [21], [22], [29] is dependent on the direction of the form:
current flow i.e. the direction of the modeled lumped resistor stress
in the equivalent circuit as shown in Eq. (9). The current or R −→ R (1 + σ ) (10)
resistor direction ϕ is measured from the axis direction [110] where, σ is the coefficient of resistance change R under
as indicated in Fig. 5. the influence of a specific stress σ given by a set of stress
 
1 tensor values. The evaluation of Eq. (9) with angles ϕ in
ρ(ϕ)/ρ̄ = (π11 + π12 )(σ1 + σ2 ) + π12 σ3 Table III shows that σ for different resistor components
2
1 of the model can be expressed as combinations of three
+ (π11 +π12 )σ6 sin(2ϕ)+ π44 (σ1 − σ2 ) cos(2ϕ) stress dependent parameters 1 , 2 and 3 , the values
2
(9) of which can be computed using Eq. (11). For resistors
in equivalent circuit model of the Hall sensor shown in
Here, ρ̄ is the average nominal resistivity. The piezo-resistance Fig. 6, the expressions for coefficient of resistance change
tensors π11 , π12 ,π44 and stress tensors σ1 , σ2 , σ3 , σ6 , use (σ = R/R) are shown in Table III.
reduced index convention. The reduced index convention fol- 
lows 11∼1, 22∼2, 33∼3, 13∼4, 23∼5, 12∼6, where 1, 2, and 1 = (π11 + π12 ) (σ1 + σ2 ) 2 + π12 σ3
3 stand for x, y, and z respectively. Thus, σ1 , σ2 , σ3 are axial 2 = (π11 − π12 ) σ6
stress along x, y and z directions respectively and σ6 is the 
3 = π44 (σ1 − σ2 ) 2 (11)
shear stress in x-y plane. Typical values of the piezo-resistive
coefficients in silicon are shown in Table II. The stress effects induce mismatch due to the change in
It is obvious from Eq. (9) that the effect of stress on resistors as given by Eq. (10), (11). For example, the stress-
change in resistivity is second harmonic in spatial angle ϕ. induced resistor mismatch between side resistors R12 and R23

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 11288 IEEE SENSORS JOURNAL, VOL. 20, NO. 19, OCTOBER 1, 2020

TABLE III
C HANGE IN R ESISTOR OF E QUIVALENT
C IRCUIT M ODEL OF F IG . 6

is given by 23 , whereas the mismatch between diagonal

resistors R13 and R24 is given by 22 . Considering a typical Fig. 7. Eight-terminal octagonal-shaped Hall sensor in silicon and two
high stress condition of σ1 = 100Pa, σ2 = −30Pa, σ3 = 1.8Pa, separate equivalent circuit models for two sets of 4-phase spinning – a)
orthogonal/[100], b) diagonal/[110].
and σ6 = 0.2Pa [22], [23] and using the piezo-resistive
coefficients for N-type silicon from Table II, the values of 1 ,
reverse; b) mode [110]/diagonal: employs 4-phase spinning
2 and 3 are evaluated to be -1.61%, -0.031% and -0.884%
with current bias along [110], [1̄10] and reverse. The Eq. (14)
respectively. These stress-induced mismatches add to the initial
shows the relation among residual offsets for octagonal Hall
unstressed mismatches in producing the total residual offset
sensors (V R O,oct ) and mode [100] (V R O,100 ) and mode [110]
following Eq. (4)-(6). It is possible to include both the effects
(V R O,110). Here, Vo (ϕ), is the offset voltage with bias current
of different mismatches in a numerical simulation. However,
from the direction of angle ϕ as defined in Fig. 5.
assuming no initial mismatch and using only the stress-induced
mismatch produce illuminating result. It is also noted that with V R O,100 + V R O,110
V R O,oct =
advanced technology nodes, the resistance mismatch related to 2  
     
the lithography and doping gradient becomes less significant. Vo π4 + Vo 3π 4 + Vo
5π
4 + Vo 7π 4
Now we consider the nominal and no-mismatch values of V R O,100 =
all resistors in the Hall sensor equivalent circuit and apply the   4  
Vo (0) + Vo π2 + Vo (π) + Vo 3π
appropriate changes in resistor values induced by mismatch V R O,110 = 2
(14)
according to Table III and Eq. (11) as shown in Eq. (12). 4
σ Octagonal Hall sensor with 8-phase spinning has been
R120 = R230 = R340 = R140 = Rs0 −→ Rs0 (1 + σ ) demonstrated [4] to achieve extremely low offset of 3.65μT
σ
R130 = R240 = Rd0 −→ Rd0 (1 + σ ) (12) (3σ ) compared to the typical offsets of ∼40-75μT in four-
terminal Hall sensors [2], [5]. In [28], experimental results
Applying the resistor changes in residual offset Eq. (4)-(6), from 4 samples of eight-terminal octagonal Hall sensors at
the following expression for the stress-induced residual offset room temperature are provided that show the 8-phase RO
(V R O,100 ) is obtained: consistently produces smaller offset compared to the 4-phase
α Ibias
2 3 R3
Rd0 s0
RO of both modes described above. In [21] it is argued that the
V R O,100 ≈ − 2 3 (13) offset arising due to stress through piezo-resistance is second-
2 (Rd0 + Rs0 )4
harmonic in spatial angle and therefore, applying SCT with
The above expression for RO is similar to the expression 8-phase spinning cancels the raw offset. However, even 4-
of Eq. (8) with 2 and 3 in place of diagonal and side phase spinning would be equally effective in canceling offset
resistance mismatch ratios respectively. The Eq. (13) is valid that is strictly second and higher harmonic in spatial angle as
only under no initial mismatch and for Hall sensor orientation concluded in [22].
corresponding to Fig. 6. Although for stress-induced offset, We apply the residual offset model based on resistor
the mismatches and therefore, the raw offsets are dependent on nonlinearity and stress-induced resistor mismatch developed
the current direction, the composite Hall sensor with multiple in section IV to understand the residual offset behavior of
orthogonally coupled Hall devices obey Eq. (13) following the eight-terminal octagonal Hall sensor. Although there are eight
linear superposition principle. terminals for the two modes of the octagonal Hall sensors,
only four terminals of one of the modes are accessed at a
V. E IGHT-T ERMINAL O CTAGONAL H ALL S ENSOR time. Therefore, the 8-terminal octagonal Hall sensor can be
The conventional Hall sensor has a 90◦ rotational symmetry represented by two 4-terminal models similar to the ones
with four terminals and employs 4-phase spinning of bias developed earlier. The equivalent circuit models for the two
current. In comparison, octagon-shaped Hall sensor with 45◦ modes of octagonal Hall sensor are also shown in Fig. 7.

rotational symmetry and eight terminals can employ 8-phase The resistors for the two networks are different; Rxx and Rxx
spinning for bias current to obtain RO [4], [21], [28]. for the orthogonal and diagonal modes respectively. However,
An octagonal Hall sensor can be viewed as consisting the nominal, unstressed values for the side and diagonal
of two 4-phase spinning Hall sensors within one Hall plate resistors are same for the both modes following Eq. (9).
as shown in Fig. 7 – a) mode [100]/orthogonal: employs The stress-induced residual offset analysis of [100]/orthog-
4-phase spinning with current bias along [100], [010] and onal mode of octagonal Hall sensor is exactly the same as

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 POLLEY et al.: RESIDUAL OFFSET IN SILICON HALL-EFFECT SENSOR: ANALYTICAL FORMULA, STRESS EFFECTS, AND IMPLICATIONS 11289

TABLE IV
C HANGE IN R ESISTOR OF E QUIVALENT C IRCUIT M ODEL OF F IG . 7b

described in section IV and generates V R O,100 (Eq. (13))

after 4-phase spinning. A similar analysis of [110]/diagonal
mode of the octagonal Hall sensor based on the equivalent Fig. 8. a) Single octagonal-shaped, eight-terminal Hall device and
circuit model shown in Fig. 7b can be performed to obtain an b) Hall sensor with four parallel, orthogonally coupled octagon Hall
devices.
expression of residual offset V R O,110 after 4-phase spinning.
The orientations of the resistors (Fig. 7b) and the expressions
for coefficient of resistance change (σ = R/R) are shown
in Table IV. The stress-dependent parameters are again given
by Eq. (11).
It is found that the residual offsets V R O,110 and V R O,100
cancel each other.
V R O,110 ≈ −V R O,100 (15)
From Eq. (14), after 8-phase spinning, the octagonal Hall
sensor generates extremely low offset due to a 2nd order
cancellation and provides great immunity to stress-induced
offset.
The raw offsets of [100] and [110] are given by the
following equations:
α Ibias Rd2 Rs
Vo f f set,100 ∼ 3
(Rd + Rs )2
α Ibias Rd2 Rs
Vo f f set,110 ∼ 2 (16)
(Rd + Rs )2
Therefore,  the ratio of raw offsets are found to be
Vo f f set,100 Vo f f set,110 ∼ 3 2 . For the specific values
of 2 and 3 evaluated in the section IV, the ratio
3 2 ∼ 28.5. This shows that although raw offsets of the
two modes are widely different, the residual offsets of the two
modes are quantitatively close.
It should be noted that the analysis is approximate and also
ignores the other sources of mismatch such as lithographic and
doping gradient.

VI. M EASUREMENT R ESULTS –O CTAGONAL

H ALL S ENSOR
We designed octagonal Hall sensor in 180nm CMOS Fig. 9. a) Mean RO drift and b) standard deviation RO of 21 octagon
Hall sensors with 4-phase spinning in orthogonal and diagonal mode and
process with lower lithographic mismatch compared to 8-phase spinning octagonal mode.
0.35μm or longer minimum feature length processes. The
sensor is comprised of four parallel, orthogonally coupled,
octagonal-shaped, eight-terminal Hall devices with nominally metal layers and silicon substrate. The raw offsets for all
50μm diameter for the individual Hall plate (Fig. 8). Care is eight current bias directions are measured over temperatures
taken for symmetric layout and ranging from −55 to 150 ◦ C at a constant current bias
Although in section V, the octagonal Hall sensor is shown of 1.2mA. The sensitivity of the octagonal Hall sensors
to be resilient to stress effects, due to experimental limitations, is measured to be 580V/AT at room temperature. The RO
the temperature sensitivity of RO is measured. The change are calculated for 4-phase spinning in orthogonal ([100]),
in temperature also introduces a change in uncalibrated stress diagonal ([110]) modes and 8-phase spinning in octagonal
due to the difference in thermal expansion coefficients of mode. Mean RO drift from the value at room temperature

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 11290 IEEE SENSORS JOURNAL, VOL. 20, NO. 19, OCTOBER 1, 2020

and standard deviation of RO for 21 Hall sensors are shown [9] R. G. Mani and K. von Klitzing, “Hall effect under null cur-
in Fig. 9a) and b) respectively. rent conditions,” Appl. Phys. Lett., vol. 64, no. 10, pp. 1262–1264,
Mar. 1994.
The mean RO at 150 ◦ C of orthogonal and diagonal [10] R. S. Popović, “Hall-effect devices,” Sens. Actuators, vol. 17, nos. 1–2,
modes are −30μT and 20μT respectively, whereas the eight- pp. 39–53, May 1989.
phase RO of octagonal mode is only −5μT. The standard [11] J. Schweda and K. Riedling, “A nonlinear simulation model of integrated
Hall devices in CMOS silicon technology,” in Proc. IEEE Int. Workshop
deviation of RO of both orthogonal and diagonal modes Behav. Modeling Simulation (BMAS), Santa Rosa, CA, USA, Oct. 2002,
is ∼60μT whereas standard deviation of RO of octagonal pp. 14–20.
mode is ∼37μT. The results demonstrate that the 8-phase [12] R. S. Vanha, F. Kroener, T. Olbrich, R. Baresch, and H. Baltes, “Trench-
Hall devices,” J. Microelectromech. Syst., vol. 9, no. 1, pp. 82–87,
spinning of octagonal Hall sensor provides lower drift of RO Mar. 2000.
over temperature as well as lower offset spread over process [13] M. Madec, J. B. Kammerer, L. Hébrard, and C. Lallement, “An
variation. accurate compact model for CMOS cross-shaped Hall effect sen-
sors,” Sens. Actuators A, Phys., vol. 171, no. 2, pp. 69–78,
An appropriate analog frontend with 8-phase spinning Nov. 2011.
octagonal Hall sensor would result in at least >3x [14] P. Munter, “Spinning-current method for offset reduction in silicon
improvement in the offset accuracy compared to the Hall plates,” Ph.D. dissertation, Dept. Elect. Eng., Univ. Delft, Delft,
The Netherlands, 1992.
state-of-the-art. [15] P. J. A. Munter, “A low-offset spinning-current Hall plate,”
Sens. Actuators A, Phys., vol. 22, nos. 1–3, pp. 743–746,
VII. C ONCLUSION Jun. 1990.
[16] A. A. Bellekom, “Origins of offset in conventional and spinning-current
The origin of residual offset of Hall sensor employing spin- Hall plates,” Ph.D. dissertation, Dept. Elect. Eng., Univ. Delft, Delft,
ning current technique with constant current bias is attributed The Netherlands, 1998.
to mismatch and voltage nonlinearity of resistors of Hall plate [17] M. Madec, J.-B. Kammerer, L. Hebrard, and C. Lallement, “Analy-
sis of the efficiency of spinning-current techniques thru compact
electrical equivalent circuit. We report a closed-form analytical modeling,” in Proc. IEEE SENSORS, Limerick, Ireland, Oct. 2011,
expression of the residual offset that not only provides insight pp. 542–545.
into the dependence on critical process and design parameters [18] M. Madec, J.-B. Kammerer, L. Hébrard, and C. Lallement,
“An improved compact model for CMOS cross-shaped Hall-effect sensor
but also helps to obtain a 1st order estimation of the expected including offset and temperature effects,” Anal. Integr. Circuits Signal
residual offset. We explored the effect of stress-induced resis- Process., vol. 73, no. 3, pp. 719–730, Dec. 2012.
tance mismatch on residual offset and derived an expression [19] U. Ausserlechner, “Limits of offset cancellation by the principle of
spinning current Hall probe,” in Proc. IEEE SENSORS, Vienna, Austria,
for residual offset of a perfectly matched Hall sensor under vol. 3, Oct. 2004, pp. 1117–1120.
stress. Finally, through analysis and measurement results we [20] P. Ruther, U. Schiller, R. Janke, and O. Paul, “Thermomagnetic resid-
demonstrated that octagonal Hall sensor employing 8-phase ual offset in integrated Hall plates,” IEEE Sensors J., vol. 3, no. 6,
spinning current results in extremely low residual offset with pp. 693–699, Dec. 2003.
[21] S. Bellekom and L. Sarro, “Offset reduction of Hall plates in three
high immunity to stress. different crystal planes,” in Proc. Int. Solid State Sens. Actuators Conf.
(Transducers), Chicago, IL, USA, Jun. 1997, pp. 233–236.
ACKNOWLEDGMENT [22] R. Steiner, C. Maier, M. Mayer, S. Bellekom, and H. Baltes, “Influence
of mechanical stress on the offset voltage of Hall devices operated
The authors would like thank K. Green, D. Garcia, with spinning current method,” J. Microelectromech. Syst., vol. 8, no. 4,
W. Culpepper, B. Bahr, and C. Rush for their support at pp. 466–472, 1999.
various phases of the Project. [23] S. Fischer and J. Wilde, “Modeling package-induced effects on molded
Hall sensors,” IEEE Trans. Adv. Packag., vol. 31, no. 3, pp. 594–603,
Aug. 2008.
R EFERENCES [24] U. Ausserlechner, M. Motz, and M. Holliber, “Drift of magnetic
[1] Magnetic Sensors Market and Technologies 2017, Yole Developpement, sensitivity of smart Hall sensors due to moisture absorbed by the
Lyon, France, 2017. IC-package,” in Proc. IEEE SENSORS, Vienna, Austria, Oct. 2004,
[2] J. Jiang and K. A. A. Makinwa, “Multipath wide-bandwidth CMOS pp. 455–458.
magnetic sensors,” IEEE J. Solid-State Circuits, vol. 52, no. 1, [25] J. M. Cesaretti, W. P. Taylor, G. Monreal, and O. Brand, “Effect
pp. 198–209, Jan. 2017. of stress due to plastic package moisture absorption in Hall
[3] M. Motz et al., “A miniature digital current sensor with differen- sensors,” IEEE Trans. Magn., vol. 45, no. 10, pp. 4482–4485,
tial Hall probes using enhanced chopping techniques and mechan- Oct. 2009.
ical stress compensation,” in Proc. IEEE SENSORS, Oct. 2012, [26] M.-A. Paun, J.-M. Sallese, and M. Kayal, “Offset and drift analysis
pp. 1–4. of the Hall effect sensors. The geometrical parameters influence,” Dig.
[4] J. C. Van der Meer, F. R. Riedijk, E. V. Kampen, K. A. A. Makinwa, and J. Nanomater. Biostruct. (DJNB), vol. 7, no. 3, pp. 883–891,
J. H. Huijsing, “ A fully integrated CMOS Hall sensor with a 3.65 /muT Jul./Sep. 2012.
3σ offset for compass applications,” in IEEE Int. Solid-State Circuits [27] M.-A. Paun, J.-M. Sallese, and M. Kayal, “Offset drift dependence of
Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2005, Hall cells with their designed geometry,” Int. J. Electron. Telecommun.,
pp. 246–247. vol. 59, no. 2, pp. 169–175, Jun. 2013.
[5] U. Ausserlechner, “Hall effect devices with three terminals: Their mag- [28] J. Ramirez and F. Fruett, “Offset reduction in a multiple-terminal Hall
netic sensitivity and offset cancellation scheme,” J. Sensors, vol. 2016, plate using current spinning,” in Proc. IEEE 9th IberoAmer. Congr.
pp. 1–16, Jan. 2016. Sensors, Bogota, Colombia, Oct. 2014, pp. 1–4.
[6] Hall-Effect Current Sensor Datasheet: ACS 723. Accessed: [29] Y. Kanda, “A graphical representation of the piezoresistance coefficients
Jun. 8, 2020. [Online]. Available: https://www.allegromicro.com/~/ in silicon,” IEEE Trans. Electron Devices, vol. ED-29, no. 1, pp. 64–70,
media/Files/Datasheets/ACS723-Datasheet.ashx Jan. 1982.
[7] O. Paul, R. Raz, and T. Kaufmann, “Analysis of the offset of semi- [30] J. M. Cesaretti, “Mechanical stress and stress compensation in Hall
conductor vertical Hall devices,” Sens. Actuators A, Phys., vol. 174, sensors,” Ph.D. dissertation, Georgia Inst. Technology, Atlanta, Georgia,
pp. 24–32, Feb. 2012. 2008.
[8] H. S. Alpert et al., “Effect of geometry on sensitivity and offset of [31] U. Ausserlechner, “An analytical theory of piezoresistive effects in Hall
AlGaN/GaN and InAlN/GaN Hall-effect sensors,” IEEE Sensors J., plates with large contacts,” Adv. Condens. Matter Phys., vol. 2018,
vol. 19, no. 10, pp. 3640–3646, May 2019. pp. 1–24, Jun. 2018.

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.
 POLLEY et al.: RESIDUAL OFFSET IN SILICON HALL-EFFECT SENSOR: ANALYTICAL FORMULA, STRESS EFFECTS, AND IMPLICATIONS 11291

Arup Polley (Senior Member, IEEE) received Baher S. Haroun (Fellow, IEEE) received the
the B.Tech. degree in electronics and electrical B.Sc. degree in EE and the M.Sc. degree from
communication engineering from the Indian Insti- Ain Shams University Cairo, Egypt, and the Ph.D.
tute of Technology Kharagpur, Kharagpur, India, degree from the University of Waterloo, ON,
in 2003, and the M.S. degree in physics and the Canada, in 1990.
Ph.D. degree in electrical engineering from the He is an elected Senior Fellow with Texas
Georgia Institute of Technology in 2008. Instruments Inc., and the Director of the Signal
He is currently a Research Engineer with Path at Kilby Labs at TI. He over his years at
Kilby Research Labs, Dallas at Texas Instru- TI has led multiple Research and Development
ments. From 2003 to 2008, he was a member projects in high-performance wireless systems,
of the Ultrafast Optical Communications Labora- ADCs, DACs, mmWave/THz RF, high-precision
tory, Georgia Institute of Technology, where he researched on holistic clocks/PLLs, Gbps SerDes, efficient RF digital power amplifiers and
approaches for low-cost, high-speed multimode optical link involving co- ultrasonic, and optical and mmWave radar sensing circuits and systems.
development of transceiver and plastic optical fiber. In 2009, he joined From 1998 to 2009, he has lead Worldwide design teams for Analog,
the Storage Product Group at Texas Instruments, Dallas, where he power management and RF CMOS integration in TI Wireless BU over
developed advanced fly height sensing system for Hard Disk Drives. six digital CMOS processes (from 0.18 μm to 28 nm) nodes for billions
He joined Kilby Research Labs in 2012, where he first developed a of wireless devices in the market. Since 2009, he has helped create and
low-power sensor platform for wearable devices. He is currently working direct multiple teams in TI Kilby Labs. He joined Texas Instruments with
on non-contact magnetic current sensor systems and development of the Mixed Signal Group, in 1995, after being an Assistant Professor and
high-speed, integrated CMOS Hall-effect sensor. He also leads TI’s an Associate Professor with Concordia University, Montreal, Canada,
internal and collaborative research on the applications of two dimensional from 1989 to 1995. He has over 150 issued patents and more than
materials. His current research interests include sensor systems and 50 published IEEE articles and was presenter. He has served as
electronic applications of two dimensional materials. He has authored a session chair, given invited talks and has been a panel speaker,
and coauthored over 30 journal and conference publications, and holds a member of technical committees and a Reviewer for multiple IEEE
20 granted U.S. patents. conferences including ISSCC and ESSIRC.

Srinath M. Ramaswamy received the B.S.

degree in instrumentation and control engineer-
ing from the University of Calicut, Malappuram,
India, in 1995, and the M.S. degree in electri-
cal engineering from Arizona State University,
Tempe, in 1999.
He joined the Wireless Terminal Business Unit,
Texas Instruments Inc., Dallas, TX, in 1999,
working on audio codecs, class-D audio ampli-
fiers, data converters and wireless transceivers.
He joined Kilby Labs in 2009, where he worked
on >100GHz transceivers in ultra-deep submicron technologies for radar
and μW medical signal processing systems. His current research inter-
ests include ultra-low power sensor interfaces & systems in ultrasonics,
optics & magnetics, IC design for wireless communication & ranging and
mixed signal circuits & signal processing architectures for a wide variety
of applications. He is currently a Distinguished Member and a Technical
Staff at Texas Instruments.

Authorized licensed use limited to: National Yang Ming Chiao Tung University. Downloaded on October 31,2024 at 07:55:16 UTC from IEEE Xplore. Restrictions apply.