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Material protected by copyright licensed to BR Dem 60730-1 0 IEC:2013 — 191 — Table H.1
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Component "Failure/Error Class of software Example of acceptable measures ° ’ Definitions 1.4
Addressing CC Failure 1.5 Data paths CC Failure Instruction Y Decrypt Execution 2. Interrupt
handling and Execution B Without interruption Rq or also Frequent Interrupt Without interruption or
also Frequent Interrupt related to different Sources Rq Comparison of redundant CPUs by: —
reciprocal comparison H.2.18.15 — independent hardware comparator; O H.2.18.3 Internal error
detection; O H.2.18.9 periodic self-test using a test pattern of H.2.16.7 address lines; O H.2.18.22
complete bus redundancy, or H.[Link] multibit bus parity H.[Link] Rq Comparison of redundant
CPUs by: reciprocal comparison, or H.2.18.15 independent hardware comparator, or H.2.18.3
Internal error detection, or H.2.18.9 periodic self-test using a test pattern, or H.2.16.7 data
redundancy, or H.[Link] multibit bus parity H.[Link] Functional test; 0 time slot monitoring Rq
Comparison of redundant functions channels by either of the two reciprocal comparison,
independent hardware comparator, or Independent and logical time interval Monitoring H.2.16.5
H.[Link] H.2.18.15 H.2.18.3 H.[Link].
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