Unit 4, Module 3

Single bus organization of CPU, ALU, Register

Instructor
Dr. R. S. Khule,
Department of Information Technology,
Matoshri College of Engineering and Research
Centre, Nashik.
 Recap

• We have discussed about system bus, Von Neumann &

Harvard architecture and Instruction cycle with and without
interrupts.

2
 Contents

• Single bus organization of CPU

• ALU
• Register (types & functions)
 Module Objectives
• To understand how a processor executes instruction
• To know the internal functional units of a processor and the
way they are interconnected.
• To know the different types of registers and their functions
 Module Outcomes
• To explain transfers between components of single
bus CPU
• To explain the various functions carried out by ALU?
• To describe the various types of registers in CPU
• Describe the functions of various registers
 Fundamental Concepts

• Processor fetches one instruction at a time and perform the

operation specified.
• Instructions are fetched from successive memory locations
until a branch or a jump instruction is encountered.
• Processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program
Counter (PC).
• Instruction Register (IR)
 Executing an Instruction

• Fetch the contents of the memory location pointed to by

the PC. The contents of this location are loaded into the
IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR
(execution phase).
Processor Organization
 Internal organization of the
processor
• ALU
• Registers for temporary storage
• Various digital circuits for executing different micro
operations.(gates, MUX, decoders, counters).
• Internal path for movement of data between ALU and
registers.
• Driver circuits for transmitting signals to external units.
• Receiver circuits for incoming signals from external units.
• PC:
 Keeps track of execution of a program
 Contains the memory address of the next instruction to be fetched and
executed.
• MAR:
 Holds the address of the location to be accessed.
 I/P of MAR is connected to Internal bus and an O/p to external bus.
• MDR:
 Contains data to be written into or read out of the addressed location.
 It has 2 inputs and 2 Outputs.
 Data can be loaded into MDR either from memory bus or from internal
processor bus.
 The data and address lines are connected to the internal bus via MDR
and MAR
 Registers:
 The processor registers R0 to Rn-1 vary considerably from one
processor to another.
 Registers are provided for general purpose used by
programmer.
 Special purpose registers-index & stack registers.
 Registers Y,Z &TEMP are temporary registers used by
processor during the execution of some instruction.
Multiplexer:
 Select either the output of the register Y or a constant value 4
to be provided as input A of the ALU.
 Constant 4 is used by the processor to increment the contents
of PC.
 Arithmetic & Logic Unit

• Does the calculations

• Almost everything else in the computer is there to service this
unit
• Handles integers
• May handle floating point (real) numbers
 ALU Inputs and Outputs
• Generic Functions , inputs & output signals :
Arithmetic : ADD,ADC,SUB,SBB,NEG, INC, DEC
Logical : AND,OR,NOT, XOR , shift , rotate
ALU:
• Used to perform arithmetic and logical operation.
• Data Path: The registers, ALU and interconnecting bus are
collectively referred to as the data path.
 Internal processor
bus

R i in

1.Register Transfers
Ri

R i out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out
• The input and output gates for register Ri are controlled by
signals is Rin and Riout .
• Rin is set to1 – data available on common bus are loaded into
Ri.
• Riout is set to1 – the contents of register are placed on the bus.
• Riout is set to 0 – the bus can be used for transferring data
from other registers .
 Data transfer between two registers

Eg: Transfer the contents of R1 to R4.

1. Enable output of register R1 by setting R1out=1. This places
the contents of R1 on the processor bus.
2. Enable input of register R4 by setting R4in=1. This loads the
data from the processor bus into register R4.
Architecture
 2.Performing an Arithmetic or Logic
Operation

• The ALU is a combinational circuit that has no internal

storage.
• ALU gets the two operands from MUX and bus. The result is
temporarily stored in register Z.
• What is the sequence of operations to add the contents of
register R1 to those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
• Step 1: Output of the register R1 and input of the register Y are
enabled, causing the contents of R1 to be transferred to Y.

• Step 2: The multiplexer’s select signal is set to select Y causing

the multiplexer to gate the contents of register Y to input A of
the ALU.

• Step 3: The contents of Z are transferred to the destination

registerR3
 Register Transfers
• All operations and data transfers are controlled by the
processor clock.

Input and output gating for one register bit.

 Fetching a Word from Memory

• Address into MAR; issue Read operation; data into MDR.

Connection and control signals for register MDR.

 3.Fetching a Word from Memory

• The response time of each memory access varies (cache miss,

memory-mapped I/O,…).
• To accommodate this, the processor waits until it receives an
indication that the requested operation has been completed
(Memory-Function-Completed, MFC).
• Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
 Timing

Assume MAR
is always available
on the address lines
of the memory bus.

 Move (R1), R2
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in
 4.Storing a word in memory

• Address is loaded into MAR

• Data to be written loaded into MDR.
• Write command is issued.
• Example : Move R2,(R1)
R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC
 Registers
• CPU must have some working space (temporary storage)
Called registers
• Number and function vary between processor designs.
• The registers in the processor performs two roles:
 User Visible registers-Enable the machine or assembly
language programmer to minimize main memory references
by optimizing use of registers.
 Control and status registers-Use by control un it to control
the operations of processors
 User Visible Registers

• General Purpose
• Data
• Address
• Condition Codes
 General Purpose Registers (1)

• May be true general purpose

• May be used for data or addressing
• Data
– Accumulator
• Addressing
– Segment
 General Purpose Registers (2)

• Make them general purpose

– Increase flexibility and programmer options
– Increase instruction size & complexity
• Make them specialized
– Smaller (faster) instructions
– Less flexibility
 How Many GP Registers?

• Between 8 - 32
• Fewer = more memory references
• More does not reduce memory references
 Condition Code Registers

• Sets of individual bits

– e.g. result of last operation was zero
• Can be read (implicitly) by programs
– e.g. Jump if zero
• Can not (usually) be set by programs
 Control & Status Registers

• Program Counter
• Instruction Register
• Memory Address Register
• Memory Buffer Register
 Program Status Word

• Sign of last result

• Zero
• Carry
• Equal
• Overflow
• Interrupt enable/disable
• Supervisor
Example Register Organizations
 Summary
• In this module we have discussed about Single bus
organization of CPU ,ALU and Register (types & functions)

35
 Assignment

1. Give Explanation of transfers between components of single bus

CPU
2. What are the Pros & cons of single bus architecture?
3. What are the various functions carried out by ALU?
4. Explain ALU with block diagram ,
5. What are registers?
6. Describe the various types of registers in CPU
7. Describe the functions of registers: IR, MBR, MAR, PC, Flag ,SP ,
Index, pointer
• In next session i.e. Module 4 of Unit 4, we are going study about
control unit ( control signals & typical organization of hard wired &
micro programmed CU), Micro Operations (fetch, indirect, execute,
interrupt) and control signals for these micro operations.
Thank You