7060 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO.

6, JUNE 2021

Neutral-Point Voltage Balancing Methods of

Series-Half-Bridge LLC Converter for
Solid State Transformer
Cheng Lu , Student Member, IEEE, Wenfei Hu, and Fred C. Lee , Life Fellow, IEEE

Abstract—With the advancements in silicon carbide (SiC) power that power is converted between medium-voltage ac (MVac) grid
devices, the solid state transformer (SST)-based power deliv- and low-voltage dc (LVdc) bus, SST essentially functions as an
ery architecture shows advantages over traditional line-frequency MVac–LVdc power conversion system and has better energy
transformer-based solution in terms of efficiency, power density,
modularity, and scalability. This article presents a three-level con- efficiency and power density than traditional line-frequency
verter cell for a modular SST, which consists of a neutral-point- transformer (LFT)-based solution. In addition, SST-based power
clamped (NPC) H-bridge ac–dc stage and a series-half-bridge delivery architecture has the merits of modularity and scalability,
(SHB) LLC dc–dc stage. Compared with two-level cell-based SST, which is beneficial to manufacturing, installation, maintenance
the total cell number is reduced to half, which means less system
as well as system expansion. As a result, SiC-based MVac-LVdc
complexity and cost. The neutral-point (NP) voltage within each cell
must be balanced for proper operation of the system. A simple and SST becomes attractive to industries and gains a lot of research
effective balancing method is proposed by adding a phase-shift an- efforts.
gle to the modulation of the SHB LLC converter with zero-voltage Although many benefits from the SST have been demon-
switching. This idea is applicable to both two-level and three-level strated by extensive study, the complexity and cost remains
modulation modes for wide-range operation. Further, a novel NP
an issue in real-world applications. The well-known SST is
voltage balancing method for burst-mode operation under light-
load condition is proposed by short-circuiting the transformer sec- typically constructed by a plurality of cells, which are connected
ondary side during burst-OFF period and utilizing the resonant tank in series at the ac side to interface with the MVac grid and
energy to balance the NP voltage without disturbing the load or the in parallel at the dc side to form the LVdc bus. Most SSTs
grid. The proposed method is experimentally verified on the SiC- reported in the literature adopted the two-level topology-based
based three-level converter cell operated around 200 kHz for SST.
cell, which had a two-level H-bridge ac–dc stage and an isolated
Index Terms—Burst-mode operation, neutral-point (NP) voltage dc–dc stage with a high-frequency MV-insulated transformer
balancing, solid state transformer (SST), three-level converter. providing the galvanic isolation. This two-level cell topology
is simple. But, considering the limited blocking voltage of
I. INTRODUCTION commercially available switching devices, too many cells and
associated transformers are needed to handle the MV input,
NEW breed of high-frequency medium-voltage (MV) iso-
A lated solid state transformer (SST) has been enabled by
recent advancements and commercialization of wide-bandgap
which means high cost and complexity. It is, therefore, desirable
to increase the voltage level of the cell and reduce the amount
of cells for a cost-effective SST.
power devices including SiC MOSFETs [1]–[4]. On the other
At present, to reduce the system complexity and total cost, the
hand, emerging application scenarios like charging stations,
three-level-based multicell configuration is practically the opti-
data centers and green buildings will adopt the dc bus, which
mum choice. This approach has been investigated for the SST
facilitates integrating photovoltaic generation and battery energy
[5], where both the cascaded H-bridge and cascaded neutral-
storage as a dc micro-grid system. Applied to such applications
point-clamped (NPC) bridge converters were considered to find
the optimum number of cells based on the efficiency/power
Manuscript received June 6, 2020; revised September 7, 2020; accepted
October 22, 2020. Date of publication November 2, 2020; date of current density Pareto analysis. In [6], the isolated dc–dc stage of an
version February 5, 2021. Recommended by Associate Editor D. Neacsu. SST used the half-bridge NPC three-level converter on the
(Corresponding author: Cheng Lu.) primary side with 600 V SJ-MOSFETs for high dc-link voltage
Cheng Lu is with the Delta Electronics (Shanghai) Company, Ltd., Shang-
hai 201209, China, and also with the Department of Electrical Engineering, and high switching frequency operation. Another unidirectional
Tsinghua University, Beijing 100084, China (e-mail: [email protected]). SST-based on a new boost-type three-level ac–dc converter was
Wenfei Hu is with the Delta Electronics (Shanghai) Company, Ltd., Shanghai proposed to reduce the number of cells as well as the number of
201209, China (e-mail: [email protected]).
Fred C. Lee is with the Department of Electrical and Computer Engineering, switches on the MV side [7]. However, this topology was limited
Virginia Polytechnic Institute and State University, Blacksburg, VA 24061 USA to applications with unidirectional power flow from grid to load.
(e-mail: [email protected]). In contrast, to support grid-interactive functions, this article
Color versions of one or more of the figures in this article are available online
at https://ieeexplore.ieee.org. will be focused on the bidirectional SST-based on three-level
Digital Object Identifier 10.1109/TPEL.2020.3035150 cells.

0885-8993 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7061

Historically, the three-level converters have been investigated two-level and three-level modulation modes. A simple and effec-
for dc–ac and dc–dc application fields in a separate way. For tive NP voltage balancing method is proposed by adding a phase-
dc–ac applications, the hard-switched NPC three-level topology shift angle to the original two-level modulation of the SHB LLC
has been widely adopted by industry as the de facto standard. converter. A leading or lagging phase shift angle between the
On the contrary, the three-level topologies for dc–dc converters gating signals of two series half bridges will generate three-level
are much more diversified with various kinds of soft-switching modulation to charge or discharge the NP divided capacitors with
techniques [8]–[14]. Research works have been carried out to the resonant tank current. Unlike previous research works, the
continuously improve the three-level dc–dc converter perfor- resonant current waveforms will maintain symmetrical during
mances in terms of efficiency, power density, simplicity, etc. positive and negative half switching cycles. NP charging currents
Among them, Barbi et al. [15], [16] proposed a novel four-switch are the same for both half switching cycles, which means very
half-bridge primary structure for a three-level pulsewidth modu- strong balancing effect. Only a very small phase shift angle
lation (PWM) dc–dc converter featuring zero-voltage switching will be needed in practice. The ZVS can always be achieved.
(ZVS). The two half-bridge legs are connected in series without To extend the output voltage range or narrow the switching
extra clamping diodes or flying capacitors to reduce the voltage frequency range, three-level modulation modes will be used.
stress on the switching devices to only half of the input voltage. The abovementioned leading or lagging phase shift mode can
Soft switching can be realized without adding auxiliary circuits. be appropriately selected for three-level modulation to balance
Therefore, the series-half-bridge (SHB) three-level converter the NP voltage. For the LLC resonant converter, the burst-mode
has more compact primary structure in comparison with the control has been used to improve its light-load efficiency. NP
conventional NPC three-level converters. This compact primary voltage balance during burst-mode operation under light-load
structure can be applied to nonresonant [17] or resonant con- condition remains an issue as the resonant tank current is too
verters [18]–[20]. Moreover, the SHB primary structure can be small. In this article, a new method for NP voltage balancing
applied to LLC resonant converters [21], which have prominent during burst-mode operation is proposed by short-circuiting the
features including overall load-range ZVS on the primary side, transformer secondary side during burst-OFF period and utilizing
ZCS on the secondary side, and better integration of magnetics. the resonant tank energy to balance the NP voltage. Thus, the
In this article, we combine the NPC H-bridge ac–dc converter NP voltage balance can be ensured for the whole range of load.
and the SHB LLC dc–dc converter to construct an SST cell. The rest of this article is organized as follows. Section II
The neutral-point (NP) voltage of the intermediate dc-link introduces the three-level cell topology for a modular SST and
capacitors in three-level converter cells shall be balanced for basic two-level and three-level modulation modes of the SHB
proper operation of the SST system. As the neutral points of both LLC converter. Section III proposes the phase-shift NP balance
stages are coupled, the NP voltage balance could be done either control method for the two-level modulation mode and extends
by the ac–dc stage or the dc–dc stage. The NP voltage balancing this idea to the three-level modulation mode. Section IV pro-
methods have already been investigated a lot for the three-level poses the NP voltage balancing method for burst-mode operation
ac–dc converters in literature. However, the NP voltage bal- under light load condition. Section V presents the simulation
ancing method for the SHB three-level dc–dc converter has and experimental results to verify the proposed control methods.
seldom been found. In [22], the capacitor voltage control strategy Finally, Section VI concludes this article.
was proposed to correct the dc-blocking capacitor voltage and
balance the NP divided capacitor voltages by adjusting the PWM
duty cycle and the phase shift of the positive and negative half II. THREE-LEVEL SST CELL TOPOLOGY AND BASIC
cycles, respectively. Primary current waveforms during positive MODULATION MODES
and negative half cycles became asymmetrical in order to bal- In this article, the SST-based system is designed for the ex-
ance the NP voltage. ZVS would be lost in severe unbalance tremely fast charging station application. The SST-based charger
cases. Besides, the stress and loss of the switching devices are has the output power level of 360 kW and can be directly
not even. In [23], the input capacitors current imbalance issue connected to the MV grid, like 10 kV in China. The SST
was addressed in addition to voltage balancing. The proposed provides the output of 1050 V dc bus, which can be tied in
ZVS PWM strategy was composed of two alternating operation with renewable energy generation and energy storage systems
modes, which achieved balanced currents through input capac- besides the electric vehicle chargers. Based on the proposed
itors and evenly distributed switching losses among four power three-level cell topology and 1.2 kV SiC devices, only seven
switches in every two switching periods. The abovementioned cells are needed for each phase of the star-connected 10 kV
literature mainly focus on three-level PWM dc–dc converters. system. For the 13.2 kV system in the U.S., each phase has nine
Unfortunately, there are few studies about the NP voltage balanc- cells connected in series, which brings the system power level
ing methods for SHB LLC resonant dc–dc converters. For SHB up to 400 kW. One more cell can be added for N–1 redundant
LLC converters, PFM modulation strategy is mostly adopted operation, which increases the system availability. Thus, the
rather than PWM. Both two-level and three-level modulation SST-based MV power delivery architecture shows the benefit
modes can be applied to the SHB LLC converter according to of modularity, scalability, redundancy, etc.
different application requirements. The three-level converter-based multicell configuration of an
In this article, NP voltage balancing methods for the SHB LLC SST is shown in Fig. 1. The SST is constructed by a plurality
converter will be comprehensively investigated covering both of cells, which are connected in series at the ac side to interface

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 7062 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

TABLE I
OUTPUT VOLTAGE LEVELS AND THEIR CORRESPONDING SWITCH STATES

waveforms for the left and right bridges are shifted up or down
simultaneously according to the NP voltage and the direction
of the grid current [25]. This method is simple, but has some
drawbacks. First, the balancing effect is poor under light-load
condition as the grid current is very small. Second, this method
relies on the direction of the grid current. In practice, the current
sampling error would result in wrong judgment of the current
direction, especially when the current is small. To overcome this,
certain amount of reactive currents need to be injected to the grid
Fig. 1. (a) Multicell configuration of an SST. (b) Proposed three-level con- under light load. The quantity of the injected reactive current
verter cell topology.
depends on the practical implementation, such as the current
sensing accuracy, the driving circuit delay time mismatch, and
the dc-link dividing capacitors tolerances. However, this is not
with the MVac grid and in parallel at the dc side to form the LVdc grid-friendly and not allowed for some applications.
bus, as shown in Fig. 1(a). Each cell consists of a diode-clamped On the other hand, the SHB LLC dc–dc stage should be able to
NPC (DNPC) H-bridge ac–dc stage and an SHB LLC dc–dc work independently in case the front-end ac–dc stage is inactive
stage, as shown in Fig. 1(b). Two stages are coupled by the or unavailable. So, the SHB LLC converter needs to balance the
intermediate dc-link with the common neutral point O. The NP voltage by itself. Before discussing its NP voltage balancing
total dc-link voltage Vdc is around 1600 V. The primary circuit methods, the basic modulation modes of SHB LLC converter are
of the SHB LLC converter has two half-bridge legs connected first introduced. Table I lists all possible output voltage levels
in series to reduce the voltage stress on the switching devices and their corresponding switch states. It can be seen that there are
Q1∼ Q4 to only half of the input voltage, i.e., Vdc /2. Therefore, three categories of output levels, namely, level “0”, level “1,” and
1.2 kV SiC MOSFETs can be used here, which are more popular level “2.” Two groups of switch states can output the level “1,”
and affordable in the market now. Clamping diodes are saved assuming that the voltages across the two dc-link capacitors [Cp
compared with the conventional DNPC 3-level dc–dc converter. and Cn in Fig. 1(b)] are equal or the NP voltage is balanced. The
Cost is of high priority in our design tradeoffs. We choose LLC modulation of the SHB LLC converter is flexible. Depending on
and not CLLC resonant circuit for saving resonant capacitors the application, it can be operated as the two-level modulation
on the secondary side. Furthermore, less component means mode or three-level modulation mode.
higher power density. The transformer provides MV isolation
and voltage transformation. The size of the transformer can
A. Two-Level Modulation Mode of the SHB LLC Converter
be dramatically reduced when operated at around 200 kHz
resonant frequency fr in this article. The leakage inductance of Level “0” and level “2” in Table I are selected for this mode
the transformer can be utilized as the resonant inductor Lr . The of operation. The key waveforms are shown in Fig. 2(a). Vgs
resonant capacitor Cr is then determined by fr and Lr [24]. Cr are driving signals of Q1∼ Q4 . Q1 and Q4 are turned ON/OFF
also functions as a dc-blocking capacitor here, bearing a dc bias simultaneously while Q2 and Q3 are turned OFF/ON simultane-
voltage of Vdc /2. On the secondary side, the active full-bridge ously. The two-level excitation voltage VAB with 50% duty ratio
circuit is adopted for bidirectional operation. The 1.7 kV SiC is generated and applied to the resonant tank. Like traditional
MOSFETs S1∼ S4 are used for 1050 V dc bus output. Detailed half-bridge LLC converters, the resonant capacitor Cr has a dc
circuit parameters can be found in the Appendix. bias voltage of Vdc /2. Fig. 2(b) and (c) show the equivalent
The NP voltage shall be balanced for safe operation. It can be circuits of level “2” and level “0” states, respectively. Ideally,
balanced by controlling either stage of the cell. The modulation the NP current iN is zero for both level “2” and level “0,” which
and NP balance control method of the front-end DNPC three- means no effect on the NP voltage.
level ac–dc stage is well known. The switching frequency of the The switching frequency is typically adjusted by a closed-loop
front-end converter is only several kilohertz since the carrier- voltage regulator. To regulate the output voltage down further,
phase-shift modulation is adopted for the multicell cascaded the switching frequency may be pushed too high with the tradi-
configuration. To balance the NP voltage, the modulation voltage tional two-level modulation mode, especially under light-load

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7063

Fig. 2. Two-level modulation mode of the SHB LLC converter. (a) Key
waveforms. (b) Equivalent circuit of level “2.” (c) Equivalent circuit of level “0.”

conditions. To address this issue, the three-level modulation

mode can be utilized for wide-range operation of the SHB LLC
converter.

B. Three-Level Modulation Mode of the SHB LLC Converter

Besides level “0” and level “2,” level “1”s in Table I are
involved in the three-level modulation mode. There are two basic
modes of three-level modulation as two groups of switch states
can synthesize the level “1.” The three-level modulation mode
is called the P mode with conduction of Q1 and Q3 , and the
N mode with conduction of Q2 and Q4 . The key waveforms Fig. 3. Three-level modulation mode of the SHB LLC converter. (a) Key
waveforms of P-mode three-level modulation. (b) Key waveforms of N-mode
of P-mode and N-mode three-level modulation are shown in three-level modulation. (c) Equivalent circuit of P-mode level “1” during the
Fig. 3(a) and (b), respectively. The duty ratio of level “1” is positive half cycle. (d) Equivalent circuit of N-mode level “1” during the positive
given by ϕ1 /π, which will vary with the gain range and/or load half cycle.

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 7064 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

Fig. 4. Simulated NP imbalance caused by 10 ns mismatch between driving

signals of Q1 and Q4 .

conditions. Fig. 3(c) and (d) show the equivalent circuits of two
types of level “1” during the positive half cycle. It can be seen
that the excitation voltages VAB and the resonant currents are the
same except that the NP current iN is in the opposite direction
for the two modes of three-level modulation. For the P-mode
three-level modulation, the NP is charged with the resonant
current during the positive half cycle while discharged during the
negative half cycle. For the N-mode three-level modulation, the
NP is discharged with the resonant current during the positive
half cycle while charged during the negative half cycle. Ideally,
with symmetrical operation, the averaged NP current during one
switching cycle is zero for both P-mode and N-mode three-level
modulation. Thus, the NP voltage can be balanced in a switching
cycle.
The duty ratio of Q1 and Q3 are more than 50% for the P-mode
three-level modulation while the duty ratio of Q2 and Q4 are
more than 50% for the N-mode three-level modulation. To make
the loss evenly distributed among the four switches, the P-mode
and N-mode three-level modulation can be alternatively used.

III. PROPOSED NP VOLTAGE BALANCING METHOD FOR SHB

LLC CONVERTER
Ideally, the NP voltage is balanced for both two-level and
three-level modulation modes as described earlier. In practice, Fig. 5. Proposed NP voltage balancing method for the two-level modulation
however, there is time delay of the control and driver circuits, mode of the SHB LLC converter with main waveforms. (a) Lag phase-shift
mode. (b) Lead phase-shift mode.
which results in the NP voltage imbalance. Furthermore, the
imbalance problem becomes severe due to the tolerance and
mismatch in hardware components. This issue is especially sig-
nificant for the SST operated at above 200 kHz in this article. In
A. Proposed NP Voltage Balancing Method for the Two-Level
Fig. 4, simulation shows that the two dc-link capacitor voltages
Modulation Mode of the SHB LLC Converter
start to diverge if there is 10 ns time delay between the driving
signals of Q1 and Q4 . For safe operation, the NP voltage shall Fig. 5 shows the proposed NP voltage balancing method for
be balanced under all circumstances. the two-level modulation mode of the SHB LLC converter,
From the equivalent circuits in Figs. 2 and 3, it can be seen which includes two operation modes, i.e., the lag and lead
that only level “1” affects the NP voltage while level “2” or level phase-shift modes. The NP will be discharged/charged when
“0” does not. Furthermore, there are two redundant types of level there is a phase lag/lead between the driving signals of the lower
“1,” namely the P-mode and N-mode level “1,” which have just and upper half bridges.
opposite effect on the NP balance. The NP can be charged or In Fig. 5(a), compared with the original driving signals in
discharged by the resonant current during the level “1” state Fig. 2, Q4 and Q3 lag behind Q1 and Q2 with a phase-shift angle
depending on the particular type of level “1.” ϕx . The level “1” is inserted into the original level “2” and “0”
The basic principle to control the NP voltage is to appro- due to the phase shift, which has a duty ratio of ϕx /π. During the
priately select the P-mode or N-mode level “1” to charge or period of level “1,” the NP will be discharged by the resonant
discharge the dc-link capacitors by the resonant current. The tank current. NP currents iN are in the same direction for both
detailed NP voltage balancing methods will be comprehen- positive and negative half switching cycles, which means very
sively investigated for both two-level and three-level modulation strong balancing effect. Only a very small phase-shift angle will
modes. be needed in practice due to the strong balancing effect. The

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7065

Fig. 6. Control diagram of the proposed NP voltage balancing method for the
two-level modulation mode of the SHB LLC converter.

resonant current waveforms maintain symmetrical during both

half switching cycles. ZVS can always be achieved. In Fig. 5(b),
Q4 and Q3 lead Q1 and Q2 by a phase-shift angle ϕx , which
has the opposite NP voltage balancing effect as in Fig. 5(a).
During the period of level “1,” the NP will be charged by the
resonant tank current. Thus, the NP voltage can be controlled by
adjusting the phase-shift angle ϕx as shown in Fig. 6. The two
dc-link capacitor voltages (VdcP and VdcN ) are compared and
the error ΔVdc , which indicates the NP balance, is controlled
by a PI controller, whose output is used to adjust the phase-shift
angle ϕx . On the other hand, the switching frequency fs is varied
to regulate the output voltage Vo to track its reference Vo_ref , for
example, by a three-pole two-zero compensator [26]. Finally,
the driving signals Vgs of the four switches can be determined
by ϕx and fs .

B. Proposed NP Voltage Balancing Method for the

Three-Level Modulation Mode of the SHB LLC Converter
Comparing Figs. 5 with 2, it can be observed that, by adding
a phase-shift angle, the original two-level modulation actually
becomes a kind of three-level modulation. Nevertheless, in Fig. 7. Proposed NP voltage balancing method for the three-level modulation
Fig. 5, the phase-shifted two-level modulation-based three-level mode of the SHB LLC converter with main waveforms. (a) Lag phase-shift
modulation has two distinct features, which distinguish it from mode. (b) Lead phase-shift mode.
the conventional three-level modulation mode in Fig. 3. One
is the alternate P-mode and N-mode three-level modulation. In
each switching cycle, there is a P-mode level “1” for one half Fig. 3. The P-mode and N-mode level “1”s alternate for each half
cycle and an N-mode level “1” for the other half cycle. All four switching cycle with the duty ratio of ϕ1 /π, during which time
switches have the same 50% duty ratio. For the conventional the NP is discharged by the resonant current. To charge the NP,
three-level modulation mode, there are only P-mode or N-mode in Fig. 7(b), the lead phase-shift mode is used instead. During
level “1”s for both positive and negative half switching cycles the time of ϕ1 in each half switching cycle, the NP is charged
as shown in Fig. 3(a) and (b), respectively. Two of four switches by the resonant current. Thus, the NP voltage can be balanced
have a duty ratio more than 50%. The other feature different by appropriately selecting the lead or lag phase-shift mode. In
from the conventional three-level modulation is the duty ratio [22], the NP voltage was balanced by regulating the phase shift
of level “1.” The duty ratio of level “1” (ϕ1 /π) in conventional of the positive and negative half cycles, which might deviate
three-level modulation is mainly determined by the gain range from 180°, depending on the imbalance level. Thus, the primary
or load conditions. However, the duty ratio of level “1” (ϕx /π) in current waveforms could become asymmetrical during positive
the proposed phase-shifted two-level modulation is determined and negative half switching cycles. On the other hand, similar to
by the NP voltage balancing controller as shown in Fig. 6. In the P-mode three-level modulation, the NP was charged during
spite of these differences, the idea of the proposed NP voltage the positive half cycle while discharged during the negative half
balancing method for the two-level modulation mode can be cycle. But, the charging and discharging time was different due
extended to the three-level modulation mode. to the phase shift. The net charge was used for NP voltage
Fig. 7 shows the proposed NP voltage balancing method for balancing. On the contrary, NP charging currents here are the
the three-level modulation modes of the SHB LLC converter. same for both half switching cycles, which results in stronger
To discharge the NP, in Fig. 7(a), the lag phase-shift mode with balancing effect than that given in [22].
an equivalent phase-shift angle of ϕ1 is proposed to replace Fig. 8 shows the control diagram of the proposed NP voltage
the conventional P-mode or N-mode three-level modulation in balancing method for the three-level modulation mode of the

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 7066 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

Fig. 8. Control diagram of the proposed NP voltage balancing method for the Fig. 9. Turn-OFF current of the primary switches under different loads.
three-level modulation mode of the SHB LLC converter.

SHB LLC converter. The two dc-link capacitor voltages (VdcP

and VdcN ) are compared, then according to the error ΔVdc , the
status of NP balance is judged and flagged with “–1/0/1,” which
means “high/normal/low.” The driving signals Vgs of the four Fig. 10. Model for the NP voltage balancing control design.
switches can be determined by the NP status flag, the P/N mode
flag, ϕ1 , and the switching frequency fs . Taking the P-mode
three-level modulation for example, if the NP status is normal where IoffP denotes the turn-OFF current, which is assumed to
(flag = 0), the conventional three-level modulation waveform be constant during the level “1” period since the level “1” period
[see Fig. 3(a) for details] will be output. If the NP status is high is very short in practice.
(flag = –1), the lag phase-shift mode waveform [see Fig. 7(a) The turn-OFF current varies with load and switching fre-
for details] will be output. If the NP status is low (flag = 1), the quency, which is illustrated in Fig. 9. These curves can be
lead phase-shift mode waveform [see Fig. 7(b) for details)] will obtained by circuit simulation or derived by a time-domain
be output. The N-mode three-level modulation with NP balance model, which is beyond the scope of this article. However,
control is similar. The waveforms in Fig. 3(b)/Fig. 7(a)/Fig. 7(b) the interested reader might refer to [27] for a design-oriented
will be output when the NP status is normal/high/low, respec- comprehensive time-domain model featuring high accuracy and
tively. calculation speed.
The model for the NP voltage balancing control loop design
is illustrated in Fig. 10, where Td stands for the total equivalent
C. Modeling and Design of NP Voltage Balancing Control
time delay including the low-pass filter for the dc-link voltages
The NP voltage balancing control and the output voltage sampling and the digital control delay, and KP and KT are the
control have very different time scales. The NP voltage balancing proportional gain and integral time constant of the PI controller,
control loop can be regarded as the auxiliary loop and should respectively. The open-loop transfer function is given by
be much slower than the main loop of output voltage control.
KP IoffP KT s + 1
Therefore, in Fig. 6, the two control loops can be decoupled and GOL (s) = . (3)
independently designed. The compensator design for the output KT πCdc s2 (Td s + 1)
voltage control has been well established in [26]. Therefore,
only the auxiliary NP voltage balancing control design will be To simplify the control design, IoffP is set to the maximum
discussed here. value in the turn-OFF current curves, which is 11 A as shown in
Referring to the equivalent circuit in Fig. 3, neglecting the Fig. 9. As a result, the stability of the balancing control can be
disturbing NP current from the front-end DNPC H-bridge con- guaranteed as long as the worst case is stable.
verter and assuming Cp = Cn = Cdc , the NP voltage error can Fig. 11 shows the Bode plot of GOL (s), whose parameters are
be modeled as listed in the Appendix. It can be observed that the cross-over
frequency with PI compensation is around 50 Hz with a phase
dΔVdc margin of 54°.
Cdc = iN . (1)
dt
IV. PROPOSED NP VOLTAGE BALANCING METHOD FOR
Averaged in a switching cycle, the NP current iN can be BURST-MODE OPERATION
obtained by the following, according to Fig. 5:
For the LLC resonant converter, the burst-mode control has
ϕx been used to improve its light-load efficiency. All switches will
iN = IoffP (2) be turned OFF during the burst-OFF period. The NP voltage will
π

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7067

Fig. 11. Dynamics of the NP voltage balancing control.

lose control during the burst-OFF period. During the burst-ON

period, the NP voltage balancing relies on the resonant current,
which becomes smaller under lighter loads. Furthermore, the
burst-ON duty ratio is decreasing with the load decreasing.
The balancing capability during the burst-mode operation will
become weaker and weaker as the load goes down. Besides, as
mentioned before, the front-end ac–dc stage of the SST cannot
balance the NP voltage well under light load either. Therefore,
it is significant to find better solutions to balance the NP voltage
for burst-mode operation of the SHB LLC converter.
A novel NP voltage balancing method for burst-mode oper-
ation is proposed by short-circuiting the transformer secondary
side during the burst-OFF period and utilizing the resonant tank
energy to balance the NP voltage. The basic idea can be il-
lustrated by the equivalent circuits shown in Fig. 12. During
the burst-OFF period, the upper switches S1 and S3 of the
full-bridge circuits on the secondary side are turned ON to
short-circuit the transformer and stop transferring resonant tank Fig. 12. Equivalent circuits during the burst-OFF period with the proposed NP
voltage balancing method. (a) Level “2”. (b) Level “0”. (c) P-mode level “1”.
energy to the load. The primary-side switches continue to work (d) N-mode level “1”.
for purpose of NP voltage balancing during the burst-OFF period.
With the short-circuited transformer, the resonant current be-
comes much larger and sufficient to control the NP voltage.
The operation principle of the primary-side switches remains
the same as presented in Section III. It should be pointed out
that the transformer can be short-circuited by turning ON either
the upper switches S1 and S3 or the lower switches S2 and S4 of
the secondary-side circuit. This idea is also applicable to other
NP voltage balancing methods for SHB LLC converter or other
types of three-level dc–dc converters.
When short circuited, the resonant currents are extremely high
resulting in very strong NP voltage balancing effect but incurring
excessive losses. To improve the light-load efficiency, the NP
voltage balancing will be performed intermittently during the
Fig. 13. Burst-mode operation with the proposed intermittent NP voltage
burst-OFF period. The burst-mode operation with the intermittent balancing strategy.
NP voltage balancing strategy is illustrated in Fig. 13. During

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 7068 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

Fig. 15. Simulation results with the proposed NP voltage balancing method for
Fig. 14. Simulation results with the proposed NP voltage balancing method the P-mode three-level modulation of the SHB LLC converter. (a) Waveforms
for the two-level modulation mode of the SHB LLC converter. (a) Waveforms including VdcP , VdcN , NP status flag, and Vo . (b) Waveforms including VAB ,
including VdcP , VdcN , ϕx , and Vo . (b) Waveforms including VAB , iLr , iLm , iLr , iLm , and iN when NP status flag = 0 and (c) when NP status flag = –1.
and iN at ϕx = 0 and (c) at ϕx = 14°

current waveforms maintain symmetrical during both positive

the burst-ON period, the NP voltage balancing methods presented and negative half switching cycles. ZVS is always achieved.
in Section III are carried out. During the burst-OFF period, the Fig. 15 shows the performances under the proposed NP volt-
transformer is periodically short-circuited by the secondary-side age balancing method for the P-mode three-level modulation of
circuit as mentioned earlier. With this control strategy, the error the SHB LLC converter. At 60 ms, the NP imbalance situation is
between the VdcP and VdcN can be controlled within ΔVdc _max . simulated, then VdcP falls and VdcN rises. The lag phase-shifted
Since the balancing capability is very strong, the duty ratio of P-mode in Fig. 7(a) is selected according to the NP status flag
the activation of the NP voltage balancing with short circuit is by the proposed controller in Fig. 8. The NP voltage balance
very small in practice. Switches are kept OFF in most time of the is fast recovered. From Fig. 15(b) and (c), it can be seen that
burst-OFF period. Therefore, the light-load efficiency will not be the resonant current waveforms maintain symmetrical during
compromised. both positive and negative half switching cycles. ZVS is also
achieved. It should be pointed out that the NP voltage balancing
for the N-mode three-level modulation is similar and omitted
V. SIMULATION AND EXPERIMENTAL VERIFICATION here. For comparison purposes, the balancing method presented
in [22] is also simulated and shown in Fig. 16(a). It can be ob-
A. Simulation Verification served that the conventional method has asymmetrical primary
In order to verify the proposed NP voltage balancing control current waveforms during positive and negative half cycles in
strategy, a simulation model of the SHB LLC converter is built order to balance the NP voltage. The more imbalance the load
in PSIM, whose circuit parameters are listed in the Appendix. of the NP, the more the asymmetrical resonant current. ZVS
Fig. 14 shows the performances under the proposed NP volt- would be lost in severe unbalance cases. As a result, the power
age balancing method for the two-level modulation mode of the loss would be dramatically increased due to lost ZVS.
SHB LLC converter. At 100 ms in Fig. 14(a), the NP imbalance Fig. 17 shows the performances under the proposed NP volt-
situation is simulated by connecting a resistor load to the upper age balancing method for the burst-mode operation of the SHB
half dc-link, then VdcP falls and VdcN rises. The lag phase-shift LLC converter under light load condition. During the burst-OFF
mode in Fig. 5(a) is applied with the phase-shift angle ϕx , which period, the transformer is short-circuited with intermittent NP
is adjusted by the proposed controller in Fig. 6. After about balancing control, which can be observed in Fig. 17(a). When
20 ms of regulation, the NP voltage becomes balanced again. short-circuited, the transformer has zero excitation voltage vCD
From Fig. 14(b) and (c), it can be observed that the resonant and zero magnetizing current iLm as shown in Fig. 17(c). The

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7069

Fig. 18. SST cell prototype.

Fig. 16. Simulation results including VAB , iLr , iLm , and iN . (a) Conventional
control strategy. (b) Proposed control strategy.

Fig. 17. Simulation results with the proposed NP voltage balancing method for
the burst-mode operation of the SHB LLC converter. (a) Waveforms including
VdcP , VdcN , iLr , iLm , and Vo . (b) Waveforms including VAB , vCD , iLr , iLm ,
and iN during burst-ON period and (c) during burst-OFF period with NP balancing.

resonant current becomes very large due to short circuit, so

that the NP current becomes much larger than that during the
burst-ON period, which can be seen by comparing Fig. 17(c) with
(b). Thus, NP balancing capability is greatly enhanced.

B. Experimental Verification
A 15 kW prototype of the three-level converter cell for an SST
is built to verify the proposed control strategy, which consists of
a DNPC H-bridge ac–dc stage and an SHB LLC dc–dc stage. Fig. 19. Experimental results with the proposed NP voltage balancing method
for the two-level modulation mode of the SHB LLC converter. (a) Waveforms
Fig. 18 shows the SST cell prototype. The peak efficiency from including Vo , VdcP , VdcN , ϕx , and fs . (b) Waveforms including Vgs _Q1 ,
the ac input to the dc output is above 98% at near half load Vgs _Q4 , VAB , and iLr at ϕx = 0 and (c) at ϕx = 14°.
and the full load efficiency is 97.7%. The specifications of the

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 7070 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

Fig. 20. Experimental results with the proposed NP voltage balancing method
for the three-level modulation mode of the SHB LLC converter. (a) Waveforms Fig. 21. Experimental results with the proposed NP voltage balancing method
including Vo , VdcP , VdcN , NP status flag, and fs . (b) Waveforms including for the burst-mode operation of the SHB LLC converter. (a) Waveforms including
Vgs _Q1 , Vgs _Q4 , VAB , and iLr when NP status flag = 0 and (c) when NP status Vgs _Q1 , Vgs _Q4 , VAB , and iLr , as well as zoomed waveforms during burst-ON
flag = –1. period and burst-OFF period with NP balancing, respectively. (b) Waveforms
including VdcP , VdcN , VAB , and Vo .

prototype are listed in the Appendix. In the experiments, for

safety reason, the intermediate dc-link voltage Vdc is regulated voltages VdcP and VdcN are equalized, which means the NP
to be 800 V by the front-end ac–dc stage while the dc output voltage is well balanced. The waveforms of the driving signals
voltage Vo is regulated by the SHB LLC dc–dc stage. The SHB Vgs _Q1 and Vgs _Q4 , the output excitation voltage VAB , and
LLC converter is responsible for the NP voltage balance. For the resonant current iLr are shown in Fig. 19(b) without phase
purpose of verification, the NP imbalance situation is emulated shifting and in Fig. 19(c) with phase shifting, respectively. It
by controlling the front-end ac–dc converter in counterbalance can be observed that the resonant current waveforms maintain
based on the aforementioned method in Section II. symmetrical during both positive and negative half switching
Fig. 19 shows the performances under the proposed NP volt- cycles, and ZVS is always achieved.
age balancing method for the two-level modulation mode of Fig. 20 shows the performances under the proposed NP volt-
the SHB LLC converter. It can be seen from Fig. 19(a) that, age balancing method for the P-mode three-level modulation of
by adjusting the phase-shift angle ϕx , the dividing capacitor the SHB LLC converter. In Fig. 20(a), the NP voltage balance

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 LU et al.: NEUTRAL-POINT VOLTAGE BALANCING METHODS OF SERIES-HALF-BRIDGE LLC CONVERTER FOR SOLID STATE TRANSFORMER 7071

Fig. 23. SST system prototype.

Fig. 24. Full-power testing results of the 10 kV SST system including three-
phase grid voltages vgA , vgB , vgC and currents igA , igB , igC , dc output current
Io , and voltage.
Fig. 22. Dynamic performance under load changes including Vo , VdcP , VdcN ,
ϕx , fs , and Io . (a) Load step up. (b) Load step down.

enter the burst mode. Although the balancing capability is quite

low, the NP voltage balancing methods presented in Section III
is recovered after the lag phase-shifted P-mode in Fig. 7(a) are still being carried out during the burst-ON period. During
is selected according to the NP status flag by the proposed the burst-OFF period, the transformer is short-circuited and the
controller in Fig. 8. In Fig. 20(b), the original P-mode three-level primary switches are intermittently activated for purpose of NP
modulation waveform is output when NP status flag = 0. The balancing, which can be observed in Fig. 21(a). Comparing the
duty ratio of level “1” is ϕ1 /π. In Fig. 20(c), the lag phase-shifted two zoomed waveforms during burst-ON period and burst-OFF
P-mode three-level modulation waveform is output when NP period with NP balancing, it can be observed that the resonant
status flag = –1. The equivalent phase-shift angle is ϕ1 . From current becomes much larger due to short circuit. So, the NP
Fig. 20(b) and (c), it can be seen that the excitation voltages current also becomes much larger than that during the burst-ON
VAB and the resonant currents iLr are the same, which means the period. Thus, NP balancing capability is greatly enhanced. As
NP balancing does not affect the power delivery. The resonant illustrated in Fig. 21(b), VdcP and VdcN are well balanced during
current waveforms maintain symmetrical during both positive the burst-mode operation. ΔVdc _max is within 10 V.
and negative half switching cycles, and ZVS is also achieved. To validate the control robustness and stability, dynamic
Fig. 21 shows the performances under the proposed NP load step performances are further investigated. Soft transition
voltage balancing method for the burst-mode operation of the between both power (low to high and high to low) modes can
SHB LLC converter under light load condition. The resonant be observed in Fig. 22(a) and (b), respectively. The NP voltage
frequency is around 200 kHz and the maximum switching fre- is well balanced for the whole range of load, including the burst
quency is limited to 400 kHz, beyond which the converter will mode operation.

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 7072 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 6, JUNE 2021

1050 V dc output, 360 kW SST has been implemented and

confirmed the efficacy.

APPENDIX
See Table II.
TABLE II
PARAMETERS OF THE SIMULATION MODEL AND EXPERIMENTAL PROTOTYPE

Fig. 25. NP voltages within 24 cells of the 10 kV SST system.

Finally, a three-phase 10 kV input, 1050 V dc output, 360 kW

SST has been constructed based on the presented three-level
cell, which has eight cells in each phase. Two sets of SSTs are ACKNOWLEDGMENT
connected in parallel for pump back testing purposes, which is The authors would like to thank the hardware team led by Dr.
shown in Fig. 23. The full-power testing results are shown in W. Zhang from the Delta Power Electronics Center (DPEC), for
Fig. 24. The output dc bus voltage is well regulated and the assistance in constructing the experimental converter cell and
input grid currents are controlled sinusoidal with unity power the SST system.
factor. The NP voltages within 24 cells are well balanced as
shown in Fig. 25, which confirmed the efficacy of the proposed
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