SYLLABUS

Programmable Peripheral Input/Output Port 8255-Architecture and

modes of operation, Programmabl eInterval tmer 8254 -Architecture
and modes of operation,DMA Controller 8257 Architecture(Just
mention the controlword, no need to memorize the control word of
8254 and 8257)

College of Engg,Kottarakkara,Dept. of
CSE 1
 8257
DMA CONTROLLER

College of Engg. Kottarakkara, Dept.

of CSE 2
 It is a 4-channel DMA.
 So 4 I/O devices can be interfaced to DMA
 It is designed by Intel
 Each channel have 16-bit address and 14 bit
counter
 It provides chip priority resolver that resolves
priority of channels in fixed or rotating mode.

College of Engg. Kottarakkara, Dept.

of CSE 3
It generates a TC signal to
indicate the peripheral that the
programmed number of data
bytes have been transferred.
It generates MARK signal to
indicate the peripheral that 128
bytes have been transferred.
It requires single phase clock.
The maximum frequency is 3Mhz
and minimum frequency is 250
Hz. College of Engg. Kottarakkara, Dept.
of CSE 4
 It execute 3 DMA cycles
1.DMA read 2.DMA write
3.DMA verify.
 It provide AEN signal that can be
used to isolate CPU and other
devices from the system bus.
 It is operate in two modes.
1.Master Mode
2.Slave Mode
College of Engg. Kottarakkara, Dept.
of CSE 5
College of Engg. Kottarakkara, Dept.
of CSE 6
 D0-D7:
 it is a bidirectional ,tri state ,Buffered
,Multiplexed data (D0-D7)and (A8-A15).
 In the slave mode it is a bidirectional (Data is
moving).
 In the Master mode it is a unidirectional
(Address is moving).

College of Engg. Kottarakkara, Dept.

of CSE 7
 IOR:
 It is active low ,tristate ,buffered ,Bidirectional
lines.
 In the slave mode it function as a input line.
IOR signal is generated by microprocessor to
read the contents 8257 registers.
 In the master mode it function as a output line.
IOR signal is generated by 8257 during write
cycle

College of Engg. Kottarakkara, Dept.

of CSE 8
 IOW:
 It is active low ,tristate ,buffered ,Bidirectional
control lines.
 In the slave mode it function as a input line.
IOW signal is generated by microprocessor to
write the contents 8257 registers.
 In the master mode it function as a output
line. IOR signal is generated by 8257 during
read cycle

College of Engg. Kottarakkara, Dept.

of CSE 9
CLK:
 It is the input line ,connected with TTL clock
generator.
 This signal is ignored in slave mode.
RESET:
 Used to clear mode set registers and status
registers
A0-A3:
These are the tristate, buffer, bidirectional
address lines.
In slave mode ,these lines are used as address
inputs lines and internally decoded to access the
internal registers.
In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on
the lines.
College of Engg. Kottarakkara, Dept.
of CSE 10
CS:
 It is active low, Chip select input line.
 In the slave mode, it is used to select the chip.
 In the master mode, it is ignored.
A4-A7:
These are the tristate, buffer, output address
lines.
In slave mode ,these lines are used as address
outputs lines.
In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on
the lines.

College of Engg. Kottarakkara, Dept.

of CSE 11
READY:
 It is a asynchronous input line.
 In master mode,
 When ready is high it is received the signal.
 When ready is low, it adds wait state between S1
and S3
 In slave mode ,this signal is ignored.
HRQ:
 It is used to receiving the hold request signal
from the output device.

College of Engg. Kottarakkara, Dept.

of CSE 12
HLDA:
 It is acknowledgment signal from microprocessor.
MEMR:
 It is active low ,tristate ,Buffered control output
line.
 In slave mode, it is tristated.
 In master mode ,it activated during DMA read
cycle.
MEMW:
 It is active low ,tristate ,Buffered control input
line.
 In slave mode, it is tristated.
 In master mode ,it activated during DMA write
cycle.
College of Engg. Kottarakkara, Dept.
of CSE 13
AEN (Address enable):
 It is a control output line.
 In master mode ,it is high
 In slave mode ,it is low
 Used it isolate the system address ,data ,and
control lines.
ADSTB: (Address Strobe)
 It is a control output line.
 Used to split data and address line.
 It is working in master mode only.
 In slave mode it is ignore.

College of Engg. Kottarakkara, Dept.

of CSE 14
TC (Terminal Count):
 It is a status of output line.
 It is activated in master mode only.
 It is high ,it selected the peripheral.
 It is low ,it free and looking for a new peripheral.
MARK:
 It is a modulo 128 MARK output line.
 It is activated in master mode only.
 It goes high ,after transferring every 128 bytes
of data block.

College of Engg. Kottarakkara, Dept.

of CSE 15
DRQ0-DRQ3(DMA Request):
 These are the asynchronous peripheral request
input signal.
 The request signals is generated by external
peripheral device.
DACK0-DACK3:
 These are the active low DMA acknowledge
output lines.
 Low level indicate that ,peripheral is selected for
giving the information (DMA cycle).
 In master mode it is used for chip select.

College of Engg. Kottarakkara, Dept.

of CSE 16
College of Engg. Kottarakkara, Dept.
of CSE 17
 It containing Five main Blocks.
1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.

College of Engg. Kottarakkara, Dept.

of CSE 18
DATA BUS BUFFER:
 It contain tristate ,8 bit bi-directional buffer.
 Slave mode ,it transfer data between
microprocessor and internal data bus.
 Master mode ,the outputs A8-A15 bits of
memory address on data lines (Unidirectional).
READ/CONTROL LOGIC:
 It control all internal Read/Write operation.
 Slave mode ,it accepts address bits and control
signal from microprocessor.
 Master mode ,it generate address bits and
control signal.

College of Engg. Kottarakkara, Dept.

of CSE 19
Control logic block:
 It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
 Master mode ,It control the sequence of
DMA operation during all DMA cycles.
 It generates address and control signals.
 It increments 16 bit address and decrement
14 bit counter registers.
 It activate a HRQ signal on DMA channel
Request.
 Slave ,mode it is disabled.
College of Engg. Kottarakkara, Dept.
of CSE 20
MODE SET REGISTERS:
 It is a write only registers.
 It is used to set the operating modes.
 This registers is programmed after
initialization of DMA channel.

D7 D6 D5 D4 D3 D2 D1 D0
AL TCS EW RP EN3 EN2 EN1 EN0

College of Engg. Kottarakkara, Dept.

of CSE 21
AL=1=Auto load mode
AL=0=Rotating mode

 TCS=1=Stop after TC (Disable Channel)

 TCS=0=Start after TC (Enable Channel)

 EW=1=Extended write mode

 EW=0=normal mode.

 RP=1=Rotating priority
 RP=0=Fixed priority.

College of Engg. Kottarakkara, Dept.

of CSE 22
 EN3=1=Enable DMA CH-3
 EN3=0=Disable DMA CH-3

 EN2=1=Enable DMA CH-2

 EN2=0=Disable DMA CH-2

 EN1=1=Enable DMA CH-1

 EN1=0=Disable DMA CH-1

 EN0=1=Enable DMA CH-0

 EN0=0=Disable DMA CH-0

College of Engg. Kottarakkara, Dept.

of CSE 23
STATUS REGISTERS:
 It is read only registers.
 It is tell the status of DMA channels
 TC status bits are set when TC signal is
activated for that channel.
 Update flag is not affected during read
operation.
 The UP bit is set during update cycle . It is
cleared after completion of update cycle.
D7 D6 D5 D4 D3 D2 D 1 D0
0 0 0 UP TC3 TC2 TC1 TCO
College of Engg. Kottarakkara, Dept.
of CSE 24
 UP=Update flag
 UP=1=8257 executing update cycle
 UP=0=8257 executing DMA cycle

 TC3=1=TC activated CH-3

 TC3=0=TC activated CH-3

 TC2=1=TC activated CH-2

 TC2=0=TC activated CH-2

College of Engg. Kottarakkara, Dept.

of CSE 25
 TC1=1=TC activated CH-1
 TC1=0=TC activated CH-1

 TC0=1=TC activated CH-0

 TC0=0=TC activated CH-0

 The address of status register is

A3A2A1A0=1000.

 8257 have 8bit data line and 16 bit address

line.

College of Engg. Kottarakkara, Dept.

of CSE 26
 A0-A3 lines are used to distinguish between
registers ,but they are not distinguish lower
and higher address.
 It is reset by external RESET signal.
 It is also reset by whenever mode set register
is loaded.
 So program initialization with a dummy (00 H).
 FF=1=Higher byte of address
 FF=0=Lower byte of address.

College of Engg. Kottarakkara, Dept.

of CSE 27
 Rotating priority Mode:
 The priority of the channels has a circular
sequence.
 Fixed Priority Rotating Mode:
 The priority is fixed.
 TC Stop Mode
 Auto Load mode
 Extended Write mode

College of Engg. Kottarakkara, Dept.

of CSE 28
Rotating Priority :-
 In the Rotating Priority Mode, the priority of
the channels has a circular sequence. After
each DMA cycle, the priority of each channel
changes. The channel which had just been
serviced will have the lowest priority.
 If the ROTATING PRIORITY bit is not set (set
to a zero). each DMA channel has a fixed
priority. In the fixed priority mode.

College of Engg. Kottarakkara, Dept.

of CSE 29
 If the TC STOP bit is set. a channel is disabled
(i.e.. Its enable bit is reset) after the Terminal
Count (TC) output goes true, thus automatically
preventing further DMA operation on that
channel. The enable bit for that channel must be
re-programmed to continue or begin another
DMA operation.

College of Engg. Kottarakkara, Dept.

of CSE 30
 If the TC STOP bit is not set.
The occurrence of the TC output has no
effect on the channel enable bits. In this case, it
is generally the responsibility of the peripheral to
cease DMA requests in order to terminate a DMA
operation.

College of Engg. Kottarakkara, Dept.

of CSE 31
 The Auto Load mode permits Channel 2 to be
used for repeat block or block chaining
operations, without immediate software
intervention between blocks. Channel 2
registers are initialized as usual for the first
data block

College of Engg. Kottarakkara, Dept.

of CSE 32
 If the EXTENDED WRITE bit is set. the duration of
both the MEMW and I/OW signals is extended by
activating them earlier in the DMA cycle.
 Extended Write option provides alternative timing
for the I/O and memory write signals which
allows the devices to return an early READY and
prevents the unnecessary occurrence of wait
states in the 8257. thus increasing system
throughput.

College of Engg. Kottarakkara, Dept.

of CSE 33
 DMA controller has four modes for data
transfer:
 1. Single Byte Transfer Mode/ Cycle Stealing
 Once the DMAC becomes the bus master, it
will transfer only ONE BYTE and return the
bus back to the microprocessor. As soon as
the microprocessor performs one bus cycle,
DMAC will once again take the bus back from
the microprocessor.
 Both DMAC and microprocessor are
constantly stealing bus cycles from each
other. It is the most popular method of DMA,
because it keeps the microprocessor active in
the background.
College of Engg. Kottarakkara, Dept.
of CSE 34
 After a byte is transferred, the CAR and CWCR
are adjusted accordingly. The system bus is
returned to the µP. For further bytes to be
transferred, the DREQ line must go active
again, and then the entire operation is
repeated.
 2. Block Transfer Mode.
 In this mode, the DMAC is programmed to
transfer all the bytes in one complete DMA
operation. After a byte is transferred, the CAR
and CWCR are adjusted accordingly.

College of Engg. Kottarakkara, Dept.

of CSE 35
 The system bus is returned to the µP, only
after all the bytes are transferred. i.e. TC is
reached or EOP signal is issued. It is the
fastest form of DMA but keeps the
microprocessor inactive for a long time.
 The DREQ signal needs to be active only in
the beginning for requesting the DMA service
initially. Thereafter DREQ can become low
during the transfer.
 3. Demand Transfer Mode
 It is very similar to Block Transfer, except that
the DREQ must active throughout the DMA
operation.

College of Engg. Kottarakkara, Dept.

of CSE 36
 If during the operation DREQ goes low, the
DMA operation is stopped and the busses are
returned to the µP.
 . Once DREQ goes high again, the DMA
operation continues from where it had
stopped.
 4. Cascade Transfer Mode
 In this mode, more than one DMACs are
cascaded together. It is used to increase the
number of devices interfaced to the µP. Here
we have one Master DMAC, to which one or
more Slave DMACs are connected.
 The Slave gives HRQ to the Master on the
DREQ of the Master, and the Master gives
HRQ to the µP on the HOLD of the µP.
College of Engg. Kottarakkara, Dept.
of CSE 37
College of Engg,Kottarakkara,Dept. of
CSE 38
College of Engg,Kottarakkara,Dept. of
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