Received April 3, 2022, accepted April 24, 2022, date of publication May 2, 2022, date of current version May

6, 2022.
Digital Object Identifier 10.1109/ACCESS.2022.3171830

An RF-SoC-Based Ultra-Wideband
Chirp Synthesizer
OMID REYHANIGALANGASHI 1,2 , (Graduate Student Member, IEEE),
DREW TAYLOR 1,2 , (Member, IEEE),
SHRINIWAS KOLPUKE 2,3 , (Graduate Student Member, IEEE),
DEEPAK N. ELLURU 1,2 , (Graduate Student Member, IEEE), FERAS ABUSHAKRA 1,2 ,

ABHISHEK K. AWASTHI 1,2,4 , (Member, IEEE),

AND SIVA-PRASAD GOGINENI 1,2,3 , (Life Fellow, IEEE)
1 Electrical
and Computer Engineering Department, The University of Alabama, Tuscaloosa, AL 35401, USA
2 Remote Sensing Center, The University of Alabama, Tuscaloosa, AL 35487, USA
3 Aerospace Engineering and Mechanics Department, The University of Alabama, Tuscaloosa, AL 35401, USA
4 Department of Electrical and Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies (UPES), Dehradun 248007, India

Corresponding author: Omid Reyhanigalangashi ([email protected])

This work was supported in part by the National Oceanic and Atmospheric Administration (NOAA)/University Corporation for
Atmospheric Research (UCAR) under Contract NA18NWS4620043B, and in part by NOAA/Cooperative Institute for Satellite Earth
System Studies (CISESS) under Contract NA19NES4320002.

ABSTRACT This paper presents the design and development of a digital two-channel chirp synthesizer
using a field-programmable gate array (FPGA) device. To achieve an integrated solution, the design
was implemented on radio-frequency system-on-chip (RF-SoC) technology that includes digital-to-analog
converters (DACs) and other radio-frequency components on-chip. To overcome the timing errors in high-
speed design with DACs operating at 6.144 GHz, a memory-stitching concept was used. A prototype was
developed to validate this concept by generating a baseband chirp with a bandwidth of 1.7 GHz and a sweep
time of 36 µs. The synthetic chirp was upconverted to 3.572-5.272 GHz for use as the transmit signal
for an ultra-wideband radar to characterize the chirp using a 1 km long optical delay line. The transmit
signal was analyzed in terms of phase and amplitude errors and corrected for these errors. The root-mean-
square (RMS) frequency deviation of the predistorted chirp from linearity over the 1.7 GHz bandwidth is
9.64 kHz, realizing a chirp linearity of 0.00057%. The measurement data show comparable performance of
our chirp synthesizer against a commercially available arbitrary-waveform-generator (AWG) operating at a
sampling rate of 60 GHz. The reported chirp synthesizer can be used in frequency-modulated continuous-
wave (FM-CW) and stretch radars. Such radars are widely used for a variety of remote sensing measurements.

INDEX TERMS RF-SoC, chirp-synthesizer, FM-CW, radar, FPGA.

I. INTRODUCTION requirement for these radars is a fast and ultra-linear chirp

Ultra-Wideband (UWB) frequency-modulated continuous- signal.
wave (FM-CW) radars are widely used for airborne snow Many UWB radars use a mixed-signal approach consisting
measurements over sea ice, ice sheets in Greenland and of phase-locked loop (PLL)-based chirp synthesizers with
Antarctica, and land [1]–[4]. In addition, UWB FM-CW a reference low frequency direct digital synthesizer (DDS)
radars have been developed and used for soil moisture and [8]–[13]. The fast chirp required for airborne applications
other remote sensing measurements [5], [6]. UWB stretch results in phase nonlinearities that degrade radar perfor-
radars are also being considered for satellite-based measure- mance. In addition, despite the high bandwidth capability
ments of snow accumulation over ice sheets [7]. A major of these methods, they lack the reconfigurability to support
a wide range of applications. The UWB microwave sig-
nal for FM-CW radars can also be generated using exclu-
The associate editor coordinating the review of this manuscript and sively digital methods. Methods for implementing digital
approving it for publication was Filbert Juwono . chirp synthesizers were introduced as early as 1991 [14], and

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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there have been many studies addressing the design of field- provides the phase and amplitude error analyses and presents
programmable gate array (FPGA)-based chirp synthesizers. the radar measurement results. Finally, Section V concludes
Gomez-Garcia et al. generated a chirp with 750 MHz band- the paper.
width using FPGA through a parallel DDS implementation
and then employed frequency multiplication by a factor of II. FM-CW RADAR PRINCIPLE
eight to obtain a 6 GHz bandwidth [9]. Frequency multiplica- In an FM-CW radar, the transmitted chirp signal frequency is
tion of low frequency chirps results in significant phase noise increased or decreased linearly over the desired bandwidth, B,
degradation. The phase nonlinearity and amplitude modula- within the sweep time of T and can be expressed as follows:
tion of the chirp require extensive post-processing to reduce α 2
)
the range sidelobes. s(t) = ej2π(f0 t+ 2 t (1)
Chua and Koo reported an FPGA-based chirp synthesizer where α = TB and 0 ≤ t ≤ T . In a typical FW-CW radar,
capable of producing a 50 MHz chirp using both DDS and the received signal is mixed with a sample of the transmitted
memory-based methods [15]. Firmansyah and Yamaguchi signal to obtain a beat frequency proportional to the target
developed a memory-based FPGA chirp generator operating range. The beat frequency for the sawtooth chirp is given by:
over a 5 MHz bandwidth with 10 µs sweep time using the
B 2R
OpenCL framework [16]. Wang et al. used an improved fb = ατ = (2)
CORDIC algorithm to design a chirp generator at 2.417 GHz T c
with a bandwidth of 1.25 MHz [17]. Prager et al. reported where fb is the beat frequency in Hz, B is the transmitted chirp
wideband chirp synthesis using a frequency stacking method bandwidth in Hz, T is the chirp sweep time in seconds, R is
on a commercial software-defined radio (SDR) platform [18]. the target range in meters, and c is the propagation velocity
In this paper, we describe a digital chirp synthesizer that of the transmitted wave in m/s.
generates a 1.7 GHz wideband chirp. The reported chirp
synthesizer uses a memory-based approach to generate fast III. RESEARCH METHODOLOGY
ultra-linear chirps appropriate for ultra-wideband airborne A digital chirp synthesizer was developed using a Xilinx
radars for operation on both manned and unmanned aircraft. ZCU111 RF-SoC development board [19], as shown in
Such chirps are very useful for providing near real-time Figure 1. In addition to the FPGA fabric, the RF-SoC is
snow and soil moisture data products to support operational equipped with eight integrated high-speed 14-bit 6.544 GSPS
applications with minimal additional post-processing. The DACs and a quad-core Arm Cortex A53 processor. Using this
developed chirp synthesizer is implemented using Xilinx RF-SoC to design a high-speed memory-based chirp synthe-
radio-frequency system-on-chip (RF-SoC) technology with sizer is challenging because of limited memory storage on the
integrated high-speed digital-to-analog converters (DACs) FPGA fabric and critical timing requirements. As the mem-
operating at a maximum sampling rate of 6.554 GSPS. The ory blocks are distributed across the RF-SoC chip, a higher
high sampling rate of the DAC can lead to timing challenges memory size results in larger interconnect propagation delay
in high-speed designs. To overcome the critical timing errors, throughout the FPGA fabric, leading to unresolvable timing
we used an FPGA-based memory-stitching method that can errors. Therefore, a memory-stitching concept is introduced
extend the chirp bandwidth and offer the opportunity to to overcome critical timing requirements.
implement FM-CW and stretch radars based on an RF-SoC Four identical block-random-access-memories (BRAMs)
platform. were used to develop the proposed chirp synthesizer. As the
To improve the chirp linearity and point target response, total number of cells in each of the instantiated BRAMs
the timing diagram of the system is thoroughly analyzed to is equal, a unique address counter can be utilized to loop
avoid discontinuities between the chirp data coming from dif- through the cells of each BRAM simultaneously. Chirp data
ferent memory elements. In the reported design, we employed were generated using MATLAB and then quantized for con-
central direct memory access (cDMA) method to mini- version to a binary data file. We used the PYNQ framework
mize processor overhead for data transmission to DACs. to develop a driver application for the RF-SoC. A detailed
To demonstrate the synthetic chirp in an operating radar, review of this framework is provided in [20]. On chip level,
an upconversion chain was designed to shift the baseband chirp data are first stored in processor double-data-rate-4
frequency by 3072 MHz to be in the operating frequency (DDR4) memory and then transferred into BRAMs on FPGA
range of an existing ultra-wideband radar at the University fabric through a central DMA system. Each BRAM has its
of Alabama. In addition, we predistorted the transmit chirp own controller, which is managed by central DMA, as shown
to reduce the phase errors and amplitude modulation effects in Figure 1. All subsystem communications between FPGA
to obtain a point target response close to an ideal. Further- fabric and processor system occur through the AXI inter-
more, we corrected the residual radar receiver phase errors to connect based on a 100 MHz pl_clk provided by the ZYNQ
generate an ideal point target response. UltraScale+ processor intellectual-property (IP) core. How-
Section II briefly reviews the operating principle of an ever, the data converter IP has a separate clocking mecha-
FM-CW radar. Section III describes the technical details nism that feeds the rest of the system on FPGA fabric to
of the chirp synthesizer that we developed, and Section IV ensure that the chirp data packets propagate synchronously

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FIGURE 1. Proposed memory-stitching architecture for multi-channel wideband chirp synthesis using RF-SoC technology.

with the DAC clock. In the utilized XCZU28DR RF-SoC, 16 samples, there are 256 bits of data occupy 32 memory
there are two DAC tiles, each including two pairs of DACs. addresses. Thus, for proper data fetching from the BRAMs
In this paper, only one pair of DACs was used to develop in each clock cycle, the address counter increments by
the two-channel chirp synthesizer. The clock to both tiles 32 or 0 × 20.
is supplied by LMX2595 wideband synthesizer, which is The system clock (CLK ) speed can be calculated by divid-
part of a complex off-chip clocking system. Further details ing the desired DAC sampling rate by the total number of
on the ZCU111 clocking architecture are provided in [21]. samples on the data stream path, which, in this case, results
In the reported chirp synthesizer, the DACs were configured in 384 MHz. As shown in the timing diagram in Figure 3,
to operate at a sampling rate of 6.144 GSPS. Because there the address counter, cnt_out triggers the assertion of the
are two pairs of DACs in each tile that are fed by the same Threshold signal whenever the Counter reaches the max-
clock source, they are synchronous with each other. How- imum value. At the falling edge of the Threshold signal,
ever, to synchronize the output chirps with external systems, the Enabler module synchronously enables/disables each
such as radars, a Trigger module was designed to assert a BRAM. In the proposed architecture, an equivalence gate,
Transistor-Transistor Logic (TTL) signal with the activation XNOR, is utilized to compare the Threshold value against
of the first BRAM. This triggering is based on the result of an always high constant to generate control signals for the
the XNOR gate. Enabler and Selector modules. In the Enabler module, the
The chirp data were divided equally into four sections output of the XNOR gate is scanned, and if it is a high
for downloading into each of the BRAMs, as shown in signal, the appropriate signal for enabling the next BRAM is
Figure 2. These data were stored in packets of 256 bits, generated. The Enabler module is a circular shift register that
each including 16 samples of a full-length chirp. We first sequentially enables BRAMs through EN _1 to EN _4 signals
assume that there are N data packets in each of the BRAMs, by shifting the initial value of b0001 whenever the Counter
P0 , . . . , PN −2 , PN −1 , where P0 is the first packet and PN −1 reaches the maximum value. To transmit chirp samples from
is the Nth packet of each subpulse. Each data packet contains the four BRAMs through the DAC, a multiplexer module
16 samples of a subpulse, S0 , . . . , S14 , S15 , where S0 is the was designed. The word length of the input signals IN _1 to
first sample and S15 is the sixteenth sample. An unwrapped IN _4 of the multiplexer is proportional to the DAC data
sample from a data packet is shown in Figure 2. The first stream length, which is 256 bits. In each clock cycle, a data
two most significant bits (MSBs) of a sample packet are packet is placed on the data stream path through mux_out.
zero because of the 14-bit DAC resolution. As the imple- As the Counter module is piped, there are 4-clock cycles of
mented BRAMs are byte-addressable, each sample occupies latency until the address counter starts counting upwards from
two memory addresses. Because each data packet includes zero. At system start-up, as Counter, Enabler, and Selector

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where the second term is zero and Equation (3) can be rewrit-
ten as:
α
s(t) = cos(2π(f0 t + t 2 )) (4)
2
where α = B/T = (f1 − f0 )/T as defined in Equation (1).
Equation (4) can be rewritten in discrete signal form as:
f1 − f0 2
s[n] = cos(2π[f0 n + n ]) (5)
2(N − 1)
Each discrete chirp signal sweeps from f0 to f1 with the total
number of samples equal to N , where 0 ≤ n < N − 1.
Equation (5) represents a periodic waveform as:
s[n + kN ] = s[n] (6)
where k = 1, 2, 3, 4, . . . , m. As shown in Figure 4, the dis-
crete samples are overlapped on top of each other, indicating
that Equation (6) holds true for Equation (5). We assume
that n is equal to n1 + n2 + n3 + n4 . Because the system
is linear, according to the additive property, Equation (5) can
be synthesized by adding multiple subpulses as follows:
s[n1 ] + s[n2 ] + s[n3 ] + s[n4 ] = s[n1 + n2 + n3 + n4 ] (7)
Equation (7) can then be reconstructed as:
s[n1 ] + s[n2 ] + s[n3 ] + s[n4 ] = s[n] (8)
Equations (8) and (6) indicate that the synthesis of an
FIGURE 2. Unwrapped data packets and their distribution across memory.
integrated chirp from multiple subpulses can be achieved
by consecutively transmitting the samples from each sub-
pulse without any delay or overlap. Discontinuities between
modules hold initial values, the first data packet, P0 , from the
samples would result in additional nonlinearity in the chirp
first BRAM, would be placed on the data stream path through
spectrum.
IN _1 for a few more clock cycles than the other samples.
Table 1 lists the resource utilization of the system imple-
This causes disorganization in overall streaming, which is
mented on the XCZU28DR RF-SoC chip. It can be observed
addressed in the next section. To avoid this issue and place
that resource utilization of the reported chirp synthesizer
data packets onto the streaming path for only one clock cycle,
on FPGA fabric is low. Resource utilization can be mini-
a ClockEnable module was designed and added to the system
mized by saving chip area and having faster critical path
architecture. This compensates for the initial condition of the
timing [22]. Optimized HDL programming is a key step in
counter by allowing the multiplexer to propagate data after
balancing FPGA resource utilization and chip area usage.
waiting for four clock cycles. As the output of Selector mod-
In the proposed design, we addressed chip area usage and
ule, mux_sel, is updated at the falling edge of the Threshold,
critical path improvement by utilizing multi-BRAM tiles and
one clock cycle latency is added to the Selector module. This
pipe-lining the signal path. In addition, the overall on-chip
ensures that inputs of multiplexer are switched only when all
power consumption was 3.414 W. However, 2.297 W of the
data packets from each of the BRAMs are passed through
total power consumption is related to the quad-core Arm
mux_out, as shown in Figure 3; otherwise, data packet loss
Cortex A53. Figure 5 shows the breakdown of the power
would be expected, which will result in discontinuity between
consumption in our design. As shown, a large portion of the
the chirp data.
power consumption belongs to the ARM processor on the
XCZU28DR RFSoC chip. The amount of consumed power
IV. RESULTS AND DISCUSSION
by the logic segments and BRAM blocks is listed in Table 1.
Experiments showed that any discontinuity between the
To evaluate the proposed chirp synthesizer in a real radar
data packets of BRAMs would result in high-range side-
system, a measurement test bench was set up, as shown in
lobes. To synthesize a continuous ultra-wideband chirp
Figure 6. As the UWB radar in this setup operates from
from subpulses, s(t) must be a continuous chirp signal,
2.7-10.7 GHz, a baseband chirp from 500-2200 MHz was
as defined in Equation (1). Using Euler’s equation, s(t) can
synthesized and upconverted to 3.572-5.272 GHz. For this
be expressed as:
purpose, a local oscillator (LO) signal of 3072 MHz was
α 2 α generated from the off-chip clocking system and supplied to
s(t) = cos(2π(f0 t + t )) + jsin(2π(f0 t + t 2 ) (3)
2 2 the LO port of the mixer. A pair of low-pass filters (LPF)

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FIGURE 3. Timing diagram of the hardware architecture in the Figure 1.

passed through a low-pass filter to eliminate extra harmonics

in the frequency range of operation of the UWB radar. A 1-km
long optical delay line was used for the loopback measure-
ment, and the intermediate-frequency (IF) signal was mea-
sured using a high-speed oscilloscope. We used a Keysight
M9502A arbitrary waveform generator (AWG) to generate a
500-2200 MHz baseband chirp and upconverted it to compare
our chirp generator performance with an off-the-shelf AWG.
Figure 7 shows a comparison of the point target response
obtained with our chirp generator and the Keysight AWG
FIGURE 4. Periodic chirp waveform as s[n + kN] = s[n] for k = 0, 1, 2, 3.
operating at 60 GSPS along with an ideal point response with
a Hanning window. Gaussian noise was added to the ideal
response to adjust the noise floor between the measurements
and ideal response.
The choice of a window for transforming the time-domain
IF signal into the frequency domain involves a trade-off
in resolution, near sidelobes, and decay rate of the far-off
sidelobes. We used Hanning window because it has low near
range sidelobes, 31.5 dB below the main lobe, and 18 dB
for octave decay rate for far-off sidelobes as summarized in
Table 2 [23], [24]. The high decay rate of the sidelobes is
important for identifying multiple reflections in the system
and other weak targets. The Blackman-Harris window is also
a good choice for analyzing FM-CW radar signals because
FIGURE 5. Power consumption breakdown of the proposed architecture.
of its very low first sidelobes and high fall-off rate. However,
it has a wide main lobe, which results in degraded resolution.
We used a Hanning window to isolate the primary delay line
was used with an ultra-wideband amplifier to condition the return from multiple reflections. In Figure 7, the asymmetri-
LO signal for the required drive level of the mixer. The cal nearby sidelobes on both sides of the main lobe and the
baseband chirp from Channel 1 of the reported synthesizer far-off sidelobes indicate amplitude and phase errors in the
was passed through a DC block and then low-pass filtered chirp and radar system [25].
to reduce the harmonics. All ports of the mixer were padded To compensate for the phase and amplitude errors,
with attenuators to reduce multiple reflections. In addition, we assume that an ideal transmit chirp can be expressed as
the output signal from the mixer RF port was attenuated follows:
to reduce third-order products. The upconverted chirp was
x(t) = ej(ω0 t+π αt
2)
amplified, filtered with a customized band-pass filter, and (9)

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FIGURE 6. RADAR measurement test-bench block diagram.

FIGURE 7. Measured IF response of the radar.

FIGURE 8. Comparison of phase errors in transmit chirp.

Now, consider the transmit chirp, with both amplitude and

phase errors, is measured with an oscilloscope as follows: and downloaded into the BRAMs. Thus, we can predistort the
transmit chirp such that the final synthetic upconverted chirp
xd (t) = A0 [1 + ma(t)]ej(ω0 t+π αt
2 +φ(t))
(10) is almost free from phase and amplitude errors. In this regard,
By multiplying xd (t) by x ∗ (t), the amplitude and phase errors the upconverted chirp was digitized using a high-speed oscil-
can be determined as follows: loscope with a sampling rate of 25 GSPS. The measured
phase errors in the transmit chirp over the frequency range
xe (t) = xd (t)e−j(ω0 t+π αt
2)
(11) of 3.572-5.272 GHz before and after predistortion is shown
in Figure 8.
Which results in: As shown in Figure 8, polynomial and sinusoidal phase
xe (t) = A0 [1 + ma(t)]ejφ(t) (12) errors occur after upconverting the baseband chirp to
the higher frequency band. The polynomial error can be
where φ(t) is the unwrapped phase of xe (t) and [1 + ma(t)] attributed to the group delay of the band-pass filter, which has
is the envelope of the xe (t). After obtaining the phase and a sharp cut-off. The measured group delay and S-parameters
amplitude errors owing to the memory-based architecture of of the fabricated band-pass filter are shown in Figure 9.
the proposed system, any waveform data can be generated We had to use a band-pass filter with a sharp cut-off to

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FIGURE 9. Measured S-parameters and group delay of the customized

band-pass filter.
FIGURE 11. Measured IF response of radar after predistortion.

FIGURE 10. IF signal simulation in a 1 km long optical-delay line using

the measured synthetic chirp from RF-SoC.

reduce the LO leakage of the mixer from degrading radar FIGURE 12. The FM-CW concept with beat signal timing.
performance. As shown in Figure 9, group delay of the band-
pass filter near the lower edge of the pass-band varied from
12-14 ns. We were able to predistort the upconverted transmit suppressed using the aforementioned predistortion approach.
chirp to reduce the phase errors to near zero, as shown in The phase errors between our work and the Keysight AWG
Figure 8. We attribute the remaining small phase errors in the after predistortion show relatively identical results; both are
transmit chirp to the quantization effect on the downloaded close to zero.
data into memories, DAC nonlinearities, and errors in the In addition, we developed an ideal FM-CW radar simulator
measurement instruments and cables. To validate our exper- to characterize the measured chirp. Figure 10 shows the sim-
iment, a linear chirp with 1.7 GHz bandwidth was directly ulation results of an ideal FM-CW radar point target response
synthesized from 3.572-5.272 GHz using the Keysight AWG for the digitized chirp with and without predistortion, along
to avoid upconversion process. As shown in Figure 8, a ripple with an ideal response. As shown in Figure 10, the simulation
can be observed in the phase error of the chirp that was results indicate that the phase and amplitude predistortions
directly synthesized by the Keysight AWG. This ripple is improve the IF signal performance.

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FIGURE 13. Measured phase errors in receiver.

FIGURE 15. Suppressing amplitude modulations in transmit chirp with

predistortion.

FIGURE 16. Measured baseband chirp frequency versus time.

TABLE 1. Resource utilization report of the proposed design.

FIGURE 14. Measured IF response with receiver phase errors removal in

post-processing.

We also evaluated our corrected upconverted chirp char-

acteristics by measuring the radar IF signal and comparing
it with a directly synthesized predistorted chirp over the fre-
quency range of 3.575-5.275 GHz using the Keysight AWG,
as shown in Figure 11. As can be observed in the solid
curve in Figure 11, the leading and trailing edges of the first
sidelobe deviated by approximately 2 dB from the ideal for
our chirp, which agrees with the results measured with the
Keysight AWG chirp. After correcting phase and amplitude these errors, we assume that y(t) is an ideal IF signal, which
errors in the transmit chirp from our proposed design, the is modelled as follows:
asymmetrical sidelobes in solid curve in Figure 11, are a yideal (t) = ejπ(2f0 τ +2ατ t−ατ
2)
(13)
result of quartic phase errors [25]–[27]. This caused a 2 dB
deviation from the ideal response for our predistorted chirp where τ is the amount of delay (tDelay ) for the arrival of
and can be interpreted as the residual phase and amplitude the received signal, which is equal to 2R/c and t is the
errors introduced by the radar receiver. To further reduce duration of the beat signal (tbeat ), as shown in Figure 12. The

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TABLE 3. Performance comparison with some existing works.

FIGURE 17. Comparison of frequency errors before and after corrections.

TABLE 2. Comparison of different windowing functions.

receiver phase errors in post-processing stage. As can be

seen in Figure 14, the measured IF signal matches the ideal
response after removal of the receiver phase errors. Measure-
ment results show that the proposed chirp synthesizer based
on the XCZU28DR can be used in high performance and
miniaturized radar applications.
Figure 15 shows an improvement in removing the ampli-
tude modulations in the measured time-domain FM-CW sig-
nal after predistortion. The measured frequency sweep of the
transmitted baseband chirp over time is shown in Figure 16.
As can be seen, the chirps with and without predistortions are
very close to the ideal chirp over the specified bandwidth. The
frequency deviation of the synthesized chirps from that of an
ideal linear chirp is shown in Figure 17. The RMS frequency
error of the predistorted chirp after upconversion process
measured received signal with phase errors in the receiver can was calculated to be 9.64 kHz. The RMS frequency error
be formulated as: before predistorting the upconverted chirp was 40.90 kHz.
These measurements indicate that there is around 31.26 kHz
yreceived (t) = ej(π(2f0 τ +2ατ t−ατ
2 )+φ (t))
rdl (14)
of improvement in RMS frequency error after applying the
where φrdl (t) is residual phase error from the receiver and phase and amplitude corrections. Moreover, as shown in Fig-
delay line. Using Equations (13) and (14), one can obtain the ure 17, a nonlinear trend can be observed in the frequency
phase errors in the receiver after multiplying the yreceived (t) errors related to the upconverted synthetic chirp without pre-
by y∗ideal (t) as follows: distortion. After compensating for the phase and amplitude
errors with predistortion, the nonlinear trend in the frequency
ejφrdl (t) = yreceived (t)y∗ideal (t) (15)
errors was suppressed. The RMS frequency error of the base-
Figure 13 shows measured phase errors in the receiver. band chirp before upconversion was 10.49 kHz as shown
This is verified by obtaining the receiver phase errors, when by the black curve in Figure 17. The overall chirp linearity
the Keysight AWG was used to synthesize the input chirp to could be estimated as the ratio of the RMS frequency error
the radar. It is possible to compensate for the receiver phase to the full-span chirp bandwidth [28]. With the calculated
errors in post-processing stage. In this regard, after obtaining RMS frequency error of 9.64 kHz in the upconverted chirp
the phase errors of the receiver using Equation (15), we can with predistortion, a linearity error of 0.00057% is obtained
eliminate these errors by multiplying the measured received over 1.7 GHz of bandwidth within 36 µs sweep time. Table 3
signal by e−jφrdl (t) . Figure 14 shows the IF signal measure- provides a performance comparison with existing studies in
ment results from our proposed system, after eliminating the the literature.

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As mentioned earlier, one of the applications of chirp radar [5] M. Lort, A. Aguasca, C. López-Martínez, and T. M. Marín, ‘‘Initial eval-
is in remote sensing of snow and soil moisture. Kim et al. uation of SAR capabilities in UAV multicopter platforms,’’ IEEE J. Sel.
Topics Appl. Earth Observ. Remote Sens., vol. 11, no. 1, pp. 127–140,
reported that to obtain a good estimate of the snow water Jan. 2018, doi: 10.1109/JSTARS.2017.2752418.
equivalent (SWE), the radar resolution must be better than [6] F. Abushakra, N. Jeong, D. N. Elluru, A. K. Awasthi, S. Kolpuke, T. Luong,
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V. CONCLUSION and frequency multiplication for airborne FMCW snow probing radar,’’ in
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A digital chirp generator was designed and implemented on
[10] K.-R. Kim, S. Kim, C.-H. Ki, T.-H. Kim, H. Yang, and J.-H. Kim,
XCZU28DR RF-SoC. Moreover, a memory-stitching con- ‘‘Development and comparison of DDS and multi-DDS chirp waveform
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the overall bandwidth within 36 µs. The simulation and [12] Z. Shen, H. Jiang, H. Li, Z. Zhang, F. Yang, J. Liu, and H. Liao, ‘‘A 12-
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measurement results show that by predistorting the phase 78 MHz/µs chirp slope and high chirp linearity,’’ IEEE Trans. Circuits
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driven ADPLL chirp synthesizer with ramp-interpolating linearization for
LFM chirp. Radar loop-back measurements indicate −30 dB FMCW radar application in 65 nm CMOS,’’ in Proc. IEEE Int. Symp.
sidelobes in the IF signal impulse response using Hanning Circuits Syst. (ISCAS), Florence, Italy, May 2018, pp. 1–4.
weighting and show a response comparable to that of a com- [14] R. J. Durrant and S. M. Parkes, ‘‘The implementation of high time band-
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channel to achieve a significantly larger bandwidth chirp. tion UAV SAR,’’ Prog. Electromagn. Res., vol. 99, pp. 71–88, 2009.
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ACKNOWLEDGMENT [18] S. Prager, T. Thrivikraman, M. Haynes, J. Stang, D. Hawkins, and
Authors would like to acknowledge two anonymous review- M. Moghaddam, ‘‘Ultrawideband synthesis for high-range-resolution
ers for their insightful comments and suggestions as well as software-defined radar,’’ IEEE Trans. Instrum. Meas., vol. 69, no. 6,
pp. 3789–3803, Jun. 2020.
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research assistants. RFSoC for digital-RF communications,’’ IEEE Micro, vol. 38, no. 2,
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[20] J. Goldsmith, C. Ramsay, D. Northcote, K. W. Barlee, L. H. Crockett,
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[27] K. Peek, ‘‘Estimation and compensation of frequency sweep nonlinearity DEEPAK N. ELLURU (Graduate Student Member,
in FMCW radar,’’ M.S. thesis, Dept. Elect. Eng., Math. Comput. Sci., Univ. IEEE) received the bachelor’s degree in electron-
Twente, Enschede, The Netherlands, 2011. ics and communication engineering from India
[28] P. V. Brennan, Y. Huang, M. Ash, and K. Chetty, ‘‘Determination of sweep and the master’s degree from The University of
linearity requirements in FMCW radar systems based on simple voltage- Alabama in Huntsville, in 2018. He is currently
controlled oscillator sources,’’ IEEE Trans. Aerosp. Electron. Syst., vol. 47, pursuing the Ph.D. degree. He joined the Remote
no. 3, pp. 1594–1604, Jul. 2011. Sensing Center, The University of Alabama,
[29] Y. Kim and T. J. Reck, ‘‘A Ku -band CMOS FMCW radar transceiver for
in 2019. His research interests include microwave
snowpack remote sensing,’’ IEEE Trans. Microw. Theory Techn., vol. 66,
circuits, antenna design, and microwave remote
no. 5, pp. 2480–2494, May 2018.
[30] W. Wu, R. B. Staszewski, and J. R. Long, ‘‘A 56.4-to-63.4 GHz multi- sensing technology.
rate all-digital fractional-N PLL for FMCW radar applications in 65 nm
CMOS,’’ IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1081–1096,
FERAS ABUSHAKRA received the B.Sc. degree
May 2014.
[31] M. Z. Straayer, A. V. Messier, and W. G. Lyons, ‘‘Ultra-linear superwide- in electrical engineering from the Jordan Univer-
band chirp generator using digital compensation,’’ in IEEE MTT-S Int. sity of Science and Technology (JUST), Irbid,
Microw. Symp. Dig., San Francisco, CA, USA, Jun. 2006, pp. 403–406. Jordan, and the M.Sc. degree in wireless com-
munication engineering from Al-Yarmouk Uni-
versity, Jordan, in 2017. He is currently pursuing
OMID REYHANIGALANGASHI (Graduate Stu- the Ph.D. degree in electrical engineering with
dent Member, IEEE) received the B.Sc. degree The University of Alabama (UA), Tuscaloosa.
in electrical engineering from Karaj Islamic Azad His research interests include dielectric resonator
University, Alborz, Iran, in 2014, and the M.Sc. antennas, UWB arrays, waveguides, and radar
degree in electrical engineering from Qazvin systems.
Islamic Azad University, Qazvin, Iran, in 2017. He
worked as a Project Engineer for 4 years in Fiber-
Home Telecommunication Technologies Co., Ltd.,
ABHISHEK K. AWASTHI (Member, IEEE)
a globally renowned information and communi-
received the B.Tech. degree in electronics and
cation network product and solution provider. In
communication engineering from the Ajay Kumar
August 2019, he joined the School of Electrical and Computer Engineering
Garg Engineering College, Ghaziabad (UPTU,
at the University of Alabama with a Research Assistantship (RA) to work
Lucknow), in 2008, the M.Tech. degree in digi-
toward a Ph.D. degree in electrical engineering. His research interests include
tal communication from the Ambedkar Institute
field-programmable gate array (FPGA), digital signal processing (DSP), and
of Technology, Delhi (GGSIP University, Delhi),
embedded systems.
in 2011, and the Ph.D. degree from the Department
of Electrical Engineering (RF and Microwave),
DREW TAYLOR (Member, IEEE) received the Indian Institute of Technology Kanpur, in 2018.
B.S. and M.S. degrees in electrical engineering He was working as an Assistant Research Engineer at the Remote Sensing
from The University of Alabama, Tuscaloosa, Center, The University of Alabama, for more than two years. Since January
AL, USA, in 2008 and 2011, respectively, and 2022, he has been an Assistant Professor with the Department of Electrical
the Ph.D. degree in electrical and computer and Electronics Engineering, University of Petroleum and Energy Studies
engineering from Mississippi State University, (UPES), Dehradun, India. His current research interests include phased
Mississippi State, MS, USA, in 2018. He is cur- antenna arrays and ultra-wideband radar systems.
rently an Assistant Professor of electrical and com-
puter engineering with the Remote Sensing Center,
The University of Alabama. His research interests
SIVA-PRASAD GOGINENI (Life Fellow, IEEE)
include digital and embedded systems, radar signal processing, and remote
was the Founding Director of the NSF Science
sensing of the earth.
and Technology Center for Remote Sensing of
Ice Sheets (CReSIS), The University of Kansas,
SHRINIWAS KOLPUKE (Graduate Student from 2005 to 2016. He has served as a Manager
Member, IEEE) received the B.E. degree in for the NASA’s Polar Program, from 1997 to 1999.
electronics engineering from Swami Ramanand He was a Fulbright Senior Scholar at the Uni-
Teerth Marathwada University, Nanded, India, versity of Tasmania, in 2002. He is currently a
in 2011, and the Master of Science degree in VLSI Cudworth Professor of engineering at The Univer-
and embedded system design from Jawaharlal sity of Alabama and the Director of the Remote
Nehru Technological University Hyderabad, India, Sensing Center. He has been involved with radar sounding and imaging of
in 2013. He is currently pursuing the Ph.D. degree ice sheets for approximately 35 years and contributed to the first successful
in aerospace engineering and mechanics with The demonstration of SAR imaging of an ice bed through ice more than three km
University of Alabama, Tuscaloosa. He joined the thick. He is also led the development of ultra-wideband radars for measuring
Master of Science Program in aerospace engineering at The University the thickness of snow over sea ice and the mapping of internal layers in polar
of Kansas, Lawrence, and graduated in early 2017. His research interests firm and ice. He has received the Louise Byrd Graduate Educator Award at
include design, development, and optimization of FM-CW radars for snow The University of Kansas.
measurements.

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