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TUSB2036
SLLS372I – MARCH 2000 – REVISED MARCH 2017

TUSB2036 2- or 3-Port Hub for the Universal Serial Bus With Optional Serial EEPROM
Interface
1 Features 2 Applications
1• Fully Compliant With the USB Specification as a • Computer Systems
Full-Speed Hub: TID #30220242 • Docking Stations
• Integrated USB Transceivers
• 3.3-V Low-Power ASIC Logic 3 Description
• One Upstream Port and 2 or 3 Programmable The TUSB2036 hub is a 3.3-V CMOS device that
Downstream Ports provides up to three downstream ports in compliance
with the USB 2.0 specification. Because this device is
– Total Number of Ports (2 or 3) Selected by implemented with a digital state machine instead of a
Input Pin microcontroller, no firmware programming is required.
– Total Number of Permanently Connected Ports Fully-compliant USB transceivers are integrated into
Is Selected by 2 Input Pins the ASIC for all upstream and downstream ports. The
downstream ports support both full-speed and low-
• Two Power Source Modes
speed devices by automatically setting the slew rate
– Self-Powered Mode according to the speed of the device attached to the
– Bus-Powered Mode ports. The configuration of the BUSPWR pin selects
• All Downstream Ports Support Full-Speed and either the bus-powered or the self-powered mode.
The introduction of the DP0 pullup resistor disable
Low-Speed Operations
pin, DP0PUR, makes it much easier to implement an
• Power Switching and Overcurrent Reporting Is onboard bus/self-power dynamic-switching circuitry.
Provided Ganged or Per Port With the new function pin, the end-equipment vendor
• Supports Suspend and Resume Operations can reduce the total board cost while adding
• Suspend Status Pin Available for External Logic additional product value.
Power Down Device Information(1)
• Supports Custom Vendor ID and Product ID With PART NUMBER PACKAGE BODY SIZE (NOM)
External Serial EEPROM
TUSB2036 HLQFP (32) 7.00 mm × 7.00 mm
• 3-State EEPROM Interface Allows EEPROM
(1) For all available packages, see the orderable addendum at
Sharing the end of the datasheet.
• Push-Pull Outputs for PWRON Eliminate the Need
for External Pullup Resistors USB-Tiered Configuration Example
• Noise Filtering on OVRCUR Provides Immunity to
Voltage Spikes
• Supports 6-MHz Operation Through a Crystal
Input or a 48-MHz Input Clock
• Output Pin Available to Disable External Pullup
Resister on DP0 for 3 ms After Reset or After
Change on BUSPWR and Enable Easy
Implementation of Onboard Bus/Self-Power
Dynamic Switching Circuitry
• No Special Driver Requirements; Works
Seamlessly With Any Operating System With USB
Stack Support
• Available in 32-Pin HLQFP Package With a 0.8-
mm Pin Pitch (JEDEC − S-PQFP-G For Low-
Profile Quad Flat Pack)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB2036
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 11
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 8.5 Programming........................................................... 13
4 Revision History..................................................... 2 9 Application and Implementation ........................ 15
9.1 Application Information............................................ 15
5 Description (Continued) ........................................ 3
9.2 Typical Application .................................................. 16
6 Pin Configuration and Functions ......................... 4
10 Power Supply Recommendations ..................... 19
7 Specifications......................................................... 6
10.1 TUSB2036 Power Supply ..................................... 19
7.1 Absolute Maximum Ratings ..................................... 6
10.2 Downstream Port Power ....................................... 19
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6 11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
7.4 Thermal Information .................................................. 7
11.2 Layout Example .................................................... 20
7.5 Electrical Characteristics........................................... 7
7.6 Differential Driver Switching Characteristics (Full 12 Device and Documentation Support ................. 21
Speed Mode) ............................................................. 7 12.1 Receiving Notification of Documentation Updates 21
7.7 Differential Driver Switching Characteristics (Low 12.2 Community Resources.......................................... 21
Speed Mode) ............................................................. 8 12.3 Trademarks ........................................................... 21
7.8 Typical Characteristics .............................................. 9 12.4 Electrostatic Discharge Caution ............................ 21
8 Detailed Description ............................................ 10 12.5 Glossary ................................................................ 21
8.1 Overview ................................................................. 10 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 10 Information ........................................................... 21

4 Revision History
Changes from Revision H (January 2016) to Revision I Page

• Changed pin OVRCUR1, OVRCUR2 and OVRCUR3 I/O column From: "O" To: "I" in the Pin Functions table ................... 5
• Changed pin MODE, NP3, NPINT1−0 and VCC I/O column From: – To: "I" in the Pin Functions table................................. 5

Changes from Revision G (May 2015) to Revision H Page

• Changed the description of f(OPRH) From: "high speed mode" To: "full speed mode" in the Recommended Operating
Conditions .............................................................................................................................................................................. 6

Changes from Revision F (September 2013) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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5 Description (Continued)
The EXTMEM (pin 26) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor
and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General
Purpose USB Hub.
The TUSB2036 supports both bus-powered and self-powered modes. External power-management devices,
such as the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports
and to detect an overcurrent condition from the downstream ports individually or ganged.
An individually port power controlled hub switches power on or off to each downstream port as requested by the
USB host. Also when an individually port power controlled hub senses an over-current event, only power to the
affected downstream port will be switched off. A ganged hub switches on power to all its downstream ports when
power is required to be on for any port. The power to the downstream ports is not switched off unless all ports
are in a state that allows power to be removed. Also when a ganged hub senses an over-current event, power to
all downstream ports will be switched off.
The logic level of the MODE pin controls the selection of a crystal input to drive an internal oscillator or an
external clock source.

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6 Pin Configuration and Functions

VF Package
32-PIN HLQFP
(Top View)

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Power source indicator. BUSPWR is an active-low input that indicates whether the downstream ports source their
BUSPWR 8 I power from the USB cable or a local power supply. For the bus-power mode, this pin must be pulled low, and for
the self-powered mode, this pin must be pulled to 3.3 V. Input must not change dynamically during operation.
DM0 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1 11
DM2 15 I/O USB differential data minus. DM1–DM3 paired with DP1–DP3 support up to four downstream USB ports.
DM3 19
DP0 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
Pullup resistor connection. When a system reset happens (RESET being driven to low, but not USB reset) or any
logic level change on BUSPWR pin, DP0PUR output is inactive (floating) until the internal counter reaches a 15-
DP0PUR 27 O
ms time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next
system reset event occurs or there is a BUSPWR logic level change.
DP1 12
DP2 16 I/O USB differential data plus. DP1–DP3 paired with DM1–DM3 support up to four downstream USB ports.
DP3 20
EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin is disabled and
EECLK 5 O must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the
EEPROM with a 100-μA internal pulldown.
EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects
EEDATA/ between ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low,
6 I/O
GANGED EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-μA
pulldown. This standard TTL input must not change dynamically during operation.
When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, pins 5 and
EXTMEM 26 I
6 are configured as the clock and data pins of the serial EEPROM interface, respectively.
GND 7, 28 GND pins must be tied to ground for proper operation.

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Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
Overcurrent Protection for bus-powered hub (active low). /Power Switching for self-powered hub (active low). The
OCPROT/
21 I pin has a different meaning for the bus or self-powered hub. If the pin is logic high the internal pulldown is
PWRSW
disabled. (1) (2)
OVRCUR1 10 Overcurrent input. OVRCUR1 − OVRCUR3 are active low. For per-port overcurrent detection, one overcurrent
input is available for each of the three downstream ports. In the ganged mode, any OVRCUR input may be used
OVRCUR2 14
I and all OVRCUR pins must be tied together. OVRCUR pins are active low inputs with noise filtering logic. Each
OVRCURn input is sampled every 2 ms and any input which is valid for two consecutive samples will be passed to
OVRCUR3 18
the internal logic. OVRCUR3 has an internal pull-up that can be enabled for the 2-port operation.
PWRON1 9 Power-on/-off control signals. PWRON1–PWRON3 are active low, push-pull outputs that enables the external
power switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However,
PWRON2 13 O
the external power switches that connect to these pins must be able to operate with 3.3-V inputs because these
PWRON3 17 outputs cannot drive 5-V signals.
RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted,
RESET 4 I all logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V
VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window.
Suspend status. SUSPND is an active high output available for external logic power-down operations. During the
SUSPND 32 O
suspend mode, SUSPND is high. SUSPND is low for normal operation.
Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core
MODE 31 I of the device and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is
selected as the clock source and 48-MHz oscillator or other on-board clock source can be used.
Number of ports is 3. Active low input. A logic 0 configures the system to use 3 ports. A logic 1 configures the
NP3 24 I
system to use 2 ports.
NPINT0 22
I Number of ports internal to hub system, which are permanently attached (see Table 1).
NPINT1 23
VCC 3, 25 I 3.3-V supply voltage
Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An
XTAL1/CLK48 30 I internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high,
XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed.
XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.

(1) If the hub is implemented to be bus-powered (via BUSPWR tying to GND):

(a) TUSB2036 reports to the host that the hub end-product downstream ports are power-switched (this is required by the USB 2.0
specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification requirement.
(b) Pin 21 acts as overcurrent protection (OCPROT) implementation indication pin for the bus-powered hub. The overcurrent protection
implementation is reported through the wHubCharacteristics. D4 bit in the hub descriptor.
(c) When OCPROT is low, the TUSB2036 reports to the host that the hub end-product provides overcurrent protection and the
wHubCharacteristics. D4 bit is set to 0.
(d) When OCPROT is high, the TUSB2036 reports to the host that the hub end-product does not provide overcurrent protection and the
wHubCharacteristics. D4 bit is set to 1.
(2) If the hub is implemented to be self-powered (via BUSPWR tying to 3.3-V VCC):
(a) TUSB2036 reports to the host that the hub end-product provides overcurrent protection to the downstream ports (this is required by
the USB 2.0 specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification
requirement.
(b) Pin 21 acts as power switching (PWRSW) implementation indication pin for the self-powered hub. The power-switching
implementation is reported through the bPwrOn2PwrGood field in the hub descriptor.
(c) When PWRSW is low, the TUSB2036 reports to the host that the hub end-product has port power switching at the downstream ports
and the bPwrOn2PwrGood is set to 50 units (100 ms).
(d) When PWRSW is high, the TUSB2036 reports to the host that the hub end-product does not have port power switching at the
downstream ports and the bPwrOn2PwrGood is set to 0 units (0 ms).

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) –0.5 3.6 V
VI Input voltage –0.5 VCC + 0.5 V
VO Output voltage –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 V or VI < VCC ±20 mA
IOK Output clamp current VO < 0 V or VO < VCC ±20 mA
TA Operating free-air temperature 0 70 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage levels are with respect to GND.

7.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VI Input voltage, TTL/LVCMOS (1) 0 VCC V
VO Output voltage, TTL/LVCMOS (2) 0 VCC V
VIH(REC) High-level input voltage, signal-ended receiver 2 VCC V
VIL(REC) Low-level input voltage, signal-ended receiver 0.8 V
VIH(TTL) High-level input voltage, TTL/LVCMOS (1) 2 VCC V
(1)
VIL(TTL) Low-level input voltage, TTL/LVCMOS 0 0.8 V
TA Operating free-air temperature 0 70 °C
R(DRV) External series, differential driver resistor 22 (–5%) 22 (+5%) Ω
f(OPRH) Operating (dc differential driver) full speed mode 12 Mb/s
f(OPRL) Operating (dc differential driver) low speed mode 1.5 Mb/s
VICR Common mode, input range, differential receiver 0.8 2.5 V
tt Input transition times, TTL/LVCMOS (1) 0 25 ns
TJ Junction temperature range (3) 0 115 °C

(1) Applies for input and bidirectional buffers.

(2) Applies for output and bidirectional buffers.
(3) These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.

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7.4 Thermal Information

TUSB2036
THERMAL METRIC (1) VF (HLQFP) UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance 71.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.4 °C/W
RθJB Junction-to-board thermal resistance 29.4 °C/W
ψJT Junction-to-top characterization parameter 2.4 °C/W
ψJB Junction-to-board characterization parameter 29.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics

over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
TTL/LVCMOS IOH = –4 mA VCC – 0.5
VOH High-level output voltage R(DRV) = 15 kΩ to GND 2.8 V
USB data lines
IOH = –12 mA (without R(DRV)) VCC – 0.5
TTL/LVCMOS IOL = 4 mA 0.5
VOL Low-level output voltage R(DRV) = 1.5 kΩ to 3.6 V 0.3 V
USB data lines
IOL = 12 mA (without R(DRV)) 0.5
TTL/LVCMOS 1.8
VIT+ Positive input threshold V
Single-ended 0.8 V ≤ VICR ≤ 2.5 V 1.8
TTL/LVCMOS 0.8
VIT– Negative-input threshold V
Single-ended 0.8 V ≤ VICR ≤ 2.5 V 1
Input hysteresis (1) TTL/LVCMOS 0.3 0.7
Vhys mV
(VT+ – VT–) Single-ended 0.8 V ≤ VICR ≤ 2.5 V 300 500
TTL/LVCMOS V = VCC or GND (2) ±10
IOZ High-impedance output current μA
USB data lines 0 V ≤ VO ≤ VCC ±10
IIL Low-level input current TTL/LVCMOS VI = GND –1 μA
IIH High-level input current TTL/LVCMOS VI = VCC 1 μA
z0(DRV) Driver output impedance USB data lines Static VOH or VOL 7.1 19.9 Ω
VID Differential input voltage USB data lines 0.8 V ≤ VICR ≤ 2.5 V 0.2 V
Normal operation 40 mA
ICC Input supply current
Suspend mode 1 μA

(1) Applies for input buffers with hysteresis.

(2) Applies for open drain buffers.

7.6 Differential Driver Switching Characteristics (Full Speed Mode)

over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tr Transition rise time for DP or DM See Figure 1 and Figure 2 4 20 ns
tf Transition fall time for DP or DM See Figure 1 and Figure 2 4 20 ns
(1)
t(RFM) Rise/fall time matching (tr/tf) × 100 90% 110%
VO(CRS) Signal crossover output voltage (1) 1.3 2.0 V

(1) Characterized only. Limits are approved by design and are not production tested.

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7.7 Differential Driver Switching Characteristics (Low Speed Mode)

over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
(1)
tr Transition rise time for DP or DM CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns
tf Transition fall time for DP or DM (1) CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns
t(RFM) Rise/fall time matching (1) (tr/tf) × 100 80% 120%
VO(CRS) Signal crossover output voltage (1) CL = 200 pF to 600 pF 1.3 2.0 V

(1) Characterized only. Limits are approved by design and are not production tested.

22 Ω
1.5 kΩ
15 kΩ

22 Ω

15 kΩ

Figure 1. Differential Driver Switching Load

Figure 2. Differential Driver Timing Waveforms

VCC
Logic high Vhys
VIH
VIT+
VIT-
VIL
Logic low
0V

Figure 3. Single-Ended Receiver Input Signal Parameter Definitions

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7.8 Typical Characteristics

1.5

V ID - Diff erential Receiver Input Sensitivity - V

1.3

0.5

0.2

0
0 1 2 3 4
0.8 2.5 3.6
VICR - Common Mode Input Rang e - V
Figure 4. Differential Receiver Input Sensitivity vs Common Mode Input Range

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8 Detailed Description

8.1 Overview
The TUSB2036 hub is a 3.3-V CMOS device that provides up to three downstream ports in compliance with the
USB 2.0 specification. Because this device is implemented with a digital state machine instead of a
microcontroller, no firmware programming is required. Fully-compliant USB transceivers are integrated into the
ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed
devices by automatically setting the slew rate according to the speed of the device attached to the ports.

8.2 Functional Block Diagram

DP0 DM0

1 2
USB
Transceiver 27
DP0PUR
32
SUSPND

M 1
U 30
Suspend /Resume X XTAL1/CLK48
Logic and 0 OSC/PLL 29
SIE XTAL2
Frame Timer 31
Hub Repeater MODE
4
RESET
26
EXTMEM

6
SIE Interface Serial EEDATA/GANGED
Logic EEPROM
Interface 5
EECLK

Port 1
Logic 24
NP3
Port 2 23, 22
Hub /Device NPINT(1- 0)
Logic Command 21
OCPROT/PWRSW
Port 3 Decoder
Logic
8
BUSPWR

Hub
USB USB USB Power
Transceiver Transceiver Transceiver Logic 10, 14, 18
OVRCUR1 - OVRCUR3
20 19 16 15 12 11
9, 13, 17
DP3 DM3 DP2 DM2 DP1 DM1 PWRON1 - PWRON3
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8.3 Feature Description

8.3.1 USB Power Management
The TUSB2036 supports both bus-powered and self-powered modes. External power-management devices,
such as the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports
and to detect an overcurrent condition from the downstream ports individually or ganged. Outputs from external
power devices provide overcurrent inputs to the TUSB2036 OVRCUR pins in case of an overcurrent condition,
the corresponding PWRON pins are disabled by the TUSB2036. In the ganged mode, all PWRON signals
transition simultaneously, and any OVRCUR input can be used. In the nonganged mode, the PWRON outputs
and OVRCUR inputs operate on a per-port basis.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types
of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port
basis). Individual-port management requires power-management devices for each individual downstream port,
but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all
the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2036 supports four modes of
power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2036 along with
the power-management devices needed to implement a fully USB compliant system.

8.3.2 Clock Generation

The TUSB2036 provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the MODE
pin controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry is
selected to drive the internal core of the chip. When MODE is high, the XTAL1 input is selected as the input
clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered
down while MODE is high. For 6-MHz operation, TUSB2036 requires a 6-MHz clock signal on XTAL1 pin (with
XTAL2 for a crystal) from which its internal APLL circuitry generates a 48-MHz internal clock to sample the data
from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the XTAL2
output, since the internal oscillator cell only supports the fundamental frequency. If low-power suspend and
resume are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of
using any device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on,
their use prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by
connecting its output to the XTAL1 pin and leaving the XTAL2 pin open, its TTL output level cannot exceed 3.6V.
If a 6-MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For crystal or resonator
implementations, the XTAL1 pin is the input and the XTAL2 pin is used as the feedback path. A sample crystal
tuning circuit is shown in Figure 5.
CL

XTAL1 XTAL2

C1 C2

NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd
are determined using a crystal from Fox Electronics – part number HC49U-6.00MHz 30\50\0±70\20, which means
±30 ppm at 25°C and ±50 ppm from 0°C to 70°C. The characteristics for the crystal include a load capacitance (CL) of
20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 Ω. In order to insure enough negative
resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 kΩ is recommended.

Figure 5. Crystal Tuning Circuit

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8.4 Device Functional Modes

8.4.1 2-3 Programmable Downstream Ports
The hub silicon can accurately reflect the system port configuration by the NP3 and NPINT1-0 pins. When NP3 is
low, the hub is configured as a 3-port hub; when it is high, the hub is configured as a 2-port hub. The NPINT1-0
pins tell the hub silicon how many ports have permanently attached devices, according to Table 1.

Table 1. System Port Configuration

HUB DESCRIPTOR
NPINT1-0 PORT AVAILABILITY DEVICE REMOVABLE FIELD
(7−0)
00 All ports are available through external USB connectors 00000000
01 Port 1 has a permanently attached device; ports 2 and 3 are externally available 00000010
10 Ports 1 and 2 have permanently attached devices; port 3 is externally available 00000110
NP3 high: 00000110
11 All ports have permanently attached devices
NP3 low: 00001110
HUB DESCRIPTOR WITH HUB
NPINT1-0 COMPOUND DEVICE OR NOT
CHARACTERISTICS FIELD BIT 2
00 Hub is not part of a compound device 0
01, 10, 11 Hub is part of a compound device 1

8.4.2 Vendor ID and Product ID With External Serial EEPROM

The EXTMEM (pin 26) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor
and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General
Purpose USB Hub. For this configuration, pin 6 functions as the GANGED input terminal and the EECLK (pin 5)
is unused. If custom VID and PID descriptors are desired, the EXTMEM must be tied low (EXTMEM = 0) and a
SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID, PID, and GANGED values. For
this configuration, pins 5 and 6 function as the EEPROM interface signals with pin 5 as EECLK and pin 6 as
EEDATA, respectively. A block diagram example of how to connect the external EEPROM if a custom product ID
and vendor ID are desired is shown in Figure 6.
TUSB2036 USB Hub
(3-Port Configuration)
30 5 V GND Bus or Local Power
6-MHz Clock
XTAL1/CLK48
Signal 3, 25
29 VCC Regulator
XTAL2
3.3 V 24
4 NP3
System 21
RESET OCPROT/
Power-On Reset
PWRSW 7, 28
26 GND
EXTMEM
12, 16, 20 4
1 DP1 - DP3
DP0
11, 15, 19 4
2
EEPROM DM1 - DM4 USB Data lines
DM0
6 3 6 10, 14, 18 and Power to
4
ORG D EEDATA OVRCUR1 - GND Downstream
Power
1 kΩ OVRCUR3 Ports
5 9, 13, 17 Switching 4
8 4 EECLK PWRON1 -
VCC Q Vbus
PWRON3
23
5 2 NPINT1
VSS C MODE
22
S NPINT0

1
Copyright © 2017, Texas Instruments Incorporated

Figure 6. TUSB2036 USB Hub With External EEPROM

12 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated

Product Folder Links: TUSB2036

 TUSB2036
www.ti.com SLLS372I – MARCH 2000 – REVISED MARCH 2017

8.5 Programming
8.5.1 Programming the EEPROM
An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the
EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 μA)
inside the TUSB2036. The internal pulldowns are disabled when the EEPROM interface is disabled
(EXTMEM = 1).
The EEPROM is programmed with the three 16-bit locations as shown in Table 2. Connecting pin 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16-bit words.
Table 2. EEPROM Memory Map
ADDRESS D15 D14 D13 D12–D8 D7–D0
00000 0 GANGED 00000 00000 00000000
00001 VID High-byte VID Low-byte
00010 PID High-byte PID Low-byte
XXXXXXXX

The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O
operations forming a single-wire bus. After system power-on reset, the TUSB2036 performs a one-time access
read operation from the EEPROM if the EXTMEM pin is pulled low and the chip select(s) of the EEPROM is
connected to the system power-on reset. Initially, the EEDATA pin is driven by the TUSB2036 to send a start bit
(1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read
instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data to
the output shift register. At this point, the hub stops driving the EEDATA pin and the EEPROM starts driving. A
dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most significant
bit (MSB) first.
The output data changes are triggered by the rising edge of the clock provided by the TUSB2036 on the EECLK
pin. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory location
by automatically incrementing the address internally. Any EEPROM used must have the automatic internal
address advance function. After reading the three words of data from the EEPROM, the TUSB2036 puts the
EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share the
EEPROM. The EEPROM read operation is summarized in Figure 7. For more details on EEPROM operation,
refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet.

Copyright © 2000–2017, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TUSB2036
 14
TUSB2036

Submit Documentation Feedback

SLLS372I – MARCH 2000 – REVISED MARCH 2017

3-Stated
With Internal
C Pulldown

Start Read OP Code(10) 6 Bit Address (000000) 48 Data Bits Don’t Care

D D15 D14 D0 XX

A5 Other A1 A0 Dummy MSB of The Other LSB of MSB of

Product Folder Links: TUSB2036

Address Bit First Word Data Bits Third Word Fourth Word
Bits

Hub Driving Data Line EEPROM Driving Data Line

Figure 7. EEPROM Read Operation Timing Diagram

www.ti.com

Copyright © 2000–2017, Texas Instruments Incorporated

 TUSB2036
www.ti.com SLLS372I – MARCH 2000 – REVISED MARCH 2017

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a
single personal computer.
Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that
provides both communication and power distribution. The power configurations are bus-powered and self-
powered modes. The maximum current that may be drawn from the USB 5-V line during power up is 100 mA.
For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable. A bus-
powered hub must always be connected downstream to a self-powered hub unless it is the only hub connected
to the PC and there are no high-powered functions connected downstream. In the self-powered mode, the hub is
connected to an external power supply and can supply up to 500 mA to each downstream port. High-powered
functions may draw a maximum of 500 mA from each downstream port and may only be connected downstream
to self-powered hubs. Per the USB specification, in the bus-powered mode, each downstream port can provide a
maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of
500 mA of current.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types
of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port
basis). Individual-port management requires power-management devices for each individual downstream port,
but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all
the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2036 supports four modes of
power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2036 along with
the power-management devices needed to implement a fully USB compliant system.
Note, even though no resistors are shown in the following applications, pullup, pulldown, and series resistors
must be used to properly implement this device.

Copyright © 2000–2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TUSB2036
TUSB2036
SLLS372I – MARCH 2000 – REVISED MARCH 2017 www.ti.com

9.2 Typical Application

A common application for the TUSB2036 is as a self-powered USB hub product. The product is powered by an
external 5-V DC Power adapter. In this application, using a USB cable TUSB2036’s upstream port is plugged into
a USB Host controller. The downstream ports of the TUSB2036 are exposed to users for connecting USB
cameras, keyboards, printers, and so forth.

Figure 8. Self-Powered USB Hub Product

9.2.1 Design Requirements

For this example, follow the design parameters listed in Table 3.

Table 3. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
VCC Supply 3.3 V
Downstream Ports 3
Power Management Individual- Port
Clock Source 6-MHz Crystal
External EEPROM No
Power Source Mode Self-Powered

16 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated

Product Folder Links: TUSB2036

 TUSB2036
www.ti.com SLLS372I – MARCH 2000 – REVISED MARCH 2017

9.2.2 Detailed Design Procedure

In a self-powered configuration, the TUSB2036 can be implemented for individual-port power management when
used with the TPS2044 because it is capable of supplying 500 mA of current to each downstream port and can
provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power is
removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered
hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient
suppressors reduce inrush current and voltage spikes on the data lines.
TUSB2036 Downstrea m
DP0PUR Ports
Upstream ¶
1.5 kΩ DP1 D+
Port
DM1 D-
D+ DP0 15 kΩ A C
D- DM0 GND
B D
SN75240† 15 kΩ
SN75240†
A C DP2 5V
B D
5V DM2
3.3 V LDO § 15 kΩ 100 mF‡
5V
4.7 mF 15 kΩ
3.3 V VCC D+
0.1 mF 4.7 mF
DP3 D-
GND GND
DM3
MODE 15 kΩ A C GND
B D
15 kΩ
SN75240† 5V

XTAL1/CLK48 BUSPWR 3.3 V 100 mF‡

6-MHz Clock EEDATA/GANGED TPS2044†

Signal
PWRON1 EN1
XTAL2 PWRON2 EN2
D+
PWRON3 EN3
D-
EN4
3.3 V EXTMEM
NP3 OUT1 GND
NPINT1 OUT2
NPINT0 OUT3 5V

System OUT4
RESET 100 mF‡
Power-On Reset
OVRCUR1 OC1 IN1
GND IN2
OVRCUR2 OC2
OVRCUR3 OC3 0.1 mF
OCPROT/PWRSW OC4

5-V Board Power

Supply

NOTES: † TPS2042 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044.
‡ 120 µF per hub is the minimum required per the USB specification. However, TI recommends a 100-µF, low ESR,
tantalum capacitor per port for immunity to voltage droop.
§ LDO is a 5-V-to-3.3-V voltage regulator. TPS76333 from Texas Instruments can be used.
¶ All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter
capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub
terminal and the series resistor, as per section 7.1.6 of the USB specification.

Copyright © 2017, Texas Instruments Incorporated

Figure 9. TUSB2036 Self-Powered Hub, Individual-Port Power-Management Application

Copyright © 2000–2017, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TUSB2036
TUSB2036
SLLS372I – MARCH 2000 – REVISED MARCH 2017 www.ti.com

9.2.3 Application Curve

Figure 10. Downstream Port 1

18 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated

Product Folder Links: TUSB2036

 TUSB2036
www.ti.com SLLS372I – MARCH 2000 – REVISED MARCH 2017

10 Power Supply Recommendations

10.1 TUSB2036 Power Supply

VCC should be implemented as a single power plane.
• The VCC pins of the TUSB2036 supply 3.3-V power rail to the I/O of the TUSB2036. This power rail can be
isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10-μF capacitor or 1-μF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB2036 power pins as possible with an optimal grouping of two of differing values per pin.

10.2 Downstream Port Power

• The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and up to 500
mA per port. Downstream port power switches can be controlled by the TUSB2036 signals. It is also possible
to leave the downstream port power always enabled.
• A large bulk low-ESR capacitor of 22 μF or larger is required on each downstream port’s VBUS to limit in-rush
current.
• The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1 μF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

11 Layout

11.1 Layout Guidelines

11.1.1 Placement
1. A 0.1 µF should be placed as close as possible on VCC power pin.
2. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.
3. If a crystal is used, it must be placed as close as possible to the TUSB2036’s XTAL1 and XTAL2 pins.
4. Place voltage regulators as far away as possible from the TUSB2036, the crystal, and the differential pairs.
5. 5. In general, the large bulk capacitors associated with the power rail should be placed as close as possible
to the voltage regulators.

11.1.2 Differential Pairs

1. Must be designed with a differential impedance of 90 Ω ±10%.
2. Route all differential pairs on the same layer adjacent to a solid ground plane.
3. Do not route differential pairs over any plane split.
4. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
5. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore
minimize the impact bends have on EMI.
6. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for USB
2.0 differential pair signals is eight inches. Longer trace lengths require very careful routing to assure proper
signal integrity.
7. Match the etch lengths of the differential pair traces. The USB 2.0 differential pairs should not exceed 50 mils
relative trace length difference.
8. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB2036 device.
9. Do not place power fuses across the differential pair traces.
Copyright © 2000–2017, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TUSB2036
TUSB2036
SLLS372I – MARCH 2000 – REVISED MARCH 2017 www.ti.com

Layout Guidelines (continued)

11.1.3 Ground
It is recommended that only one board ground plane be used in the design. This provides the best image plane
for signal traces running above the plane. The thermal pad of the TUSB2036 and any of the voltage regulators
should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port
connectors on a different plane for EMI and ESD purposes.

11.2 Layout Example

Figure 11. Downstream Ports

20 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated

Product Folder Links: TUSB2036

 TUSB2036
www.ti.com SLLS372I – MARCH 2000 – REVISED MARCH 2017

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised docum

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2000–2017, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TUSB2036
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TUSB2036VF ACTIVE LQFP VF 32 250 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 TUSB2036

& no Sb/Br)
TUSB2036VFG4 ACTIVE LQFP VF 32 250 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 TUSB2036
& no Sb/Br)
TUSB2036VFR ACTIVE LQFP VF 32 1000 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 TUSB2036
& no Sb/Br)
TUSB2036VFRG4 ACTIVE LQFP VF 32 1000 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 TUSB2036
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB2036VFR LQFP VF 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TUSB2036VFR LQFP VF 32 1000 336.6 336.6 31.8

Pack Materials-Page 2
 PACKAGE OUTLINE
VF0032A SCALE 1.700
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

7.2
B
6.8
NOTE 3 25
32
PIN 1 ID

1 24

7.2 9.2
TYP
6.8 8.8
NOTE 3

8
17

9 16
A
0.45
28X 0.8 32X
0.25
4X 5.6 0.2 C A B

C
1.6 MAX
SEATING PLANE

(0.13) SEE DETAIL A

TYP

0.25 (1.4)
GAGE PLANE

0.15
0 -7 0.1 C 0.05
0.75
0.45
DETAIL A
A 15

TYPICAL
4219769/A 04/2019
NOTES: PowerPAD is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Reference JEDEC registration MS-026.

www.ti.com
 EXAMPLE BOARD LAYOUT
VF0032A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM

32 25

32X (1.5)

1 24

32X (0.55)

SYMM 33
(8.4)

28X (0.8)

8 17
(R0.05) TYP

SEE DETAILS 9 16

(8.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

OPENING
EXPOSED METAL

EXPOSED METAL
METAL UNDER
SOLDER MASK SOLDER MASK
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4219769/A 04/2019
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
VF0032A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
32 25

32X (1.5)

1 24

32X (0.55)

SYMM 33
(8.4)

28X (0.8)

8 17
(R0.05) TYP

9 16
(8.4)

SOLDER PASTE EXAMPLE

SCALE:8X

4219769/A 04/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

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