Division of Science & Technology

Department of Information Sciences

Assignment#1

Pentium 4 and Core i5

Name: M.Faizan

Roll Number: Bsf23006565

Program: BSCS T

Session: Evening T

Section: B T

Semester: 3rd Semester

Course Instructor: Mam Perwasha Wazir

University of Education, Lahore

 Intel Core i5:
The Intel Core i5 (Raptor Lake) uses a hybrid architecture with Performance Cores (P-Cores) for high-
demand tasks and Efficiency Cores (E-Cores) for background tasks. It features Intel Thread Director for
optimizing workload distribution between cores. The processor supports DDR5 and PCIe 5.0 for faster
memory and connectivity. It includes a large L3 cache shared across cores for improved performance. The
CPU connects to the LGA 1700 socket with 1700 contact points for stable communication with the
motherboard.

Pins:
The Intel Core i5 (Raptor Lake) utilizes the LGA
1700 socket, which has 1,700 contact points or pins
on the motherboard. These pins facilitate the
electrical and data connections between the
processor and the motherboard. The socket design
ensures compatibility with specific Intel CPUs and
enhances signal integrity and power delivery. It is a
key feature for stability and performance in
computing systems. The LGA 1700 socket supports
both Raptor Lake and Alder Lake processors,
offering improved efficiency and performance
compared to previous generations.
 Pinout Layout for Intel Core i5 in LGA 1700
Pin A1-A5:  D5: PROCHOT#  H2: DMI_RX1 (DMI
 A1: VSS (Ground) (Processor Hot, thermal Receive Lane 1)
 A2: VCC (Core Voltage throttling)  H3: PCIe_TX2 (PCIe Data
Supply) Pin E1-E5: Transmit Lane 2)
 A3: PCIe_RX0 (PCIe Data  E1: VCCSA (System  H4: VCC (Core Voltage
Receive Lane 0) Agent Voltage Supply) Supply)
 A4: DMI_TX0 (DMI  E2: SVIDALERT# (Serial  H5: VID1 (Voltage
Transmit Lane 0) Voltage Identification Identification Bit 1)
 A5: RESET (Reset Signal) Alert) Pin J1-J5:
Pin B1-B5:  E3: VSS (Ground)  J1: VCCSA (System
 B1: BCLK (Base Clock)  E4: DMI_RX0 (DMI Agent Voltage Supply)
 B2: VCCSA (System Receive Lane 0)  J2: VSS (Ground)
Agent Power Supply)  E5: VCC (Core Voltage  J3: PCIe_RX2 (PCIe Data
 B3: PCIe_CLK (PCIe Supply) Receive Lane 2)
Clock) Pin F1-F5:  J4: BCLK (Base Clock)
 B4: INTR (Interrupt  F1: VSS (Ground)  J5: VCCIO (I/O Voltage
Request)  F2: DMI_TX1 (DMI Supply)
 B5: PWRGOOD (Power Transmit Lane 1) Pin K1-K5:
Good Signal)  F3: PCIe_TX1 (PCIe Data  K1: VCCSA (System
Pin C1-C5: Transmit Lane 1) Agent Voltage Supply)
 C1: VCCIO (I/O Voltage  F4: VCC (Core Voltage  K2: VSS (Ground)
Supply) Supply)  K3: DMI_TX2 (DMI
 C2: VSS (Ground)  F5: SVIDCLK (Serial Transmit Lane 2)
 C3: PCIe_TX0 (PCIe Data Voltage Identification  K4: SVIDDAT (Serial
Transmit Lane 0) Clock) Voltage Identification
 C4: SMI# (System Pin G1-G5: Data)
Management Interrupt)  G1: SMI# (System  K5: VCCPLL (PLL
 C5: VID0 (Voltage Management Interrupt) Voltage Supply)
Identification Bit 0)  G2: PCIe_RX1 (PCIe Pin L1-L5:
Pin D1-D5: Data Receive Lane 1)  L1: VCC (Core Voltage
 D1: THERMTRIP#  G3: VSS (Ground) Supply)
(Thermal Trip Indicator)  G4: VCCIO (I/O Voltage  L2: PCIe_RX3 (PCIe Data
 D2: VCCPLL (PLL Supply) Receive Lane 3)
Voltage Supply)  G5: THERMDA (Thermal  L3: DMI_RX2 (DMI
 D3: VSS (Ground) Diode Anode) Receive Lane 2)
 D4: ICHRESET (Chipset Pin H1-H5:  L4: VSS (Ground)
Reset)  H1: VSS (Ground)  L5: VCCIO (I/O Voltage
Supply)
Types of pins:
1. Power and Ground Pins
 VCC (Core Voltage Supply): Supplies power to the processor’s core. Multiple VCC pins are spread
across the grid to maintain stable power.
 VSS (Ground): Ground pins are used to return electrical current. Multiple VSS pins are distributed
throughout the socket to provide stability and proper grounding.
2. Data Pins (DMI/PCIe)
 PCIe Data Pins: Handle PCI Express communication between the processor and peripherals (such as
graphics cards, SSDs, etc.).
 DMI (Direct Media Interface) Pins: Facilitate data transfer between the CPU and the chipset, managing
communication with I/O devices.
3. Memory Interface Pins
 Memory Data Pins: Responsible for transferring data between the CPU and system memory (typically
DDR4 or DDR5 for LGA 1700).
 Memory Address Pins: These pins send memory addresses to access RAM.
 Memory Control Signals: Control memory read/write operations and refresh cycles, ensuring smooth
data transactions.
4. Clock and Timing Pins
 BCLK (Base Clock): Synchronizes the processor's internal operations with external system components.
 RESET: Used to reset the CPU and initialize the system during boot or restarts.
 PWRGOOD: Indicates that the power supply to the processor is stable and within the required
operational range.
5. Voltage Regulation Pins
 VCCIO: Supplies voltage to the I/O interfaces for stable data transfer.
 VCCSA: Powers the system agent, which manages the integrated memory controller and I/O functions.
 VID (Voltage Identification) Pins: Communicate with the motherboard’s voltage regulator to
dynamically adjust the processor’s voltage as needed.
6. Power Management Pins
 SVID (Serial Voltage Identification): Allows the processor to communicate with the voltage regulator
for dynamic power adjustments.
 STPCLK# (Stop Clock): Stops the processor clock during low-power states to conserve energy.
 SLEEP: Signals the processor to enter a low-power sleep state.
 PROCHOT#: Activates thermal throttling or initiates shutdown to prevent overheating.
7. Interrupt Pins
 INTR (Interrupt Request): A general interrupt request pin used for external interrupt handling.
 NMI (Non-Maskable Interrupt): A higher-priority interrupt that cannot be disabled, used for critical
system errors.
8. PCI Express and I/O Control Pins
 PCIe_CLK, PCIe_RST: Provide clock and reset signals for PCIe lanes.
 PCIe_RX/TX: Manage data transmission (receive and transmit) for PCIe lanes, connecting to expansion
devices like GPUs and storage drives.
 I/O Pins: Handle general input/output operations with peripherals (USB, SATA, etc.).
9. Thermal Management Pins
 THERMTRIP#: Monitors thermal conditions and initiates shutdown or throttling when temperatures are
too high.
 VCC_TT (Thermal Throttle Voltage): Regulates voltage for thermal throttling mechanisms, protecting
the processor from overheating.
10. Miscellaneous Pins
  NC (No Connect): Pins that are not connected in this generation but reserved for future use or features.
 JTAG Pins: Debugging and testing pins, primarily used by engineers for diagnostics and
troubleshooting.

LGA 1700 Socket and Pin Configuration:

The Intel Core i5 Raptor Lake processors use the
LGA 1700 socket, which is a Land Grid Array
socket. Unlike older CPUs that had pins on the
processor itself, the LGA design places the 1700
pins on the motherboard socket, with flat contacts
on the CPU. This configuration improves both
durability and signal integrity. With 1700 contact
points, the LGA 1700 socket offers greater
connectivity for power and data, making it well-
suited for modern high-performance CPUs like the
Core i5.

-----------------------------------------------

Pentium 4
The Pentium 4 architecture, codenamed "NetBurst,"
was introduced by Intel in 2000. It featured a long
instruction pipeline (up to 31 stages) aimed at
achieving higher clock speeds, typically between
1.4 GHz and 3.8 GHz. The architecture supported
Hyper-Threading, allowing better multitasking by
simulating two processors. It also introduced the
SSE2 instruction set for improved multimedia
performance. However, despite the high clock
speeds, the NetBurst architecture suffered from heat
issues and inefficiency compared to its successors
like the Core series.
The Pentium 4 processor architecture includes several key components that contribute to its functionality. The
Bus Interface Unit (BIU) manages communication with the system bus, caches, and L1 data and code caches.
The Instruction Decoder translates instructions into micro-operations (μ-ops), with simple instructions requiring
one μ-op and complex ones handled by the Microcode ROM. After decoding, μ-ops are stored in the Trace
Cache, which can hold up to 12K μ-ops, allowing faster execution. Complex instructions are routed through the
Microcode ROM, which generates the necessary μ-ops for execution. The processor's Branch Prediction unit
uses speculative execution to anticipate future instructions, reducing the wait time during branching conditions.
This design improves performance and instruction throughput.

Pins:
The Intel Pentium 4 processor used either Socket 423 or Socket 478, and these sockets had different types of
pins that played various roles in connecting the CPU to the motherboard. Here's an overview of the types of
pins found in these sockets:
1. Power Supply Pins: These pins provide the necessary power (Vcc) to the CPU. Pentium 4, especially with
its high clock speeds, required efficient power management, and these pins were responsible for delivering the
required voltage levels.

2. Ground Pins (GND): These pins are responsible for grounding the CPU, helping to stabilize the electrical
signals and prevent noise or interference during the processor’s operation.

3. Data Pins: These pins facilitate data transfer between the processor and the system memory (RAM) or other
peripherals. They serve as the main communication route for input/output operations.

4. Address Pins: These pins are used by the CPU to communicate with the system memory, indicating the
location in memory where data should be read from or written to.

5. Control Pins: Control signals, such as interrupts, reset, and clock signals, are sent through these pins. They
are critical in managing the CPU's operations and synchronizing with other system components.

6. Cache and Bus Interface Pins: These pins communicate with the system cache (L2) and other buses,
ensuring data is transferred efficiently between the processor and the system.

In the Socket 478 the increased number of pins (478 compared to 423 in the older socket) allowed for improved
power distribution and data handling, especially necessary for higher-speed operations. These pins were
typically arranged in a grid layout to maximize connection efficiency and reliability.

Pinout Layout for Intel Pentium 4 in Socket 478

 Pin A1-A5:
o A1: VSS (Ground)
o A2: VCC (Core Voltage Supply)
o A3: RESET# (System Reset Signal)
o A4: D63 (Data Bit 63)
o A5: GND (Ground)
 Pin B1-B5:
o B1: BCLK (Bus Clock Input)
o B2: VSS (Ground)
o B3: DMI_REQ# (Direct Media Interface Request Line)
o B4: VCC (Core Voltage Supply)
o B5: D62 (Data Bit 62)
 Pin C1-C5:
o C1: DMI_ACK# (Direct Media Interface Acknowledge Line)
o C2: VCC (Core Voltage Supply)
o C3: VSS (Ground)
o C4: A0 (Address Line 0)
o C5: GND (Ground)
 Pin D1-D5:
o D1: D61 (Data Bit 61)
o D2: DMI_REQ# (Direct Media Interface Request Line)
 o D3: VSS (Ground)
o D4: D60 (Data Bit 60)
o D5: VCC (Core Voltage Supply)
 Pin E1-E5:
o E1: VCC (Core Voltage Supply)
o E2: GND (Ground)
o E3: D59 (Data Bit 59)
o E4: A31 (Address Line 31)
o E5: VSS (Ground)
 Pin F1-F5:
o F1: D58 (Data Bit 58)
o F2: GND (Ground)
o F3: A30 (Address Line 30)
o F4: VCC (Core Voltage Supply)
o F5: D57 (Data Bit 57)
 Pin G1-G5:
o G1: VCC (Core Voltage Supply)
o G2: A29 (Address Line 29)
o G3: D56 (Data Bit 56)
o G4: VSS (Ground)
o G5: A28 (Address Line 28)
 Pin H1-H5:
o H1: VCC (Core Voltage Supply)
o H2: GND (Ground)
o H3: D55 (Data Bit 55)
o H4: DMI_ACK# (Direct Media Interface Acknowledge Line)
o H5: VCC (Core Voltage Supply)
 Pin J1-J5:
o J1: D54 (Data Bit 54)
o J2: GND (Ground)
o J3: DMI_REQ# (Direct Media Interface Request Line)
o J4: VSS (Ground)
o J5: D53 (Data Bit 53)
 Pin K1-K5:
o K1: VCC (Core Voltage Supply)
o K2: D52 (Data Bit 52)
o K3: A1 (Address Line 1)
o K4: DMI_ACK# (Direct Media Interface Acknowledge Line)
o K5: GND (Ground)
 Pin L1-L5:
o L1: D51 (Data Bit 51)
o L2: VCC (Core Voltage Supply)
o L3: GND (Ground)
o L4: A2 (Address Line 2)
o L5: D50 (Data Bit 50)