Lesson 004

Field Effect Transistor

The field-effect transistor (FET) is a semiconductor device which depends for its operation
on the control of current by an electric field. Therefore FET is a voltage control device.
The two types of field effect transistor are:

(i) The junction field-effect transistor (JUGFET or JFET or simply FET) and

(ii) Insulated-gate field-effect transistor (IGFET). It is also called Metal-oxide-

semiconductor (MOS) transistor or MOST or MOSFET.
The JFET can be in two forms, P-channel and N-channel, depending on the type of
semiconductor forming the basis of the transistor. JFET operates in depletion mode.
Like BJT, all FETs are three terminals devices, the terminals are: the Source, the Gate and the
Drain which correspond to Emitter, Base and Collector in BJT.
Fig. 4.10 and Fig. 4.11 show the basic structures of an N-channel JFET and P-channel JFET
respectively. While Fig. 4.12 and Fig. 4.13 show their symbols in that order.
-G +G

S N-Channel D S P-Channel D

Fig. 4.10 Fig. 4.11 +G

-G

D
D

G
G

S Fig. 4.13
S

The field-effect transistor differs from the BJT in the following important characteristics:
(i) FET is a unipolar device

(ii) It exhibits high input impedance

(iii) It is less noisy than BJT

(iv) It is simpler to fabricate and occupies less space in integrated form.

(v) It exhibits no offset voltage at zero drain current.

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 The Principle of Operation of JFET
N-channel JFET shall be considered for discussing JFET operation.
(i) When neither any bias is applied to the gate (i.e. VGS = 0) nor any voltage to the drain with
respect to source (i.e. VDS = 0), the depletion region around the P-N junctions are of equal
thickness and symmetrical (Fig, 4.14).
(ii)When positive voltage is applied to the drain terminal D with respect to source terminals
without connecting gate terminal G to supply (Fig. 4.15), electrons flows from terminal D to
S. Due to the flow of current, there is a uniform voltage drop across the channel resistance as
we move from terminal D to terminal S. This voltage drop reverse biases the diode. The gate
is more negative with respect to those points in the channel which are near to D than to S.
Hence depletion layers penetrate more deeply into the channel at points lying closer to D than
S (Fig. 4.15). The size of the depletion layers formed determines the width of the channel and
hence the magnitude of current ID flowing through the channel.
A(iii) When the gate is biased negative with respect to the source, while the drain is applied
with positive bias with respect to the source (Fig. 4.16), the P-N junction are reversed biased
and depletion regions are formed. P-regions are heavily doped compared to the N- channel,
so the depletion regions penetrate deeply into the channel and this result in narrow channel
and the resistance is increased and drain current ID is reduced. If the negative voltage at the
gate is further increased, depletion layers meet at the center and the drain current ID is cut-off
completely (Fig. 4.17). On the other hand, if the negative bias to the gate is reduced, the
width of the depletion layers gets reduced causing decrease in resistance and therefore
increase in drain current ID.
D +VDD D +VDD
D D +VDD
N N
N N
G
G P P P P G
G P P P P
VGG
N N VGG
N N
Fig. 4.15 S
Fig. 4.14 S
S S
Fig. 4.16
Fig. 4.17

The two distinct modes in which MOSFET operations are: Depletion mode and Enhancement
mode. Each mode is further subdivided into N-channel and P-channel. Fig. 4.18a and
Fig. 4.18b shows the N-channel Enhancement-mode MOSFET and N-channel

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depletion-mode MOSFET respectively. While Fig. 4.19a and Fig. 4.19b show their symbols
in that order. S -G D
S +G D
oxide
oxide
n-Channel
n-Channel
P – type substrate
P – type substrate
Fig. 4.18b Substrate
Fig. 4.18a Substrate
D
D

G
G

Fig. 4.19b
Fig. 4.19a
S
S
Exercise 5
Draw the diagram and symbols a P-channel Enhancement-mode MOSFET and P-channel
depletion-mode MOSFET hence explain their working principles.

Important Terms
The important terms are:
(i) Shorted-gate drain current (IDSS)
(ii) Pinch off voltage (VP)
(iii) Gate-Source cut-off voltage (VGS(OFF))
These terms can be explained with the aid of Fig. 4.20 and Fig. 4.21.
ID(mA)
Break-down
Region
D DSS
G VDD
VDS

S Active
Region

Fig. 4.20 VDS(max)

VP VDS
Fig. 4.21
Fih.4.20 shows a JFET circuit with VGS = 0 (i.e. source short circuited to gate). This is
normally called short-gate condition. Fig. 4.21 shows the graph between ID and VDS for the
shorted gate condition obtained from Fig. 4.20. As VDS increase, ID first increase rapidly then
become constant at pinch off voltage VP. At this point, ID reaches the maximum value called

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IDSS. When VDS further increase, IDSS is constant upto the point called VDS(max), beyond
VDS(max) the transistor breakdown.
Since IDSS is measured under shorted gate condition, it is the maximum drain current that can
be obtained with normal operation of JFET. The region between VP and VDS(max) is called
constant current region or active region.

Definitions:
(i) Shorted-gate drain current IDSS is the drain current with source short-circuited to gate (i.e.
VGS = 0) and drain voltage (VDS ) equal to pinch-off voltage. It is sometime called zero bias
current.
(ii) Pinch-off voltage VP is the minimum drain-source voltage at which the drain current
essentially becomes constant.
(iii) Gate-Source cut-off voltage VGS(off) is the gate-source voltage when the channel is
completely cut-off and the drain current becomes zero.

Output Characteristic of JFET

It is a family of curves that shows the relationship between Drain-Source voltage VDS and
Drain current ID of a JFET for different values of the gate-source voltages VGS.
ID(mA)

IDSS VGS = 0 V

VGS = -1

VGS = -2

VP VDS (V)
Fig. 4.22

Fig. 4.22 shows the output characteristic curves of a typical N-channel JFET circuit. It is
obtained by first keeping VGS = 0 and then plot the curve of VDS versus ID.. Then repeat the
process for VGS = -1 V and VGS = -2 V.
It is observed that each of the curves in Fig. 4.22 is a part of parabola, a complex
mathematical analysis of the parabola yielded the following:
2
 VGS 
I D  I DSS 1   ..........................................................................................4.10
 VP 
Where:
ID is the drain current at given VGS

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 IDSS is the shorted-gate grain current
VGS is the gate-source voltage.

JFET BIASING
For proper operation of N-channel JFET, gate must be negative with respect to source. This
can be achieved either by inserting a battery in the gate circuit or by a circuit known as
biasing circuit. The three types of biasing are: fixed bias, self bias and voltage divider bias.

Fixed Bias Circuit

Fig. 4.23 shows a fixed biasing circuit for N-channel JFET. The fixed bias is obtained by
using a battery VGG. This battery ensures that the gate is always negative with respect to
source and no current flows through resistor RG and gates terminal i.e. IG = 0. The battery
provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the
battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C1 to
develop across RG. The voltage drop across RG is equal to IGRG zero volt.
VDD

RD
C2

C1
VDS
VOI
VGS
VS RG2
VGG

Fig. 4.23

N.B
For dc analysis of JFET amplifier, the general relationship is given as IG = 0; ID = IS and
2
 V 
I D  I DSS 1  GS 
 VP 
Applying KVL to the output loop gives:
VDS = VDD - IDRD.
Then the gate-source voltage VGS is given as VGS = -VG – VS = -VG - 0 = -VGS
Since VGS is fixed value of dc supply and magnitude of gate-source voltage VGS is also fixed,
hence this circuit is named fixed bias circuit. Since this circuit uses two batteries VDD and
VGG , it is also known as two battery bias circuit.

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 Self Bias
Self bias for an N-channel JFET is as shown in Fig.4.24. The circuit eliminated the
requirement of two dc supplies i.e. only drain supply is used and no gate supply is connected.
In this circuit, resistor RS, known as bias resistor is connected in the source terminal. The dc
component of drain current ID flowing through RS makes a voltage drop across resistor RS.
VDD

RD
C2

C1
VDS
VO
VGS
VS
RG2
RS

Fig. 4.24
The voltage drop across RS reduces the gate-source reverse voltage required for JFET
operation. The resistor RS, the feedback resistor prevents any variation in JFET drain current.
Since no current flows through the reverse-biased gate-source, the gate current IG = 0,
therefore VG =IGRG =0 V; VS = IGRS; VGS = VG –VS = 0 – IDRS = -IDRS
Therefore the drop across RS provide the biasing voltage VGS and no external source is
required for biasing and for this is reason it is called self biasing circuit.
Applying KVL to the output loop,
VDS = VDD – ID(RD + RS).
Self bias of a JFET stabilizes its quiescent operating points against any changes in its
parameter like trans-conductance. If the give JFET is replaced by another JFET having
double conductance the drain current will also try to be double but since any increase in
voltage drop across RS, therefore gate-source voltage, VGS becomes more negative and thus
increase in drain current is reduced.

Potential (Voltage) Divider Bias

Fig. 4.25 shows a potential divider bias circuit. RG1 and RG2 form a potential divider across
drain supply VDD. The gate is reverse biased so that IG = 0 and the gate voltage is

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 VDD
ID
RG1 RD

C1 C2
VDS
VO
VGS
VS
RG2 CS
RS

Fig. 4.25
R G2
VG   VDD
R G1  R G 2
Applying KVL to the input loop,
VG - VS = 0
VGS = VG - VS = VG – ISRS = VG – IDRS (since ID ≈ IS)
The circuit is designed such that IDRS is larger than VG so that VGS is negative. This provides
the correct bias voltage.
V  VGS
ID  G
RS
VDS = VDD – ID(RD + RS).

Exercise 6
Write extensively about JFET and MOSFET.

Equivalent Circuit of a JFET

Like the junction transistor, the JFET can be represented by circuit which is equivalent of its
response to small signals causing it to operate over the linear part of its characteristics. The
JFET equivalent circuit shown in Fig.4.26 is similar to that for the junction transistor except
that the input impedance is so high that it can be considered infinite, i.e. equivalent to an open
circuit. G D

Vbe gmVgs rd Vds

Fig.2.26

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 Universal Bias Common Source Small Signal Analysis
VDD
ID
RG1 RD Ri Ro

C2 G D Io
C1
VDS Id
VO
VGS Vgs g V rd
VS R1//R2 Vds RD V o
Vs m gs
RG2 CS
RS
S

Fig. 4.27 Fig.4.28

Fig.4.28 shows the small signal equivalent circuit of Fig. 4.27,

(i)
Vo   g m Vgs ( rd // R D )

but
Vs  Vgs

Vo  g mV gs (rd // R D )
 Av     g m (rd // R D )..............................................4.11
V gs V gs

(ii) from
V Io R o  Io   R o  Ro
Av  o       Ai
Vs I s R i  Is   R i  Ri
R R
 
 Ai  Av i   g m rd // R D  i .......... .......... .......... .......... .......... .......... .......... ........ 4.22
Ro Ro
2 2
Vo I o I o Ro I o I o2 Ro  I o  Ro Ro  Ri  Ro 2 Ri .....4.23
Ap 
Vi I i
   
I s Ri I o I 2 R  I i  Ri
2
 Ai   g m rd // RD
Ri 
 
Ro  Ri
 2 r
 g m d // RD
Ro
 
i i

Universal Bias Common drain Small Signal Analysis

Fig.4.30 shows the small signal equivalent circuit of Fig. 4.29, Fig.4.31 is the simplify form
of Fig. 4.29. G D
VDD

gmVgs rd
RG1 Vgs
C2 R1//R2 S
C1 VS
VDS
VGS Rs VO
VS
RG2
RS VO
8Fig.4.30
Fig. 4.29
 Ro

G S
Vgs

R1//R2 gmVgs rd RS Vo
Vs

Fig.4.31
From Fig. 4.31,
Vo  g mV gs ( rd // R S )......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .... 4.24

The KVL eqn. from input to output is given as:

VS  Vgs  Vo  Vgs  g m Vgs ( rd // R S )

Therefore, the gate-to-source voltage is

VS
V gs  .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..4.25
1  g mV gs ( rd // R S )
Subt. Eqn. 2.25 into 2.24
Vo g mV gs (rd // RS )
Av   .......................................................................................4.26
VS 1  g mV gs (rd // RS )

To determine the output resistance of Fig. 4.31, set all independent small-signals source equal
to zero, apply a test voltage to the output terminals and measure the test current.
Ro

G S Ix
Vgs

R1//R2 gmVgs rd RS Vx

Fig.4.32
The KCL eqn. from input to output is given as:
V V
I x  g m Vgs  x  x
R S rd
Since Vgs = -Vx,
 1 1
 I x  Vx  g m   
 R S rd 
Or

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Ix 1 1 1
  gm  
Vx Ro R S rd
1
 Ro  // R S // rd .......... .......... .......... .......... .......... .......... .......... .......... ......... 4.26
gm
Exercise 7
Determine the small signal voltage gain of a multistage circuit shown in Fig. 4.33. Given that
gm1 = gm2 =0.63 mA/V.

+5 V

383 kΩ 16.1 kΩ

C1 C2 C2

VS 135 kΩ
39 kΩ CS 8 kΩ 4 kΩ VO

Fig. 4.34

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