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Lab 8

This lab, "Flip-Flops," focuses on examining the behavior and applications of different flip-flops. You start by configuring an SR latch and then set up a D flip-flop (7474) to observe how its synchronous and asynchronous inputs control its output. Next, you’ll work with a JK flip-flop (7476), testing its asynchronous clear and preset functions and exploring its toggle mode.

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9 views

Lab 8

This lab, "Flip-Flops," focuses on examining the behavior and applications of different flip-flops. You start by configuring an SR latch and then set up a D flip-flop (7474) to observe how its synchronous and asynchronous inputs control its output. Next, you’ll work with a JK flip-flop (7476), testing its asynchronous clear and preset functions and exploring its toggle mode.

Uploaded by

Xavos
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 8 Flip-Flops

ICs: 7474 (DFF), 7476(JKFF), 7486 (XOR), 7402(2-input NOR), 7400(2-input NAND)

The objective of this lab is to investigate the behavior of various latches and flip-flops.

T Flip-flop

T flip-flop is a complementing flip-flop.


I. SR Latch
8. Turn off the power and disconnect the circuit.
II. D Flip-Flop

Procedure:
1. Insert the 7474 into the breadboard.
2. Refer to the following figure and wire the 7474. Wire the asynchronous inputs CLR and PR to two
switches. Wire the synchronous inputs D to a switch and the CLK input to a single-pulse clock
(see Instructor if clock is not hooked up or working).
3. Operate the asynchronous inputs CLR and PR according to the inputs in Table 1, and record the
results in the table. Also write the name of the condition in the last column of the table.
4. Disable the asynchronous inputs (PR and CLR to 1).
5. Operate the synchronous inputs D and CLK of the 7474 according to the inputs in Table 2.
Observe and record the results in Table2.
Table 1

Table 2

Questions (answer on your report)


1) Draw a logic symbol for a D flip-flop. Label the inputs D, CLK, PR, and CLR and the outputs Q
and Q.
2) What are the synchronous inputs of the D flip-flop?
3) What are the asynchronous inputs of the D flip-flop?
4) Which output column in Table 2 is exactly the same as the input D column?
5) A logical _______ at PR will preset the Q output of the 7474 D flip-flop to a logical
___________, assuming that CLR is a 1.
6) The synchronous inputs of the D flip-flop only operate when the PR and CLR inputs are
_________ (disabled, enabled) with a logical __________.
7) The 7474 D flip-flop is a _________________ (negative-, positive-) edge triggered flip-flop.
8) Write the state/characteristic equation of D flip flop, i.e., Q(t+1) = ?
III. JK Flip-Flop: Procedure:
1. Insert the 7476 into the breadboard.
2. Wire the asynchronous inputs PR and CLR to two switches.
Wire the synchronous inputs J and K to switches and the CLK
input to a single-pulse clock.
3. Operate the asynchronous inputs PR and CLR and record the
results in Table 3. Also, write the condition in the last
column.
4. Operate the synchronous inputs J, K, and CLK of the 7476
according to Table 4. Observe and record results.

Table 4

Table 3

Questions (answer on your report)

1) Draw a logic symbol for a J-K flip-flop. Label the inputs J, K, CLK, PR, and CLR and the outputs
Q and Q’.
2) What are the synchronous inputs of the J-K flip-flop?
3) What are the asynchronous inputs of the J-K flip-flop?
4) The truth table for the asynchronous inputs is the same as for what other flip-flop we have used?
5) The inverter bubbles at the PR and CLR inputs of the 7476 mean that a logical ___________ will
disable these asynchronous inputs and enable the synchronous inputs.
6) What is the meaning of the inverter bubble on the clock input of the 7476?
7) What is meant by the “toggle” position of the flip-flop(i.e., what happens to the LED’s in toggle
mode)? Also, what must PR, CLR, J, and K be in order for the FF to be in toggle mode?
8) Write the state/characteristic equation of JK flip flop, i.e., Q(t+1) = ?
9) What type of triggering does the 7476 use (positive or negative edge)?

IV. T-Flip-Flop.
T flip-flop is a complementing flip-flop ad can be obtained from JK flip-flop or D flip-flop as below.
Construct a T flip-flop and record its behavior in the following table.

Clock T Q(t) Q(t+1) Name of


Condition
0 0
0 1
1 0
1 1

Write the state/characteristic equation of T flip flop, i.e., Q(t+1) = ?

V.
Refer to the data sheet for a 7474, edge-triggered D flip-flop. Construct the following
circuit in MultiSI. Select the actual 7474 IC from the digital menu rather than a D flip-flop symbol.
Connect VCC and Ground to the appropriate pins on the IC. Connect a toggle switch to the asynchronous
CLEAR line and set the switch to a logic ‘1’. Connect VCC to the asynchronous PRESET line. Connect
the Function Generator to the CLOCK input. To get a 0 – 5 V square wave, select a 50% duty cycle, 1
kHz square wave with an amplitude of 2.5V and an offset of 2.5V. (Connect the + output to the clock
input and the common input to ground. The – output should not be connected). Monitor the CLOCK input
and the ‘Q’ output using a Logic Analyzer. You can find Function Generator and Logic Analyzer under
the menu of Instruments)

CLK
a) Turn the simulator on and then turn off the simulator after a number of clock signals has occurred.
Sketch an output waveform as shown on the logic analyzer. Note that the clock at the bottom of
the logic analyzer is not the input clock here. The input clock has a 1kHz frequency. You need to
read the time of each cycle to get the frequency.

1ms 2ms 3ms 4ms

b) Measure and record the frequency of the ‘Q’ waveform.


Frequency = _______________

c) What is the function of this simple D flip-flop circuit? _________________ Why?

d) Turn the simulator back on. Toggle the asynchronous CLEAR input to a ‘0’. What
happens to the output?
________________________________________________

Review Questions: Answer the following questions (next page) after the lab is completed.
V

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