CS 330 Hardware and Systems Fundamentals

Fall 2024 – Lab # 3: Extending Adder to perform

multiplication and designing an ALU

Due Date: Thursday, 10th October 2024 @11:59PM.

INTRODUCTION

Digital circuits form the backbone of modern computing systems, enabling the manipulation
and processing of digital information through a series of logical and arithmetic operations. At
the heart of these circuits lies the Arithmetic Logic Unit (ALU), a critical component
responsible for executing fundamental arithmetic computations and logical comparisons
essential for data processing tasks. In this laboratory session, we will extend our adders to
perform multiplication and delve into the intricacies of designing an ALU using multiplexers,
comparators, and full adders.

The objective of this laboratory session is to provide students with hands-on experience in
designing, implementing, and testing key components of an ALU, thereby deepening their
understanding of digital logic and arithmetic operations. Through a series of guided exercises
and practical tasks, students will explore the functionalities of multiplexers, comparators, and
full adders within the context of ALU design, focusing on their roles in data routing,
comparison and arithmetic computation.

Throughout the lab session, students will be tasked with conceptualizing and constructing a
functional ALU circuit that can perform basic arithmetic operations such as addition and
subtraction, multiplication and division as well as logical comparisons between input values.
By integrating multiplexers to control data flow, comparators to facilitate comparison
operations, and full adders to execute arithmetic computations, students will gain insight into
the interplay between various digital circuit components and their collective contribution to
ALU functionality.

Furthermore, this laboratory session emphasizes collaborative teamwork, problem-solving,

and critical thinking skills as students work together to address challenges, debug issues, and
optimize the performance of their ALU designs. By fostering a hands-on learning

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environment, this session aims to empower students with practical skills and knowledge that
are applicable across various domains of digital circuit design and computer architecture.

In summary, this laboratory session serves as a foundational exploration into the principles
and practices of digital circuit design, offering students a tangible opportunity to engage with
the complexities of ALU architecture and gain valuable insights into the inner workings of
digital computing systems. Through experimentation, collaboration, and reflection, students
will emerge with a deeper appreciation for the intricacies of digital logic and a solid
foundation upon which to build further expertise in the field of computer engineering and
electronics.

Lab Objectives:

1. Understanding Basic Arithmetic and Logic Operations: Gain a comprehensive

understanding of fundamental arithmetic operations (addition, subtraction) and logical
operations (comparison) within the context of digital circuitry.
2. Multiplexer and Comparator Proficiency: Develop proficiency in designing and
implementing multiplexers and comparators to efficiently route and compare data
signals within the ALU architecture.
3. Full Adder Integration and Arithmetic Logic Unit Functionality: Learn to
integrate full adders into the ALU design to perform addition and subtraction
operations accurately while managing carry propagation and handling various input
scenarios.
4. Team Collaboration and Problem-Solving Skills: Enhance teamwork and problem-
solving skills through collaborative design, troubleshooting, and testing phases,
fostering effective communication and shared responsibility for achieving project
objectives.

Part 1: Extending your Adder to Perform Multiplication

An adder can be extended to perform multiplication. In this part, we will extend the adder to
perform the multiplication of 2-bit numbers. Here, we will need some AND gates in addition
to our full-bit adder.
The binary multiplication rules are as follows:
 1×1=1
 1×0=0
 0×1=0
 0×0=0

Let us consider this scenario of a 2-bit multiplication:

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Here, you will realize that we need four AND gates and TWO adders to perform this
multiplication. The result of multiplying 2-bit inputs results in a maximum of 4-bit output
result.
Notice that at each point in the addition process, at most 2 bits are added. What does this tell
us? We can use half adders to design our 2-bit multiplier. Can you think of how full bit
adders can be used to accomplish this same design?

Half-Adder Truth Table

A (Input 1) B (Input 2) Sum (S) Carry (C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Explanation of Outputs:

 Sum (S): This output is the result of the XOR operation on the two inputs A and B. It
is high (1) when either (but not both) of the inputs is high.
 Carry (C): This output is the result of the AND operation on the two inputs A and B.
It is high (1) only when both inputs are high (1).

Logical Expressions:

 Sum: S=A⊕B (XOR)

 Carry: C=A⋅B (AND)

The half-adder is used in building more complex arithmetic circuits, such as full adders and
binary adders.

a. A 2-bit multiplier with two half bit adders and four AND gates shown in the image

below:

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 Figure 1. 2-bit multiplier with half adders

Activity 1:
 Implement the half adder

 Design a 2-bit multiplier as shown in the image above.

 Design a 3-bit multiplier using a combination of half and full adders.

Name the half adder as halfbitadder 2-bit multiplier as mult2bit and 3-bit multiplier as

mult3-bit. Provide screenshots in your submission document.

NB: Note that both half and full adders can be combined to design a multiplier. Also we

have designed a full bit adder in our previous lab so brainstorm on what the half bit

adder would be. This should be simple, right?

1. How many AND gates and adders will be required in designing a 3-bit multiplier?

2. How many XOR and AND gate (s) will be required in designing the half bit adder?

A picture of a 3-bit multiplier can be seen below:

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 Figure 2. 3-bit Multiplier

Part 2: Designing a Divider Circuit

At this stage, we have an understanding of how our addition, subtraction and multiplication
operations are performed by the processor. We have also seen that we can extend an adder to
perform subtraction and multiplication. In the next section, we will design a 2-bit divider
circuit.

Figure 2: Decimal division and its related operations

In figure 2 above, 128 is divided with 8, which results in 16 as the answer, with 0 as the
remainder. So case, 128 is called the dividend, 8 is called the divisor, 16 is called the

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quotient, and 0 is called the remainder. Now, let us take an example of binary division. First,
the following four rules of binary division are the achievable conditions for binary division.

Table 1: Division operation of bits and the results obtained.

Dividend Divisor Result
1 1 1
1 0 Insignificant
0 1 0
0 0 Insignificant

Consider the figure below.

Figure 3: Binary division operation

Step 1: First, look at the first two numbers in the dividend and compare with the divisor. Add
the number 1 in the quotient place. Then subtract the value, and you get 1 as the remainder.
Step 2: Then bring down the next number from the dividend portion and do the step 1 process
again.
Step 3: Repeat the process until the remainder becomes zero by comparing the dividend and
the divisor value.
Step 4: Now, in this case, after you get the remainder value as 0, you have zero left in the
dividend portion, so bring that zero to the quotient portion.

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Therefore, the resultant value is the quotient value which is equal to 111110.

NB: You would realize that designing a divider circuit is more complex. For example, if you
wanted to divide 17 by 5, you could subtract 5 from 17 and use a counter to track the number
of times until you are left with a remainder lesser than 5. Therefore, most of these complex
circuits are programmed or described using a hardware description language.

Part 3 (Post – Lab Activity): Design a simple 8-bit Arithmetic Unit (AU).
At this point, you have built an addsub module that can add and subtract two 8-bit numbers.
The module takes a two-bit signal as a control for addition or subtraction. The next step is to
combine this module with other modules from the library to create a complex module that
performs addition, subtraction, multiplication and division. You will use your designed 8-bit
addsub together with the in-built multiplier and divider to implement an 8-bit AU.

Create a circuit called AU in the same Logisim file and connect two inputs A and B of 8-bits
each to your addsub, multiplier and divider as shown in the image below:

Figure 4: An 8-bit Arithmetic Unit

At this point, you will have three possible results coming out from the add/sub, multiplier and
divider modules. These results are:
 Sum/difference
 Product
 Quotient

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Since the processor must perform one operation at a time, there has to be a means to select
one of the results as the final output. You can use a multiplexer.
A multiplexer (mux) is a combinational circuit that takes 2^n data inputs, n selection inputs
and only 1 output. For instance, a 2-input mux should have 2 data inputs, 1 selection input
and a single output. Similarly, a 4-input mux takes 4 data inputs, 2 selection inputs and a
single output.

Simulations:
Use a 4-to-1 multiplexer to connect the three results from your arithmetic unit to the inputs of
your mux. Since you have only three inputs being filled, your mux should have one empty
data input. Using the selector, you can choose which module’s result will be at the output.
Test the result of the circuit the following way. Use the following test cases in testing your
ALU:

 Add A = 64 and B = 8
 Subtract A = 10 from B = 32
 Multiply A = 20 and B = 2
 Divide A = 40 by B = 8

Part 4: Design a simple 8-bit Logic Unit (LU) using a Comparator.

Equal (=) Functionality

Below is a truth table for evaluating the equality of two 1-bit inputs A and B.

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 Input A Input B A=B
0 0 1
0 1 0
1 0 0
1 1 1

From the truth table, we can realize that our expression would be E = A’B’ + AB. You will
realize that our expression E = A’B’ + AB (and truth table above) is equivalent to the XNOR
Gate truth table. Thus, we can simply use the XNOR Gate to realize equality by designing a
circuit (name as equal1bit) which outputs high when both input bits are equal, as show in the
image below:

Figure 3. 1-bit equality

Activity 1: Design an 8-bit equality Circuit

Now, let us design an 8-bit equality checker which takes two 8-bit inputs A and B and

produces a high when both inputs are equal. Name the module circuit as equal8bit. You will

realize that we will need 8 XNOR Gates. We will later need one more AND Gate to AND all

results from the individual bit comparisons to achieve the equality check. Your circuit will

look like the image below:

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 Figure 4. 8-bit equality checker

Less than (<) Functionality

Below is a truth table for evaluating the expression A < B.

Input A Input B A<B
0 0 0
0 1 1
1 0 0
1 1 0

From the truth table above, we can derive our expression, L = A’B, as implemented in the
image below. Name circuit as less1bit.

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 Figure 5. 1-bit less than

Unlike checking for equality which is straightforward by comparing bit by bit and ANDing
all outputs from each bit-by-bit comparison, the less than operation requires that we take into
consideration, the positional weights of the bits while comparing. For example:
A = 00000101 = 5
B = 00001000 = 8
In the example above, A < B will result in a low output (right after comparing the A0 and B0)
if we do just bit-by-bit comparison.

Greater than (>) Functionality

Below is a truth table for evaluating the expression A > B.

Input A Input B A>B
0 0 0
0 1 0
1 0 1
1 1 0

From the truth table above, we can derive our expression, L = AB’, as implemented in the
image below. Name circuit as great1bit.

Figure 6. 1-bit greater than

Like the less than operation, we must take into consideration, the positional weights of the
bits while comparing. We leave it as a challenge to design such circuit.
For example:
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A = 00000100 = 4
B = 00000001 = 1
In the example above, A > B will result in a low output (right after comparing the A0 and B0)
if we do just bit-by-bit comparison.

Activity 2 (Post-Lab Activity): Designing an 8-bit Logic Unit (LU) Using a

Comparator

The objective of this section is to implement the operations involved in the Logical Unit (LU)
of an Arithmetic Logic. These are the basic operations of a comparator – equal, greater and
less than. Afterward, the Logic Unit can be combined with the Arithmetic Unit to form a
basic 8-bit Arithmetic Logic Unit.

Add a new circuit and name it as LU. In this part, we will use Logisim’s comparator which
allows us to easily compare two values for any number of input bits. The comparator can be
found in the Arithmetic folder, like the image below:

The first input bit(s), A is the input preceding the operator, while B follows the operator.
Here, you will supply the comparator with two 8-bit inputs and expect a 1-bit output (high or
low) each from the three operations after comparison. Ensure that the Numeric Type
Property of your comparator is Unsigned. For example:
A = 00000010 = 2
B = 00000001 = 1

Figure 5: Simulating the behavior of a comparator.

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We can extend our logic unit to include other operations and a mux as shown in the image
below. (Hint: we are using an 8-input mux because we have 6 possible outputs from our
Logic Unit, hence the use of a 3-bit selector).

From this:

To this:

Figure 6: An 8-bit Logic Unit

Part 5: Design a simple 8-bit Arithmetic Logic Unit (ALU) using a

Comparator.
At this stage, you should have an:

 8-bit Arithmetic Unit

 8-bit Logic Unit with 6 possible outputs

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  Combine these 2 units to form an 8-bit Arithmetic Unit (Hint: example below)

An ALU with a simple Logical Unit that has four possible outputs (hence the use of a 4-input
mux and a 2-bit selector) is shown in the image below:

Figure 7: Arithmetic and Logic Units combined.

Now, replicate the same for your ALU. Note that your Logic Unit will have 3 selectors
due to your implementation in Part 4 above.

Complete the following test cases:

 Test Case A:
Multiply A = 10 and B = 22 by hand. Indicate the product in binary.
Indicate a high (true) or a low (false) for the following:
I. A>B
II. A <= B
Justify your responses above by simulating your circuit and attach screenshots.

 Test Case B:
Divide A = 255 and B = 5 by hand. Indicate the quotient in binary.
Indicate a high (true) or a low (false) for the following:
I. A != B
II. A >= B
Justify your responses above by simulating your circuit and attach screenshots.

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  Test Case C:
Subtract A = 250 and B = 27 by hand. Indicate the difference in binary.
Indicate a high (true) or a low (false) for the following:
III. A<B
IV. A=B
Justify your responses above by simulating your circuit and attach screenshots.

Part 6: IN-CLASS DESIGN CHALLENGE PROBLEM (Will be graded by the

FIs)

Team A: Automatic Water Pump Controller Design

Problem Statement: Design a combinational logic circuit for an Automatic Water Pump
Controller that operates based on water levels monitored by sensors:

 Low-Level Sensor (L): 1 if water is above low, 0 if below.

 Mid-Level Sensor (M): 1 if water is above mid, 0 if below.
 High-Level Sensor (H): 1 if water is at or above high, 0 if below.

The pump should:

 Turn ON if water is below the low mark.

 Turn OFF if water reaches the high mark.

Inputs:

 L, M, H

Output:

 P where P=1, if the pump is ON.

Steps to Follow:

1. Truth Table: Create the truth table for all sensor combinations.
2. SOP and POS:
o Develop the SOP and POS expressions.
3. Universal Gate Implementation:
o Design the circuit using NAND or NOR gates only by converting the Boolean
expressions.
o Implement the design in Logisim Evolution using universal gates.
4. Simulation:

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 o Simulate the circuit to verify that the pump operates correctly under various
water level conditions.

Real-World Application: This system mimics an automatic water tank controller for
efficient water management in homes or industries.

Team B: Digital Lock System

Problem Statement: Design a combinational logic circuit for a Digital Lock System. The
lock uses a 4-digit combination, with each digit represented as a binary input:

 1 means the button for that digit is pressed.

 0 means it is not pressed.

The lock opens (output 1) if the correct combination (A,B,C,D) is entered. For this problem,
let the combination be 1010.

Inputs:

 A,B,C,D (digit inputs)

Output:

 O where O=1 if the combination is correct.

Steps to Follow:

1. Truth Table: Create the truth table for all input combinations (16 rows).
2. SOP and POS:
o Write the SOP and POS expressions for the correct combination.
3. Universal Gate Implementation:
o Convert the expressions into NAND or NOR gate implementations.
o Build the circuit in Logisim Evolution using these gates.
4. Verification:
o Test the circuit to ensure it unlocks with the correct combination.

Real-World Application: This system models basic security logic in digital locks and
keypads used in safes or secure areas.

TEAM C: Voting System Majority Detector

Problem Statement: Design a combinational logic circuit for a Voting System Majority
Detector. The system takes 5 inputs from voters, each vote represented as:

 1 for YES
 0 for NO

The circuit outputs:

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  1 (MAJORITY YES) if at least 3 votes are YES.
 0 (MAJORITY NO) if fewer than 3 votes are YES.

Inputs:

 V 1 ,V 2 , V 3 ,V 4 ,V 5 (voter inputs)

Output:

 A where A=1, if the majority votes YES.

Steps to Follow:

1. Truth Table: Construct the truth table for all voting combinations (32 rows).
2. SOP and POS:
o Write both SOP and POS forms of the Boolean expression for majority
detection.
3. Universal Gate Implementation:
o Convert the Boolean expressions to use NAND or NOR gates exclusively.
o Build the circuit in Logisim Evolution using these gates.
4. Testing:
o Test the circuit to confirm it correctly identifies majority votes.

Real-World Application: This system models majority-based decision-making, such as in

elections or voting processes in organizations.

TEAM D: Home Security Alarm System

Problem Statement: Design a combinational logic circuit for a Home Security Alarm
System. The system has 4 sensors:

 Front Door (F): 1 if open, 0 if closed.

 Back Door (B): 1 if open, 0 if closed.
 Window (W): 1 if any window is open, 0 if closed.
 Motion Detector (M): 1 if motion is detected, 0 if no motion.

The alarm triggers (output 1) if:

 Either the front or back door is open AND motion is detected.

 Any window is open AND motion is detected.

Inputs:

 F, B, W, M

Output:

 A where A=1 if the alarm is triggered.

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Steps to Follow:

1. Truth Table: Develop the truth table with all possible input combinations.
2. SOP and POS:
o Write both the SOP and POS forms of the Boolean expression for the alarm
logic.
3. Universal Gate Implementation:
o Convert the expressions into a form that can be implemented using NAND or
NOR gates only.
o Design and simulate the circuit using Logisim Evolution, ensuring that all
gates used are NAND or NOR.
4. Testing:
o Test the circuit to verify that the alarm triggers correctly under various
conditions.

Real-World Application: This system is comparable to a modern home security alarm,

ensuring proper monitoring of unauthorized entries.

Part 7: Reflections Questions

1. How did the selection of multiplexers contribute to the overall design of the ALU, and
what were the key considerations in choosing the appropriate multiplexer
configurations?

2. Reflect on the role of comparators within the ALU design. How did these components
facilitate comparison operations, and what challenges or limitations did you encounter
when integrating them into the circuit?

3. Discuss the significance of full adders in the ALU's arithmetic operations. How did
the utilization of full adders impact the efficiency and functionality of addition and
subtraction processes within the ALU?

4. When implementing subtraction in the adder/subtractor circuit using two’s

complement, what steps does the circuit take to perform the operation? How does this
process differ from a basic addition operation, and why is two's complement used for
subtraction in digital systems?

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 5. Consider the trade-offs and design decisions involved in balancing performance,
complexity, and resource utilization within the ALU design. How did you navigate
these trade-offs to achieve an optimal solution?

6. Reflect on the overall design process and teamwork dynamics during the lab session.
What were the key challenges faced by the team, and how were they addressed
collaboratively? What lessons can be learned from the design and implementation
process for future projects or improvements?

Submission:
Please submit a zip file (name as ID_Lab3) containing:
 PDF of your written responses.
 Updated Logisim-evolution file.

Grading Rubric for Logisim Evolution Logic Design Lab Session (Total: 100
Points)

Needs
Criteria Excellent (16-20) Good (11-15) Satisfactory (6-10) Points
Improvement (0-5)
Design meets
Design meets all
most Design meets basic Design does not
specifications;
specifications; specifications; meet specifications;
Design Accuracy circuits function /20
minor errors in several errors in circuits do not
correctly for all
function for function. function.
test cases.
some cases.
Effectively uses a
variety of
Uses appropriate
components Limited variety of Incorrect or
components, but
Use of (AND, OR, NOT, components; may inappropriate use of
may not fully /20
Components XOR, etc.) and rely heavily on one components; lacks
utilize available
demonstrates type. understanding.
options.
understanding of
universal gates.
Logic circuits are
Logic circuits are Basic
optimized and
implemented implementation of Poor implementation
implemented
correctly but logic circuits; of logic circuits; lack
Logic using universal
could be further minimal of optimization; no /20
Implementation gates where
optimized; some optimization; use of universal
applicable; clear
use of universal limited use of gates.
and efficient
gates. universal gates.
design.
Test Cases and Comprehensive Adequate test Minimal test cases; No test cases /20

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 Needs
Criteria Excellent (16-20) Good (11-15) Satisfactory (6-10) Points
Improvement (0-5)
test cases covering
cases covering
all possible
most scenarios; validation is provided; outputs are
Validation scenarios; all
some outputs inconsistent. not validated.
outputs validated
validated.
correctly.
Clear, detailed
Adequate
documentation
documentation Basic
including circuit Poor or no
with some circuit documentation
diagrams, truth documentation;
Documentation diagrams and provided; missing
tables, and disorganized /20
and Presentation explanations; key components;
explanations of presentation;
presentation is presentation lacks
design choices; difficult to follow.
somewhat clarity.
well-organized
organized.
presentation.
Actively engaged
Participated in Limited
in group work;
Collaboration group work; participation; Did not participate;
contributed
and contributed but minimal no contribution to /10
significantly to the
Participation could have contribution to group work.
project and helped
engaged more. group effort.
peers.
Demonstrates
Shows some No creativity shown;
exceptional Basic design with
creativity in relies entirely on
Creativity and creativity in little creativity;
design; attempts existing designs /10
Innovation design; innovative follows standard
innovative without any
approaches to approaches.
approaches. adaptation.
solving problems.

Total Points: /100

Grading Scale:

 Excellent (85-100 points): Outstanding understanding of logic design principles;

exceptional work in all areas.
 Good (70-84 points): Good grasp of concepts; minor improvements needed in one or
two areas.
 Satisfactory (50-69 points): Basic understanding; significant improvements needed
in several areas.
 Needs Improvement (0-49 points): Lacks understanding; major improvements
required across all areas.

This rubric is designed to effectively assess the students’ performance in the logic design lab
session, ensuring comprehensive evaluation across critical areas of their work, scaled to a
total of 100 points.

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