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Hardware Implementation Report

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16 views5 pages

Hardware Implementation Report

Uploaded by

mohitgupta8102442050
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Hardware Implementation

Raj Kohale
April 2024

1 Introduction
In this section I have done basic program implementation on a Hardware where we use ZYBO Z-7010. Here I have
done two types of implementation
1. By using ZYBO kit input/output port
2. BY using Virtual input/output on FPGA.

2 Tools/Requirements
2.1 Xiling Vivado
To simulate and for observing behaviour of different logic gate we need Xiling Vivado tool.Vivado is a software for
synthesis and analysis of hardware description language designs, superseding Xilinx ISE with additional features
for system on a chip development and high-level synthesis.

2.2 ZYBO Z-7010


The ZYBO (ZYnq BOard) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit de-
velopment platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is
based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core
ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. When coupled
with the rich set of multimedia and connectivity peripherals available on the ZYBO, the Zynq Z-7010 can host a
whole system design.

3 What I have done?


3.1 Basic Overview
I have written verilog code Binary to Gray converter in Xiling Vivado then by doing simulation I have observed
behaviour of program. After that I have set input/output Power supply i.e.(3.3V) and save constrained file with
extension XDC and perform RUN Implementation and generate bit stream for program.
After creating bit stream I have connected ZYBO kit with system and turn on kit(power supply for kit 5V). Then
from Open hardware manager I have choose target and connect ZYBO kit with Xiling Vivado. After that I have
dump file on kit and by changing inputs from kit buttons I have observed output from LEDs.

3.2 Steps to be followed


3.2.1 Step 1
Write the verilog code and test bench for the given execution and save the file in Design Source and Simulation
Source.

3.2.2 Step 2
Simulation
Perform the run simulation and observe the simulated result and verify with the inputs which is given from the
testbench.

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3.2.3 Step3
RTL analysis (Schematic)
Go for the I/O planning and select package pin and set the pin numbers which we are using for inputs and
outputs.(pin numbers will be given on the kit). Similarly, set the values of I/O standards for the inputs and
outputs. (refer data sheet for the I/O standards values for each input and output). Finally save the file with the
extension of .xdc.

3.2.4 Step 4
Synthesis and Run Implementation
Go for the run synthesis, during synthesis in Xilinx Vivado, the tool translates Register Transfer Level (RTL)
code, written in Hardware Description Languages (HDLs) (i.e. Verilog) into a netlist. This netlist represents a
digital circuit composed of logic gates and flip-flops.

3.2.5 Step5
Hardware Connection
Connect the FPGA board to the Device.

3.2.6 Step6
Program and Debug
Click on Generate Bitstream, it will generate bitstream of program.
Bitstream The bitstream tells the FPGA how to connect its internal building blocks (logic gates and flip-flops)
to achieve the desired functionality based on the program.
Select Program device from the open hardware manager and give the bitstream file to the device. It will dump
bitstreams on the FPGA board.

3.2.7 Step 6
Hardware Implementation
Give the different inputs from the inputs buttons and observe the output from the Leds.

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4 Observations
4.1 Binary to Gray code

Figure 1: Verilog code for binary to gray

4.2 Testbench

Figure 2: Testbench

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4.3 Simulation

Figure 3: Simulation

4.4 RTL analysis schematic

Figure 4: RTL analysis schematic

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4.5 FPGA board connection

Figure 5: FPGA board

5 What I have learned?


1. How to write verilog code for the given functionality.
2. By creating testbench for the code observe the simulation output and check the given code matched with
functionality or not.
3. Observe the RTL Schematic and do I/O floor planning.

4. How to generate bitstream from the code.


5. How the output will be coming by varying the inputs on the kit, which shows the desired functionality based
on the our requirements.

6 Demonstration
Hardware implementation

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