5 4 3 2 1

8MPLUS-BB i.MX8M Plus Reference Base Board

Table of Content Revision History
Page 1 Cover
D Rev. Code Date By Description D

Page 2 Block Diagram A 2019-11-04 Frank Initial version

Page 3 PWR TREE 1. Change R452 to 1K, to get the correct output level of VPCIe_3V3.
A1 2020-04-28 Frank 2. Update PMIC PCA9450C I2C address to "0x25", according to latest datasheet.
Page 4 CPU IO INTERFACE 3. Update "ENET0" naming to "ENET2", to meet with latest fusemap and software definition.
4. Change R51 to 324K, to meet the new requirement for VBUS detect threshold (>=3.7V) from
Page 5 USB TYPE-C Power USB Type-C Functional Test Specification since 2019
5. Change several Boot Mode configurations to "Reserved".
Page 6 USB3.0 TYPE-C DRP 6. Update the block diagram, change "OTG" to "Dual Role".
7. Change U48 from PCA9617ADP to PCA9509ADP for better compatibility of HDMI monitors, R185 needs be populated.
Page 7 USB3.0 HOST 1. Change D2, D4 from NSR0320 to BAT54HT1 to reduce the reverse leakage current for Type-C Quadramax Load Test.
2. Change R186 from 10K to 100K, D9, D32 from NSR0320 to BAT54HT1 to reduce the leakage current on CEC line.
Page 8 Giga Ethernet0 HDMI CTS requires <=1.8uA on CEC line.
A2 2020-10-10 Frank 3. Change R333, R334 from 4.7K to 1.5K, for better drive strength of I2C signals.
Page 9 Giga Ethernet1 4. Change U30 from PCMF1USB3S to PCMF1HDMI2S, which is dedicated for HDMI application.
5. DNP R432 and R433, remove the signal connections for USB1_DNU(USB1_ID), USB2_DNU(USB2_ID),
these pins CAN'T be used, according to latest I.MX8M Plus datasheet.
Page 10 M.2 PCIe3.0
C 1. Change "X-8MPLUS-BB" to "8MPLUS-BB" for mass production. C

Page 11 MicroSD A3 2021-01-11 Frank 2. Remove the text "NXP CONFIDENTIAL AND PROPRIETARY" on each page.
3. Change R452 to 0ohm, to improve load transient response for high power consumption M.2 devices.
Page 12 MIPI CSI 4. Change U56 from NTB0104 to NTS0104, which can support bigger capacitive load.

Page 13 MIPI DSI 1. Remove Q3, add U81 and related components to reduce the output delay of PCIE external reference clock.
2. Remove R432, R433, as USB1_DNU(USB1_ID), USB2_DNU(USB2_ID) are not used.
B 2021-03-12 Frank
Page 14 LVDS Display 3. Add R142, provide the connection for M.2 PCIE_DIS2, DNP as default.
4. Add R163, provide the option to control PWDN of each camera module separately, DNP as default.
Page 15 HDMI Display
B1 2021-05-13 Elyon 1. Change C120 and C121 to 0.22uF (150-79999) to meet the spec requirement for PCIe Gen3 TX AC coupling capacitance
(175~265nF).
Page 16 Audio CODEC

Page 17 CAN

Page 18 Expansion CN

Page 19 Remote Debug

B Page 20 Power B

Page 21 BOOT_CFG

1. Interrupted lines coded with the same letter or letter

combinations are electrically connected.

2. Device type number is for reference only. The

number varies with the manufacturer.

3. Special signal usage:

_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
4. Interpret diagram in accordance with American
National Standards Institute specifications, current
revision, with the exception of logic block symbology.

A
Preliminary - Subject to Change without Notice! A
Microcontroller Product Group
This board was designed for maximum flexibility in 6501 William Cannon Drive West
Austin, TX 78735-8598
software development and demonstrates multiple This document contains information proprietary to NXP and shall not be used for engineering design,
functions possible with i.MX processors. Although best procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
design practices have been applied, some areas may ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
not be suitable for a mass-production design. Designer: Drawing Title:
FL
8MPLUS-BB
NXP CONFIDENTIAL AND PROPRIETARY Drawn by:
FL
Page Title:
Title and Rev History
Approved: Size Document Number Rev
<Approver> C SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 1 of 21

5 4 3 2 1
 5 4 3 2 1

IMX8MPLUSLPD4‐EVK 8MPLUSLPD4‐EVK
8MPLUSLPD4-CPU
46371
46368
8MPLUSDR4‐EVK
8MPLUSDDR4‐CPU 47568
8MPLUS-BB 46370 8MPLUS‐BB 46370
### Block Diagram ###
D D

MIPI CSI MIPI CSI MIPI DSI LVDS x2 HDMI2.0

with eARC
mini-SAS CN mini-SAS CN mini-SAS CN mini-SAS CN CON19

LANE x4 LANE x4 LANE x4 2x 4LANE

QSPI Nor MIPI CSI1 MIPI CSI2 MIPI DSI LVDS x2 HDMI2.0
Micron 32MB
x4 bits
QSPIA USB3.0
Dual Role USB TYPE-C 5V@3A
MT25QU256ABA1 DRP

USB3.0
HOST USB TYPE-A [email protected]
C Button PMIC POWER HOST C

Reset NXP PCA9450C

DRAM
Micron LPDDR4 48Gb
MT53E1536M32D4DT-046 WT:A
Micron DDR4 16Gb x2
x32 bits
DRAM
NXP SDHC1/UART/PCM

PCIe3.0
M.2 NGFF
KEY-E:WiFi/BT...
2.4/5GHz

MT40A512M16LY-075:E
i.MX8M Plus
ARM CORTEX 4x A53 + M7 Giga Ethernet
RGMII x2 RJ45
eMMC 5.1 x8 bits
Realtek: RTL8211FDI
Sandisk 32GB SDHC3
SDINBDG4-32G-I1

JTAG
JTAG
B
MicroSD x4 bits
SDHC2
10 PIN Header Remote Debug B

SD3.0 Support

Button x2 UART(A53/M7)
DBG UART PC
ONOFF/GPIO UART->USB FT4232H
ONOFF
GPIO/UART/SPI/SAI SAI/I2C I2C
Internet

GPIO/UART... SAI/I2C... I2C

Boot Switch PC

EXP CN Audio Codec I2C CN

GPIO/UART SAI/GPIO/I2C... I2C On 8MPLUSLPD4‐CPU/8MPLUSD4‐CPU/8MPLUSDR3L‐CPU
/SPI/SAI
A A
Microcontroller Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

3.5mm POLE Headphone ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
8MIC-RPI-MX8 Designer:
FL
Drawing Title:
HSL HSR GND MIC 8MPLUS-BB
CTIA Standard Drawn by: Page Title:
PDM Mic Array FL Block Diagram
Approved: Size Document Number Rev
<Approver> C SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 2 of 21

5 4 3 2 1
 5 4 3 2 1

IMX8MPLUSLPD4-EVK PWR TREE

Type-C Port 0 VBUS_IN VSYS

5-20V DCDC BUCK 5V/3A
D Power Only PMIC: PCA9450C CPU: i.MX8M Plus D

MPS MP8759GD
SNK PD (5‐20V) SEQ REG TYP Max Capability(mA) SEQ PWR/Signal TYP Required(mA)
DCDC_5V 1 LDO1 1.8 10 1 NVCC_SNVS_1V8 1.8 10
5V/5A 2 RTC_CLK ‐‐ ‐‐ 2 32K_INTERNAL ‐‐ ‐‐
3 BUCK1/3 0.85/0.95 6000 3 VDD_SOC 0.85/0.95 5000
4 BUCK2 0.85/0.95/1.0 3000 4 VDD_ARM 0.85/0.95/1.0 2200
5 LDO3 1.8 300 5 VDDA_1V8 1.8 300
6 BUCK5 1.8 2000 6 VDD_1V8/NVCC_xxx 1.8 NxCxVx(0.5xF)
7 BUCK6 1.1 2000 7 NVCC_DRAM_1V1 1.1 NxCxVx(0.5xF)
8 BUCK4 3.3 3000 8 VDD_3V3/NVCC_xxx 3.3 NxCxVx(0.5xF)
8 MUXSW 3.3 400 8 VSD_3V3 3.3 300
9 LDO5 3.3/1.8 150 9 NVCC_SD2 3.3/1.8 10
10 POR_B ‐‐ ‐‐ 10 POR_B ‐‐ ‐‐

LPDDR4
VEXT_3V3 VDD1
3.3V/4A VDD2/VDDQ
DCDC BUCK
MPS MP2147
QSPI
C VCC C

VDD_5V
Load SW 5V/3A
MOSFET eMMC
VCCQ
VCC

WiFi/BT
VBAT
VIO

Audio CODEC
AVDD/LINE VDD
SPKVDD

MicroSD
VCC

mini-SAS
B
(MIPI CSI/DSI) B
1.8V
3.3V
5V

mini-SAS (LVDS)
1.8V
PER_12V 3.3V
DCDC BUCK 12V/3A 5V
MPS MP2263GD
12V

M.2 PCIe
2500mA
3.3V

USB Type-C Port2

3400mA
5V [400mA-3400mA]

USB Type-A Host

900mA
A
5V [900mA] A

Microcontroller Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ___ IUO: _X_ PUBI: ___

Designer: Drawing Title:
FL
8MPLUS-BB
Drawn by: Page Title:
FL Power Tree
Approved: Size Document Number Rev
<Approver> Custom SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 3 of 21

5 4 3 2 1
 5 4 3 2 1

IO Connector IO Expansion
Receptacle Receptacle VDD_1V8 VDD_3V3
J1 J2 C1 C2 C3 C4
2 1 2 1 1.0UF 0.1uF 1.0UF 0.1uF
4 3 CSI2_DN3 4 3 LVDS1_TX0_P 10V 25V 10V 25V
12 CSI2_DN3 LVDS1_TX0_P 14
6 5 CSI2_DP3 6 5 LVDS1_TX0_N 0402_CC 0402_CC 0402_CC 0402_CC
12 CSI2_DP3 LVDS1_TX0_N 14
8 7 8 7
WDOG_B 10 9 BOOT_MODE0 CSI2_DN2 10 9 LVDS1_TX1_P

23
21
19 WDOG_B BOOT_MODE0 19 12 CSI2_DN2 LVDS1_TX1_P 14
GPIO1_IO15 12 11 BOOT_MODE1 CSI2_DP2 12 11 LVDS1_TX1_N GND U1 GND
12 CSI_MCLK BOOT_MODE1 19 12 CSI2_DP2 LVDS1_TX1_N 14
D 14 13 BOOT_MODE2 14 13 1 EXT_PWREN1 VEXT_3V3 power control, default high to enable. D

VDD_I2C
VDD
BOOT_MODE2 19 P0_0 EXT_PWREN1 20
GPIO1_IO14 16 15 BOOT_MODE3 CSI2_CKN 16 15 LVDS1_CLK_P 2 EXT_PWREN2 PER_12V power control, default low to disable, only enable after Type‐C power input raises to 15V or 20V.
7 USB2_PWR_EN BOOT_MODE3 19 12 CSI2_CKN LVDS1_CLK_P 14 P0_1 EXT_PWREN2 20
GPIO1_IO13 18 17 CSI2_CKP 18 17 LVDS1_CLK_N 3 CAN1/I2C5_SEL SPDIF CAN1/I2C5 IOMUX select, default low for CAN1, high for I2C5.
14 LVDS_TS_nINT 12 CSI2_CKP LVDS1_CLK_N 14 P0_2
GPIO1_IO12 20 19 GPIO1_IO06 20 19 4 PDM/CAN2_SEL SAI5 PDM/CAN2 IOMUX select, default low for PDM, high for CAN2.
CSI_nRST 12 CSI2_DN1 LVDS1_TX2_P P0_3 FAN_EN
14 LVDS_BL_PWM
GPIO1_IO11 22 21 GPIO1_IO05
CSI1_SYNC 12 12 CSI2_DN1
22 21 5 FAN_EN 18 FAN Power control, default low to disable.
CSI2_DP1 LVDS1_TX2_N LVDS1_TX2_P 14 P0_4 PWR_MEAS_IO1
24 23 GPIO1_IO01
DSI_BL_PWM 13 12 CSI2_DP1 24 23 GND 18 6 PWR_MEAS_IO1 19
GPIO1_IO00 LVDS1_TX2_N 14 ADDR P0_5 PWR_MEAS_IO2
14 LVDS_EN
GPIO1_IO10 26 25 26 25 7 PWR_MEAS_IO2 19
GPIO1_IO9 28 27 CSI2_DN0 28 27 LVDS1_TX3_P EX_POR_B 24 P0_6 8 EXP_P0_7
13 DSI_TS_nINT 12 CSI2_DN0 LVDS1_TX3_P 14 RESET P0_7 EXP_P0_7 10,18
GPIO1_IO8 30 29 USB1_RXN CSI2_DP0 30 29 LVDS1_TX3_N
13 DSI_EN USB1_RXN 6 12 CSI2_DP0 LVDS1_TX3_N 14
GPIO1_IO7 32 31 USB1_RXP 32 31 I2C IO EXP P1_0 10
12 CSI2_SYNC USB1_RXP 6 EXP_P1_0 18
34 33 34 33 LVDS0_TX0_P I2C3_SCL R306 0 IOEXP_SCL 19 11
LVDS0_TX0_P 14 SCL P1_1 EXP_P1_1 18
USB1_DN 36 35 USB1_TXN 36 35 LVDS0_TX0_N I2C3_SDA R307 0 IOEXP_SDA 20 12
6 USB1_DN USB1_TXN 6 LVDS0_TX0_N 14 SDA P1_2 EXP_P1_2 18
USB1_DP 38 37 USB1_TXP 38 37 13
6 USB1_DP USB1_TXP 6 P1_3 EXP_P1_3 18
40 39 40 39 LVDS0_TX1_P 14
LVDS0_TX1_P 14 P1_4 EXP_P1_4 18
42 41 USB2_RXN 42 41 LVDS0_TX1_N 15
USB2_RXN 7 LVDS0_TX1_N 14 P1_5 EXP_P1_5 18
USB1_VBUS_3V3 44 43 USB2_RXP 44 43 GPIO1_IO12 R308 0 IOEXP_nINT 22 16
6 USB1_VBUS_3V3 USB2_RXP 7 INT P1_6 EXP_P1_6 18
46 45 46 45 LVDS0_CLK_P 17
LVDS0_CLK_P 14 P1_7 EXP_P1_7 18
48 47 USB2_TXN 48 47 LVDS0_CLK_N
USB2_TXN 7 LVDS0_CLK_N 14
USB2_VBUS_3V3 50 49 USB2_TXP 50 49
7 USB2_VBUS_3V3 USB2_TXP 7

VSS
52 51 52 51 LVDS0_TX2_P

EP
LVDS0_TX2_P 14
USB2_DN 54 53 PCIE_CLKN 54 53 LVDS0_TX2_N
7,10 USB2_DN PCIE_CLKN 10 LVDS0_TX2_N 14
USB2_DP 56 55 PCIE_CLKP 56 55 PCA6416AHF,128
PCIE_CLKP 10

9
25
7,10 USB2_DP 58 57 58 57 LVDS0_TX3_P
LVDS0_TX3_P 14
JTAG_TMS 60 59 PCIE_RXN 60 59 LVDS0_TX3_N
19 JTAG_TMS PCIE_RXN 10 LVDS0_TX3_N 14
JTAG_TDO 62 61 PCIE_RXP 62 61
19 JTAG_TDO PCIE_RXP 10
JTAG_TDI 64 63 64 63
19 JTAG_TDI JTAG_MOD PCIE_TXN
66 65 PCIE_TXN 10 66 65
21 JTAG_MOD JTAG_TCK PCIE_TXP
68 67 PCIE_TXP 10 68 67 GND
19 JTAG_TCK
70 69 70 69
CSI1_DN0 72 71 DSI_DN0 NAND_DQS 72 71 SD1_STROBE
12 CSI1_DN0 DSI_DN0 13 CSI_PWDN 12
CSI1_DP0 74 73 DSI_DP0 ONOFF 74 73 SD1_RESET_B
12 CSI1_DP0
76 75
DSI_DP0 13 19 ONOFF
POR_B 76 75 SD1_CLK M2_SD_nRST 10 VDD_1V8 VDD_3V3 VDD_1V8 VDD_3V3
19 POR_B M2_SD_CLK 10
CSI1_DN1 78 77 DSI_DN1 PMIC_ON_REQ 78 77 SD1_CMD C6 C7 C8 C9 C286 C287 C288 C289
12 CSI1_DN1 DSI_DN1 13 20 PMIC_ON_REQ M2_SD_CMD 10
CSI1_DP1 80 79 DSI_DP1 80 79 1.0UF 0.1uF 1.0UF 0.1uF 1.0UF 0.1uF 1.0UF 0.1uF
12 CSI1_DP1 DSI_DP1 13
82 81 82 81 SD1_DATA0 M2_SD_DATA0 10 VDD_1V8 10V 25V 10V 25V 10V 25V 10V 25V
CSI1_CKN 84 83 DSI_CKN 84 83 SD1_DATA1 M2_SD_DATA1 10 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC
12 CSI1_CKN DSI_CKN 13
CSI1_CKP 86 85 DSI_CKP CLKIN1 86 85 SD1_DATA2 M2_SD_DATA2 10
12 CSI1_CKP DSI_CKP 13 TP1
88 87 88 87 SD1_DATA3 M2_SD_DATA3 10 U4
CSI1_DN2 90 89 DSI_DN2 CLKOUT1 90 89 GND GND GND 3 2 GND

23
24
12 CSI1_DN2 DSI_DN2 13 TP2 VCCA VCCB

1
CSI1_DP2 92 91 DSI_DP2 92 91 SD1_DATA4 R41 U3
12 CSI1_DP2 DSI_DP2 13
94 93 CLKIN2 94 93 SD1_DATA5 2.2K R312 10K 4

VCCA

VCCB1
VCCB2
CSI1_DN3 96 95 DSI_DN3 TP3
96 95 SD1_DATA6 VDD_1V8 R322 10K 5 1DIR
12 CSI1_DN3 DSI_DN3 13 M2_BT_WAKE_HOST 10 2DIR
CSI1_DP3 98 97 DSI_DP3 CLKOUT2 98 97 SD1_DATA7 1
12 CSI1_DP3 DSI_DP3 13 TP4 M2_SD_WAKE_HOST 10 1OE
100 99 100 99 SD1_DATA4 3 21 R323 10K 16
A1 B1 PCIe_nDIS_3V3 10 GND 2OE
PU as default SD1_DATA5 4 20 PU as default
A2 B2 PCIe_nRST_3V3 10
PMIC_32K_OUT R314 0 REF_CLK_32K 5 19
A3 B3 REF_CLK_32K_3V3 10
DF40C-100DS-0.4V(51) DF40C-100DS-0.4V(51) GPIO1_IO00 R315 0 DNP 6 18 SAI2_RXC 6 15
A4 B4 1A1 1B1 ENET_nRST 9
7 17 SAI1_RXD0 7 14
A5 B5 1A2 1B2 ENET1_nRST 8
NAND_DQS 8 16 SAI2_RXFS 8 13
A6 B6 VEXT_3V3_EN 20 2A1 2B1 ENET_nINT 9
GND GND GND GND SPDIF_EXT_CLK 9 15 SAI1_RXD1 9 12
A7 B7 CAN1_STBY_3V3 17 2A2 2B2 ENET1_nINT 8
C SAI2_MCLK 10 14 C
A8 B8 CAN2_STBY_3V3 17
10 11
R4 10K 2 GND1 GND2
VDD_1V8 DIR OE=H: Hi‐Z; OE=L: enabled

GND1
GND2
GND3
EPAD
22 74AVC4T245GU

Receptacle Receptacle
OE
DIR=H, A ‐> B
74AVC8T245BQ GND GND
OE=H: Hi‐Z; OE=L: enabled DIR=L, A <‐ B

11
12
13
25
J3 J4
2 1 SAI5_RXFS 2 1 SAI5_RXD0 DIR=H, A ‐> B
VSYS_5V 4 3 VSYS_5V 18 SAI5_RXFS
SAI5_RXC 4 3 SAI5_RXD1
SAI5_RXD0 18
6 5
18 SAI5_RXC
6 5 SAI5_RXD2
SAI5_RXD1
SAI5_RXD2
18
18
DIR=L, A <‐ B GND
8 7 SAI5_MCLK 8 7 SAI5_RX3 GND
17 CAN2_RX
10 9 10 9
12 11 SAI2_RXFS 12 11 SAI2_TXC
SAI2_RXC M2_PCM_CLK 10
14 13 14 13 SAI2_TXFS
M2_PCM_SYNC 10
16 15 16 15 SAI2_TXD
SAI2_MCLK M2_PCM_OUT 10
18 17 18 17 SAI2_RXD
M2_PCM_IN 10
20 19 20 19
22 21 SAI3_MCLK 22 21 SAI3_TXC
16 SAI3_MCLK SAI3_TXC 16
24 23 SAI3_RXC 24 23 SAI3_TXFS
16 AUD_PWR_EN SAI3_TXFS 16

CAN Selection
26 25 SAI3_RXFS 26 25 SAI3_TXD
16 AUD_nINT SAI3_TXD 16

I2C Level shifter

28 27 SAI3_RXD 28 27
16 SAI3_RXD
30 29 30 29
VDD_3V3 32 31 VDD_1V8 SPDIF_TX 32 31 ECSPI2_SCLK
ECSPI2_SCLK 18
34 33 SPDIF_RX 34 33 ECSPI2_SS0
ECSPI2_SS0 18
36 35 SPDIF_EXT_CLK 36 35 ECSPI2_MOSI
ECSPI2_MOSI 18
VDD_1V8
38 37 38 37 ECSPI2_MISO
ECSPI2_MISO 18
40 39 40 39
42 41 PMIC_32K_OUT UART3_CTS 42 41 HDMI_DDC_SCL
VSD_3V3 44 43 SYS_nRST
18 UART3_CTS
UART3_RTS 44 43 HDMI_DDC_SDA
HDMI_DDC_SCL 15
SYS_nRST 19 18 UART3_RTS HDMI_DDC_SDA 15
46 45 PMIC_SCLL UART3_TXD 46 45 C33 C37
TP52 18 UART3_TXD
48 47 PMIC_SDAL UART3_RXD 48 47 HDMI_HPD 0.1uF 0.1uF
TP53 18 UART3_RXD HDMI_HPD 15
50 49 50 49 HDMI_CEC VDD_1V8 VDD_1V8 VDD_3V3 VDD_3V3 25V 25V

12
HDMI_CEC 15

9
UART1_TXD 52 51 PMIC_SCLH ENET_MDC 52 51 U52 0402_CC 0402_CC
10 M2_UART_TXD TP54 8,9 ENET_MDC
UART1_RXD 54 53 PMIC_SDAH ENET_MDIO 54 53 EARC_N_HPD SPDIF_TX 1
10 M2_UART_RXD TP55 8,9 ENET_MDIO EARC_N_HPD 15
UART1_CTS 56 55 I2C2_SCL ENET_TX_CTL 56 55 EARC_P_UTIL
10 M2_UART_CTS I2C2_SCL 10,12,13,14 9 ENET_TX_CTL EARC_P_UTIL 15
UART1_RTS 58 57 I2C2_SDA ENET_TXC 58 57 GND
10 M2_UART_RTS I2C2_SDA 10,12,13,14 9 ENET_TXC
60 59 60 59 HDMI_TXCN C10 C11 CAN1_TX 2 11 I2C5_SCL
HDMI_TXCN 15 17 CAN1_TX
UART2_TXD 62 61 I2C3_SCL ENET_TD0 62 61 HDMI_TXCP 0.1uF 0.1uF
19 UART2_TXD I2C3_SCL 12,14,16 9 ENET_TD0 HDMI_TXCP 15
A53 Debug UART2_RXD 64 63 I2C3_SDA ENET_TD1 64 63 25V 25V 10
19 UART2_RXD I2C3_SDA 12,14,16 9 ENET_TD1
UART4_TXD 66 65 I2C4_SCL ENET_TD2 66 65 HDMI_TXN0 R7 R8 R9 R10 0402_CC 0402_CC R11 R12 R13 R14 SPDIF_RX 4
19 UART4_TXD 9 ENET_TD2 HDMI_TXN0 15
M7 Debug UART4_RXD 68 67 I2C4_SDA ENET_TD3 68 67 HDMI_TXP0 I2C2/I2C3 pull up on SOM 10K 10K 10K 10K 10K 10K 10K 10K
19 UART4_RXD 9 ENET_TD3 HDMI_TXP0 15
70 69 70 69 DNP DNP DNP DNP GND GND

11
1
72 71 ENET_RX_CTL 72 71 HDMI_TXN1 U5 CAN1_RX 5 8 I2C5_SDA
9 ENET_RX_CTL HDMI_TXN1 15 17 CAN1_RX
74 73 SAI1_TXC ENET_RXC 74 73 HDMI_TXP1

VCCA

VCCB
ENET1_RXC 8 9 ENET_RXC HDMI_TXP1 15
SAI1_RXFS 76 75 SAI1_TXD0 76 75 7 CAN1/I2C5_SEL
8 SAI1_RXFS ENET1_TD0 8
SAI1_RXC 78 77 SAI1_TXD1 78 77 HDMI_TXN2 I2C2_SCL 2 10
8 SAI1_RXC ENET1_TD1 8 HDMI_TXN2 15 A1 B1 I2C2_SCL_3V3 6,10
80 79 80 79 HDMI_TXP2 I2C2_SDA 3 9 NLAS3158
HDMI_TXP2 15 I2C2_SDA_3V3 6,10

3
6
SAI1_RXD0 82 81 SAI1_TXD2 ENET_RD0 82 81 I2C3_SCL 4 A2 B2 8 SPDIF_TX R444
ENET1_TD2 8 9 ENET_RD0 A3 B3 I2C3_SCL_3V3 5,18 TP11
B SAI1_RXD1 84 83 SAI1_TXD3 ENET_RD1 84 83 I2C3_SDA 5 7 SPDIF_RX 10K B
ENET1_TD3 8 9 ENET_RD1 A4 B4 I2C3_SDA_3V3 5,18 TP12
SAI1_RXD2 86 85 SAI1_TXD4 ENET_RD2 86 85

GND
8 ENET1_MDC ENET1_TX_CTL 8 9 ENET_RD2
SAI1_RXD3 88 87 SAI1_TXD5 ENET_RD3 88 87 SD2_RESET_B R15 10K 12
8 ENET1_MDIO
90 89
ENET1_TXC 8 9 ENET_RD3
90 89
SD2_RESET_B 11 VDD_1V8 OE
SAI1_RXD4 92 91 SAI1_TXD6 SD2_WP 92 91 SD2_DATA0 NTS0104GU12 GND
8 ENET1_RD0 TCPC_nINT 5 6 USB1_TYPEC_EN_B SD2_DATA0 11

6
SAI1_RXD5 94 93 SAI1_TXD7 SD2_nCD 94 93 SD2_DATA1 GND
8 ENET1_RD1 TCPC_nINT1 6 11 SD2_nCD SD2_DATA1 11
SAI1_RXD6 96 95 SAI1_TXFS SD2_CLK 96 95 SD2_DATA2 I2C2_SCL
8 ENET1_RD2
SAI1_RXD7 98 97 SAI1_MCLK
ENET1_RX_CTL 8 11 SD2_CLK
SD2_CMD 98 97 SD2_DATA3
SD2_DATA2 11 TP5
I2C2_SDA CAN1(Default)
8 ENET1_RD3
100 99
USB1_SS_SEL 6 11 SD2_CMD
100 99
SD2_DATA3 11 TP6
TP7
I2C3_SCL GND CPU(SPDIF)
TP8
I2C3_SDA Note:
NTS part has strict requirement for capacitive load: <150pF;
DF40C-100DS-0.4V(51) DF40C-100DS-0.4V(51) I2C5

GND GND VDD_1V8

GND GND

DCDC_5V VSYS_5V VDD_1V8 VDD_1V8 VDD_3V3 VDD_3V3

C336 C337
J26 0.1uF 0.1uF
1 25V 25V

12
9
R309 0 2 U54 0402_CC 0402_CC
DCDC_5V R310 0 VSYS_5V 3 C12 C13 SAI5_RX3 1
0.1uF 0.1uF
HDR 1X3 25V 25V GND
DNP R16 R17 R18 R19 0402_CC 0402_CC R20 R21 R22 R23 SAI5_RXD3 2 11 CAN2_TX
18 SAI5_RXD3 CAN2_TX 17
10K 10K 10K 10K 10K 10K 10K 10K
GND DNP DNP GND GND DNP DNP 10 PDM/CAN2_SEL

11
1
U6 4

VCCA

VCCB
R445
DCDC_5V VDD_3V3 TP131 VDD_1V8 TP132 I2C4_SCL PCIE_nCLKREQ_1V8 2 10
PCIe_nCLKREQ_3V3 10
5 8 10K
I2C4_SDA PCIe_nWAKE_1V8 3 A1 B1 9
I2C5_SCL A2 B2 PCIe_nWAKE_3V3 10
4 8 7
A3 B3 I2C5_SCL_3V3 18

I2C Address Table

I2C5_SDA 5 7
A4 B4 I2C5_SDA_3V3 18
NLAS3158

GND

3
6
C16 C17 C18 C19 C20 C21 C22 C23 R27 10K 12 GND
0.1uF 22uF 0.1uF 22uF 22uF 0.1uF 22uF 22uF VDD_1V8 OE
25V 16V 25V 10V 10V 25V 10V 10V NTS0104GU12

6
0402_CC 0805_CC 0402_CC CC0603 CC0603 0402_CC CC0603 CC0603 I2C5_SCL
TP9
I2C5_SDA
Port Type Device Address Voltage TP10
GND
GND GND GND GND
I2C1 PMIC PCA9450C 0x25(0100101x) 1.8V Note:
NTS part has strict requirement for capacitive load: <150pF; PDM Mic(Default)
LVDS0 IT6263 0x4C(1001100x) 1.8V CPU
DSI-HDMI ADV7535 0x3D(0111101x) 1.8V
CAN2
M.2 Clock 9FGV0241A 0x68(1101000x) 3.3V
A

I2C2 Type-C1 PTN5110 0x50(1010000x) 3.3V POR_B Buffer A

Type-C1 NX20P3483UK 0x72(1110010x) 3.3V VDD_1V8

CSI1 1.8V
SAI Usage M.2
LVDS1 IT6263 0x4C(1001100x)
1.8V
1.8V
1
U2
6
C5
25V
0.1uF
0402_CC
GND Microcontroller Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
Port Usage Type-C0 PTN5110 0x50(1010000x) 3.3V OE VCC procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
POR_B 2 4 EX_POR_B
SAI1 RGMII ENET1, IO I2C3 CODEC WM8960 0x1A(0011010x) 1.8V A Y ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
3 5 Designer: Drawing Title:
SAI2 M.2 BT IO_EX PCA6416A 0x20(0100000x) 1.8V GND NC FL
74LVC1G125GM 8MPLUS-BB
SAI3 Audio Codec CSI2 1.8V GND Drawn by: Page Title:
FL CPU IO Interface
SPDIF CAN1/I2C5 EX_CN 3.3V R407 0 DNP
Approved: Size Document Number Rev
SAI5 PDM MIC/CAN2 I2C5 I2C_CN 3.3V <Approver> D SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 4 of 21

5 4 3 2 1
 5 4 3 2 1

USB Type-C Power Supply

This is the power supply, must be ON for system running!
USB TYPE-C Port 0
D D
USB_PWR_VBUS_F
J5
F1
A4 DC5-20V Input 1 2
VBUS1 A9
VBUS2 B9 7A USB_PWR_VBUS_F
VBUS3
VBUS4
B4 Rs=7.5 mOhm R453
47K For discharge
Sink up to 20V Load switch
A6 DNP TP102 VBUS_IN
DP1 A7 USB must supply 12V or greater.
DN1 U9
B6
DP2 B7 B2 A1
DN2 GND VLDO_3V3 C2 VBUS1 VINT1 B1
A2 U10 D2 VBUS2 VINT2 C1
USB TYPE-C

SSTXP1 A3 C24 E1 VBUS3 VINT3 D1 + C25 + C26

SSTXN1 USB_CC1_ESD A1 OVP A2 USB_CC1 4.7uF E2 VBUS4 VINT4 100uF 100uF
B11 USB_CC2_ESD B1 CON_CC1 CC1 B2 USB_CC2 50V VBUS5 50V 50V
SSRXP1 B10 CON_CC2 CC2 C27 CC1210 cce8p3x8p3 cce8p3x8p3
Rd
SSRXN1 USB_CC2 C1 C2 0.1uF
B2 D1 CON_SBU1 SBU1 D2 25V
SSTXP2 B3 CON_SBU2 SBU2 0402_CC GND NX20P_OVLO B3 A2 NX20P_ACK
SSTXN2 OVLO ACK TP13
D3 A3 R42 GND
A11 B3 SBUEN CTRL LOGIC VSYS C3 GND 100K R43 100K
SSRXP2 GND FLAG TP16 VDD_1V8
A10
SSRXN2 NX20P0407
A5 USB_CC1_CN NX20P_EN A3
C CC1 B5 USB_CC2_CN GND EN C
CC2

3
Q1
A8 USB_SBU1 GND1 GND2 GND3
SBU1 TP14
B8 USB_SBU2 R44 C164 NX20P5090UK
SBU2 TP15 C3 D3 E3
PD_EN_SNK R2 10K 1 100K 0.22uF
SH1 A1 50V ‐ 5A Max ‐
SH2 SH1 GND1 A12 0402_CC Rds=30 mOhm
SH3 SH2 GND2 B12 R45 C163 NX3008NBKW,115 DNP Vin=2.5~20V, 29V tolerance
SH4 SH3 GND3 B1
SYS PWR Switch 100K 0.22uF

2
SH4 GND4 SW3 50V
1 0402_CC
23K20101#LCP-582RF 2 USB_CC1_ESD GND
USB_CC1_CN 3

4 GND GND GND GND

GND 5 USB_CC2_ESD
USB_CC2_CN 6

M096H-A020RT21A
Control CC for Type‐C PD power on/off control
1-2/4-5 OFF Default
3‐2/6‐5 ON

B
CC Logic Detection B

PD_EN_SRC
TP17
PD_EN_SNK
USB_PWR_VBUS_F PD_EN_SNK 6

D2
Always ON LDO
16
2

U11 A C
USB_PWR_VBUS_F TP23
EN_SNK1
EN_SRC

15 VBUS LDO BAT54HT1

VBUS D4 U13
INTERNAL LDO

R447 10K A C 1 5
C29 2.2uF BYPASS 4 VDD_3V3 USB1_OTG_VBUS_F IN OUT VLDO_3V3
10V 0402_CC BYPASS 11 OD USB_LD_nFLT 4 C35
BAT54HT1
FAULT_N C34 R50 100K 3 NC 2 2.2uF # This LDO is used for preventing the Ld SW
3 1 FRS_EN 1uF R49 47K EN GND 10V
VDD_3V3 VDD VBAT LDO FRS_EN TP97 NX20P3483UK enter into dead battery mode.
BYPASS RAIL

9 DEBUG_ACCESS 35V TPS70933DBVR 0402_CC

DBG_ACC TP18
C30 4.7uF CC0603
10V CC0603 GND GND
default "L" GND GND
USB_CC1 13 6 ILIM_5V_VBUS
CC1 ILIM_5V_VBUS TP20
USB_CC2 14 5
CC2 SLV_ADDR I2C ADDR: 1010000X

TP19 TP21 10 OD GND TP22 TCPC_nINT 4

12 ALERT_N
VDD_5V VCONN_IN Microcontroller Product Group
BAT

C31 0.1uF 8 PD_I2C_SCL 6501 William Cannon Drive West

25V 0402_CC 17 I2C_SCL 7 PD_I2C_SDA Austin, TX 78735-8598
A GND I2C_SDA A
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
PTN5110NHQZ PTN5110
ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
GND Designer: Drawing Title:
FL
R291 0 PD_I2C_SCL 8MPLUS-BB
4,18 I2C3_SCL_3V3
R292 0 PD_I2C_SDA Drawn by: Page Title:
4,18 I2C3_SDA_3V3
FL USB TYPE-C Power
Approved: Size Document Number Rev
<Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 5 of 21

5 4 3 2 1
 5 4 3 2 1

USB1_OTG_VBUS_F
VDD_5V VDD_3V3

USB3.0 Type-C
R46 C32
1.2M 0.1uF
1% 25V R48

5
R47 0402_CC 1K
1M 4 V+
1% - GND
R5 1
USB1_VBUS_3V3 4
47K
3 U12
For discharge
+ V- SGM8709YN5G
VBUS > 3.7V -> H

2
D D
R51 R52 VBUS < 3.7V -> L
324K 249K
1% 1% NOTE:
VBUS detect >=3.7V is a new requirement from USB Type-C Functional Test Specification since 2019.
This is NOT the power supply! For Non Type-C case, VBUS is usually 5V input, we can remove the comparator circuit and directly connect
receptacle VBUS to 8M Plus USBx_VBUS pin through a 30K 1% serial resistor for cost saving.
USB TYPE-C Port 1 GND

USB1_OTG_VBUS USB1_OTG_VBUS_F TP110

J6
F2 De-bounce PWR SW OFF PWR SW ON Reboot U14
A4 DC5-20V Input 1 2 USB1_OTG_VBUS_F C2 C6 USB1_VBUS_IN R53
DNP
0
VBUS1 A9 C3 VBUS1 VCHG1 D6 R54 0 VBUS_IN
VBUS2 B9 DC5V/3A Output 7A C36 C4 VBUS2 VCHG2 E6
DNP
VBUS3 B4 Rs=7.5 mOhm 4.7uF C5 VBUS3 RCP VCHG3 F6 + C40
VBUS4 VBUS4 VCHG4 ‐ 5A Max ‐
50V D4 G6 Sink Rds=28 mOhm 100uF
A6 USB1_DP_CN CC1210 D5 VBUS5 VCHG5 Vin=2.8~20V, 29V tolerance 50V
DP1 A7 E4 VBUS6 cce8p3x8p3
DN1 E5 VBUS7 D2 DNP
B6 GND F4 VBUS8 RCP V5V_1 E2 Set to 3.4A I2C CTRL GND
DP2 B7 USB1_DN_CN F5 VBUS9 V5V_2 F2 DCDC_5V
DN2 VBUS10 V5V_3

1
G4 G2 ‐ 0.4~3.4A ‐ C41 C42
A2 SSTXP1 VLDO_3V3 G5 VBUS11 V5V_4 D3 Source Rds=38 mOhm 47UF 0.1uF
USB TYPE-C

SSTXP1 A3 SSTXN1 VBUS12 V5V_5 E3 Vin=4.0~5.5V 16V 25V

2
SSTXN1 # Use Always On Power(with VBUS), aviod entering Dead Battery Mode. V5V_6 F3 CC1210 0402_CC
B11 SSRXP1 A1 V5V_7 G3
SSRXP1 B10 SSRXN1 VLDO_3V3 VDD V5V_8
SSRXN1 C45 C46 PD_EN_SRC1 R55 0 EN_SRC1 G1 A6 C43 0.01UF USB1_VBUS_IN GND
B2 SSTXP2 0.1uF 0.1uF EN_SNK1 F1 EN_SRC CAP2 50V 0402_CC
SSTXP2 B3 SSTXN2 25V 25V EN_SNK A3 C44 1000pF
SSTXN2 0402_CC 0402_CC FRS_EN1 B6 Control and VBUS
CAP1 50V 0402_CC
A11 SSRXP2 FRS_EN Gate Driver A5
SSRXP2 A10 SSRXN2 U15 GND GND R56 100K A2
LDO
VLDO VLDO1_3V3
SSRXN2 R57 100K E1 EN
A5 USB1_CC1_CN A1 OVP A2 USB1_CC1 ADDR B5 C47
CC1 B5 USB1_CC2_CN B1 CON_CC1 CC1 B2 USB1_CC2 GND I2C ADDR: 1110010X GND5 B4 4.7uF VDD_3V3
CC2 CON_CC2 CC2 LD1_I2C_SDA C1 GND4 B3 10V
C Rd C
A8 USB1_SBU1 USB1_CC2 C1 C2 LD1_I2C_SCL B1 SDA GND3 B2 CC0603
SBU1 TP24 CON_SBU1 SBU1 SCL I2C GND2
B8 USB1_SBU2 D1 D2 LD1_nINT OD D1 A4
SBU2 TP25 CON_SBU2 SBU2 INT GND1
SH1 A1 D3 A3 R58 0 5% PD1_I2C_SCL
SH1 GND1 SBUEN VSYS 4,10 I2C2_SCL_3V3
SH2 A12 B3 CTRL LOGIC C3 R59 0 5% PD1_I2C_SDA NX20P3483UK R60
SH2 GND2 GND FLAG TP26 4,10 I2C2_SDA_3V3
SH3 B12 GND 10K
SH4 SH3 GND3 B1 NX20P0407 R61 0 5% LD1_I2C_SCL default "UFP" mode
SH4 GND4 R62 0 5% LD1_I2C_SDA
GND USB_LD_nFLT1 R63 0 LD1_nINT
23K20101#LCP-582RF

PD_EN_SNK1 R64 10K EN_SNK1

3
GND
Q2
NX3008NBKW,115
GND PD_EN_SNK 1
Differential Channel Crossbar Switch 5 PD_EN_SNK
R65
1M
1%
True Table:
B1
B2

2
U16 PD_EN_SNK PD_EN_SNK1 EN_SNK1
H X L
L H H
CMF+ESD U18 L L L
SSTXP1 A4 C4 SS_TXP1 C50 0.1uF 25V S_TXP1 8 10 GND GND
B0_P A0_P USB1_TXP 4
SSTXN1 A3 C3 SS_TXN1 C48 0.1uF 25V S_TXN1 7 9
B0_N A0_N USB1_TXN 4
SS_RXP1 2 13
B1_P A1_P USB1_RXP 4
SSTXP2 A2 C2 SS_RXN1 1 14
B1_N A1_N USB1_RXN 4
SSTXN2 A1 C1
SS_TXP2 C52 0.1uF 25V S_TXP2 5 12
PCMF2USB3S SS_TXN2
SS_RXP2
C53 0.1uF 25V S_TXN2 6
15
C0_P
C0_N
C1_P
SEL
XSD
3 TYPEC_EN_B USB1_SS_SEL 4
CC Logic Detection
SSRXP1 A1 C1 SS_RXN2 16 4 VDD_1V8
B
SSRXN1 A2 C2 C1_N VDD 11 PD_EN_SRC1 B
VSS 17 PD_EN_SNK1
SSRXP2 A3 C3 EPAD
SSRXN2 A4 C4 CBTU02043 R38 USB1_OTG_VBUS_F
CMF+ESD 10K C55 C56

16
SEL=H, A‐C

2
0.22uF 2.2uF U17
10V 10V
SEL=L, A-B as default

EN_SRC
EN_SNK1
0402_CC 0402_CC 15 VBUS LDO
U19 VBUS
XSD=H, disable
B1
B2

INTERNAL LDO
PCMF2USB3S
GND GND C51 2.2uF BYPASS1 4
XSD=L, enable as default 10V 0402_CC BYPASS 11 OD USB_LD_nFLT1
FAULT_N
GND 3 1 FRS_EN1
VDD_3V3 VDD VBAT LDO FRS_EN

BYPASS RAIL
9 DEBUG_ACCESS1
DBG_ACC TP27
TYPEC_EN_B R40 0 C54 4.7uF
USB1_TYPEC_EN_B 4
10V CC0603
default "L"
USB1_CC1 13 6 ILIM_5V_VBUS1
CC1 ILIM_5V_VBUS TP29
USB1_CC2 14 5
GND CC2 SLV_ADDR I2C ADDR: 1010000X

TP28 TP30 10 OD GND TP31 TCPC_nINT1 4

12 ALERT_N
B1 VDD_5V VCONN_IN
U75

BAT
C57 0.1uF 8 PD1_I2C_SCL
25V 0402_CC 17 I2C_SCL 7 PD1_I2C_SDA
GND I2C_SDA
CMF+ESD
PTN5110NHQZ PTN5110
USB1_DP_CN A2 C2 USB1_DP
USB1_DP 4
GND
USB1_DN_CN A1 C1 USB1_DN
USB1_DN 4
PCMF1USB3S

A A
Microcontroller Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
USB1_DNU(USB1_ID)
TP45
ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
Designer: Drawing Title:
FL
Caution: 8MPLUS-BB
I.MX8M Plus USBx_ID pins are changed to USBx_DNU, CAN'T be used. Drawn by: Page Title:
FL USB3.0 TYPE-C
Recommend to use common GPIO if USB Identification is needed.
Approved: Size Document Number Rev
<Approver> C SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 6 of 21

5 4 3 2 1
 5 4 3 2 1

USB3.0 HOST
USB2_HOST_VBUS
USB 3.0 HOST
D U21 D
Receptacle, Type A, RA USB_HOST_TXP A1 C1 USB2_H_TXP C59 0.1uF 25V
J7 USB2_TXP 4
USB_HOST_TXN A2 C2 USB2_H_TXN C60 0.1uF 25V USB2_TXN 4
S1 9
1 G1 SSTX+ USB_HOST_RXP A3 C3
VBUS USB2_RXP 4
8 USB_HOST_RXN A4 C4

9
SSTX- USB2_RXN 4

1
2 CMF+ESD

8
D- 7

2
GND_DRAIN VDD_3V3

7
3

3
D+

6
6

4
4 SSRX+

B1
B2
S2 GND 5 PCMF2USB3S
G2 SSRX- R66
1K
USB_TYPE_A GND DNP
GND

GND GND GND B1 USB2_VBUS_3V3 4

U77
Note:
C C
CMF+ESD USB2_VBUS_3V3 is not needed for HOST only port.

USB_HOST_DP A2 C2 USB2_H_DP R298 0 USB2_DP 4,10

USB_HOST_DN A1 C1 USB2_H_DN R299 0 USB2_DN 4,10
PCMF1USB3S

5V Source Load Switch

USB2_HOST_VBUS TP103

D5
A C
DCDC_5V TP46
USB2_DNU(USB2_ID)
MBR140SFT

1
C1

C62
B1
B2

B B
C61 1 2 47UF U22 47UF
GND
16V CC1210 16V
VCP1
VCP2
VCP3

2
CC1210
VDD_3V3 A1 C2
A2 VIN1 VBUS3 D2
VIN2 VBUS2 D1 GND Caution:
R448 10K NX5P_FLT# A4 VBUS1
R68 10K DNP NX5P_FRS C4 FLT I.MX8M Plus USBx_ID pins are changed to USBx_DNU, CAN'T be used.
FO Recommend to use common GPIO if USB Identification is needed.
GND3
GND2
GND1

GND R67 51K 1% NX5P_ILIM A3 ‐ 0.4~3.3A ‐

CAP

ILIM Rds=35 mOhm

EN

Vin=4.0~5.5V
NX5P3363UKZ
B4

B3
D3
C3

D4

Microcontroller Product Group

R302 0 NX5P_EN C64
4 USB2_PWR_EN 6501 William Cannon Drive West
1000pF Austin, TX 78735-8598
FO=0, Slew rate control(Internal 1M PD) 50V
0402_CC This document contains information proprietary to NXP and shall not be used for engineering design,
FO=1, fast turn on procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
RILM, ILIM = 51K, 0.9A GND GND
ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
A EN=0, disable(Internal 1M PD); EN=1, enable Designer: Drawing Title: A
FL
8MPLUS-BB
Drawn by: Page Title:
FL USB3.0 HOST
Approved: Size Document Number Rev
<Approver> A4 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 7 of 21

5 4 3 2 1
 5 4 3 2 1

RGMII 10/100/1000Mbps Ethernet

ETH1_VDD1V0 ETH1_AVDD1V0 ETH1_AVDD3V3

L7 120 Ohm TP34

D D
C84 C85 C86 C339 C87 C88
1.0UF 0.1uF 0.1uF 0.1uF 1.0UF 0.1uF R101 0 DNP
10V 25V 25V 25V 10V 25V VDD_1V8 ETH1_VDDIO
0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC
ETH1_DVDD3V3 ETH1_VDDIO
L5 120 Ohm
GND GND
VDD_3V3 ETH1_DVDD3V3

C89 C90 C91 C92 L6 120 Ohm

4.7uF 0.1uF 4.7uF 0.1uF Ethernet IO Voltage, VDD_3V3 ETH1_AVDD3V3
10V 25V 6.3V 25V default = 1.8 V Internal.
CC0603 0402_CC 0402_CC 0402_CC
ETH1_VDD1V0 ETH1_DVDD1V0
GND GND ETH_CT1
L8 120 Ohm

C14 C93 C94

1.0UF 0.1uF U26 0.22uF

21

29

38

11
40

28
J9

3
8

1
10V 25V # 100‐Ohm differential pairs 10V
0402_CC 0402_CC 0402_CC 14 ETH1_LED1/CFGLDO0

DVDD10

DVDD33

CT
AVDD10_1
AVDD10_2
AVDD10_3

AVDD33_1
AVDD33_2

DVDD_RG
1 ETH1_TRX0_P 14
MDIP0 10/100Mb/s Link / Active
2 ETH1_TRX0_N GND
MDIN0 13 ETH1_10M_100M_Link/Active R104 510
GND 13 GND
4 ETH1_TRX1_P
ENET1_RD0 0 R105 ENET1_RXD0/RXDLY 25 MDIP1 5 ETH1_TRX1_N ETH1_TRX0_P 2 1
4 ENET1_RD0 ENET1_RD1 ENET1_RXD1/TXDLY RXD0/RXDLY MDIN1 ETH1_TRX0_N TRD1+
0 R103 24 3 2
4 ENET1_RD1 ENET1_RD2 ENET1_RXD2/PLLOFF RXD1/TXDLY ETH1_TRX2_P ETH1_TRX1_P TRD1-
0 R102 23 6 4 3
4 ENET1_RD2 ENET1_RD3 ENET1_RXD3/PHYAD0 RXD2/PLLOFF MDIP2 ETH1_TRX2_N ETH1_TRX1_N TRD2+
0 R106 22 7 5 4
4 ENET1_RD3 RXD3/PHYAD0 MDIN2 ETH1_TRX2_P TRD2-
6 5
ENET1_RXC 0 R108 ENET1_RXC/PHYAD1 27 9 ETH1_TRX3_P ETH1_TRX2_N 7 TRD3+ 6
4 ENET1_RXC ENET1_RX_CTL ENET1_RXCTL/PHYAD2 26 RXC/PHYAD1 MDIP3 ETH1_TRX3_N ETH1_TRX3_P TRD3-
0 R107 10 8 7
4 ENET1_RX_CTL RXCTL/PHYAD2 MDIN3 ETH1_TRX3_N TRD4+
9 8
ENET1_TD0 18 32 ETH1_LED0/CFG_EXT TRD4- 12 ETH1_LED2/CFGLDO1
4 ENET1_TD0 TXD0 CFG_EXT/LED0 12
ENET1_TD1 17 33 ETH1_LED1/CFGLDO0 1 Gb/s Link / Active
4 ENET1_TD1 TXD1 CFG_LDO0/LED1
ENET1_TD2 16 34 ETH1_LED2/CFGLDO1

GND
4 ENET1_TD2

SH1
SH2
ENET1_TD3 15 TXD2 CFG_LDO1/LED2 11 ETH1_1GB_Link/Active R109 510
C 4 ENET1_TD3 GND C
TXD3 31 3.3V IO ENET1_nINT 11
ENET1_TXC 20 INT/PME ENET1_nINT 4
4 ENET1_TXC

10

SH1
SH2
ENET1_TX_CTL 19 TXC 13 ETH1_MDC RJ-45
4 ENET1_TX_CTL TXCTL MDC 14 ETH1_MDIO
ETH1_CLK125_OUT 35 MDIO
TP35 CLKOUT 39 R112 2.49K 1%
RSET GND
ENET1_nRST 3.3V IO 12
4 ENET1_nRST PHYRST 30
ETH1_XTALI 36 REG_OUT/LDO_OUT ETH1_VDD1V0
ETH1_XTALO 37 XTAL_IN C95 C96
GND

XTAL_OUT/ EXT_CLK 4.7uF 0.1uF

Y2 6.3V 25V
1 4 0402_CC 0402_CC
41

RTL8211FDI-CG

GND GND GND_CHASSIS

2 3
GND
C97 25MHz C98
22PF 22PF
50V 50V
0402_CC 0402_CC
ETH1_MDC R110 0 ENET1_MDC
ENET1_MDC 4
ETH1_MDIO R111 0 ENET1_MDIO
ENET1_MDIO 4
GND
R424 0 DNP ENET_MDC
ENET_MDC 4,9
R425 0 DNP ENET_MDIO
ENET_MDIO 4,9

ESD protection
ENET1_RXC
U27 U28
ENET1_nRST R113 10K ETH1_LED1/CFGLDO0 ETH1_TRX2_P 10 1 ETH1_TRX2_P ETH1_TRX0_P 10 1 ETH1_TRX0_P
ENET1_nINT R114 10K VDD_3V3
ETH1_LED2/CFGLDO1 ETH1_TRX2_N 9 2 ETH1_TRX2_N ETH1_TRX0_N 9 2 ETH1_TRX0_N
ENET1_MDIO R100 1.5K 1%
B ETH1_VDDIO B
8 8
3 3
EMI Filter Reserved C99 C100 C101
22PF 470PF 470PF ETH1_TRX3_P 7 4 ETH1_TRX3_P ETH1_TRX1_P 7 4 ETH1_TRX1_P
50V 50V 50V
SAI1_RXFS R317 0 ENET1_EVENT_IN 0402_CC 0402_CC 0402_CC GND ETH1_TRX3_N 6 5 ETH1_TRX3_N GND ETH1_TRX1_N 6 5 ETH1_TRX1_N
4 SAI1_RXFS TP42
SAI1_RXC R318 0 ENET1_EVENT_OUT DNP DNP DNP
4 SAI1_RXC TP56
IP4292CZ10-TBR IP4292CZ10-TBR

GND

ETH1_DVDD3V3
Power-on Strapping Pins CFG ETH1_VDDIO

R117 R118 R439 R127 R120

R115 R116 RGMII Power Source CFG_EXT CFG_LDO[1:0] Pull‐up for additional 2ns delay to 4.7K 4.7K 4.7K 4.7K 4.7K
4.7K 4.7K DNP DNP DNP
DNP External 3.3V 1 00 TXC/RXC for data latching. DNP
ENET1_RXD1/TXDLY
ETH1_LED0/CFG_EXT External 2.5V 1 01 ENET1_RXD0/RXDLY

A ETH1_LED2/CFGLDO1 External 1.8V 1 10 ENET1_RXCTL/PHYAD2 A

ETH1_LED1/CFGLDO0 ENET1_RXC/PHYAD1
External 1.5V 1 11 ENET1_RXD3/PHYAD0
Microcontroller Product Group
6501 William Cannon Drive West
R121 R122 R123 Internal 2.5V 0 01 ENET1_RXD2/PLLOFF Austin, TX 78735-8598
4.7K 4.7K 4.7K Pull‐up to disable PLL @ ALDPS mode. This document contains information proprietary to NXP and shall not be used for engineering design,
DNP Internal 1.8V(Default) 0 10 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
R124 R125 R126 R119 R438 R128
Internal 1.5V 0 11 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
PHY Address PHYAD[2:0] DNP Designer: Drawing Title:
FL
2 001 8MPLUS-BB
GND Drawn by: Page Title:
FL Giga Ethernet1
GND Approved: Size Document Number Rev
<Approver> C SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 8 of 21

5 4 3 2 1
 5 4 3 2 1

RGMII 10/100/1000Mbps Ethernet TSN supported

ETH_VDD1V0 ETH_AVDD1V0 ETH_AVDD3V3

L3 120 Ohm TP32

C333 C65 C66 C67 C68 C69

D D
1.0UF 0.1uF 0.1uF 0.1uF 1.0UF 0.1uF R70 0 DNP
10V 25V 25V 25V 10V 25V VDD_1V8 ETH_VDDIO
0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC
ETH_DVDD3V3 ETH_VDDIO
L1 120 Ohm
GND GND
VDD_3V3 ETH_DVDD3V3

C70 C71 C72 C73 L2 120 Ohm

4.7uF 0.1uF 4.7uF 0.1uF Ethernet IO Voltage, VDD_3V3 ETH_AVDD3V3
10V 25V 6.3V 25V default = 1.8 V Internal.
CC0603 0402_CC 0402_CC 0402_CC
ETH_VDD1V0 ETH_DVDD1V0
GND GND ETH_CT
L4 120 Ohm

C334 C74 C75

1.0UF 0.1uF U23 0.22uF

21

29

38

11
40

28
J8

3
8

1
10V 25V # 100‐Ohm differential pairs 10V
0402_CC 0402_CC 0402_CC 14 LED1/CFGLDO0

CT
DVDD10

DVDD33

AVDD10_1
AVDD10_2
AVDD10_3

AVDD33_1
AVDD33_2

DVDD_RG
1 ETH_TRX0_P 14
MDIP0 10/100Mb/s Link / Active
2 ETH_TRX0_N GND
MDIN0 13 10M_100M_Link/Active R74 510
GND 13 GND
4 ETH_TRX1_P
ENET_RD0 0 R73 RXD0/RXDLY 25 MDIP1 5 ETH_TRX1_N ETH_TRX0_P 2 1
4 ENET_RD0 ENET_RD1 RXD0/RXDLY MDIN1 ETH_TRX0_N TRD1+
0 R72 RXD1/TXDLY 24 3 2
4 ENET_RD1 ENET_RD2 RXD1/TXDLY ETH_TRX2_P ETH_TRX1_P TRD1-
0 R71 RXD2/PLLOFF 23 6 4 3
4 ENET_RD2 ENET_RD3 RXD2/PLLOFF MDIP2 ETH_TRX2_N ETH_TRX1_N TRD2+
0 R75 RXD3/PHYAD0 22 7 5 4
4 ENET_RD3 RXD3/PHYAD0 MDIN2 ETH_TRX2_P TRD2-
6 5
ENET_RXC 0 R77 RXC/PHYAD1 27 9 ETH_TRX3_P ETH_TRX2_N 7 TRD3+ 6
4 ENET_RXC ENET_RX_CTL RXC/PHYAD1 MDIP3 ETH_TRX3_N ETH_TRX3_P TRD3-
0 R76 RXCTL/PHYAD2 26 10 8 7
4 ENET_RX_CTL RXCTL/PHYAD2 MDIN3 ETH_TRX3_N TRD4+
9 8
ENET_TD0 18 32 LED0/CFG_EXT TRD4- 12 LED2/CFGLDO1
4 ENET_TD0 TXD0 CFG_EXT/LED0 12
ENET_TD1 17 33 LED1/CFGLDO0 1 Gb/s Link / Active
4 ENET_TD1 TXD1 CFG_LDO0/LED1
ENET_TD2 16 34 LED2/CFGLDO1

GND
4 ENET_TD2

SH1
SH2
ENET_TD3 15 TXD2 CFG_LDO1/LED2 11 1GB_Link/Active R78 510
4 ENET_TD3 TXD3 11 GND
C 31 3.3V IO ENET_nINT C
ENET_TXC 20 INT/PME ENET_nINT 4
4 ENET_TXC

10

SH1
SH2
ENET_TX_CTL 19 TXC 13 R79 0 RJ-45
4 ENET_TX_CTL TXCTL MDC ENET_MDC 4,8
14 R80 0 ENET_MDIO 4,8
DNP ETH_CLK125_OUT 35 MDIO
TP33 CLKOUT 39 R81 2.49K 1% GND
ENET_nRST 3.3V IO 12 RSET
4 ENET_nRST PHYRST 30
ETH_XTALI 36 REG_OUT/LDO_OUT ETH_VDD1V0 R82 1M
ETH_XTALO 37 XTAL_IN C76 C77
GND

XTAL_OUT/ EXT_CLK 4.7uF 0.1uF

Y1 6.3V 25V C78 1000pF
1 4 0402_CC 0402_CC 2KV CC1210
41

RTL8211FDI-CG

GND GND GND_CHASSIS

2 3
GND
C79 25MHz C80
22PF 22PF
50V 50V
0402_CC 0402_CC

GND

ENET_nRST R83 10K

VDD_3V3
ENET_RXC
ESD protection
ENET_nINT R84 10K
LED1/CFGLDO0 U24 U25
ETH_TRX2_P 10 1 ETH_TRX2_P ETH_TRX0_P 10 1 ETH_TRX0_P
B ENET_MDIO B
R85 1.5K 1% LED2/CFGLDO1
ETH_VDDIO ETH_TRX2_N 9 2 ETH_TRX2_N ETH_TRX0_N 9 2 ETH_TRX0_N

8 8
EMI Filter Reserved C81 C82 C83 3 3
22PF 470PF 470PF
50V 50V 50V ETH_TRX3_P 7 4 ETH_TRX3_P ETH_TRX1_P 7 4 ETH_TRX1_P
0402_CC 0402_CC 0402_CC
DNP DNP DNP GND ETH_TRX3_N 6 5 ETH_TRX3_N GND ETH_TRX1_N 6 5 ETH_TRX1_N

IP4292CZ10-TBR IP4292CZ10-TBR

GND

ETH_DVDD3V3 Power-on Strapping Pins CFG ETH_VDDIO

R88 R89 R90 R91

R86 R87 RGMII Power Source CFG_EXT CFG_LDO[1:0] Pull‐up for additional 2ns delay to 4.7K 4.7K 4.7K 4.7K
4.7K 4.7K DNP DNP
DNP External 3.3V 1 00 TXC/RXC for data latching. DNP
RXD1/TXDLY
LED0/CFG_EXT External 2.5V 1 01 RXD0/RXDLY

A LED2/CFGLDO1 External 1.8V 1 10 RXCTL/PHYAD2 A

LED1/CFGLDO0 RXC/PHYAD1 Microcontroller Product Group
External 1.5V 1 11 RXD3/PHYAD0
6501 William Cannon Drive West
R92 R93 R94 Internal 2.5V 0 01 RXD2_PLLOFF Austin, TX 78735-8598
4.7K 4.7K 4.7K Pull‐up to disable PLL @ ALDPS mode. This document contains information proprietary to NXP and shall not be used for engineering design,
DNP Internal 1.8V(Default) 0 10 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
R95 R96 R97 R98 R99
Internal 1.5V 0 11 4.7K 4.7K 4.7K 4.7K 4.7K ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
Designer: Drawing Title:
PHY Address PHYAD[2:0] FL
8MPLUS-BB
GND
1 001 Drawn by: Page Title:
FL Giga Ethernet2_TSN
GND Approved: Size Document Number Rev
<Approver> C SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 9 of 21

5 4 3 2 1
 5 4 3 2 1

VDD_3V3
R129

R130
DNP
0

0
PCIE_DIG1
PCIe3.0 M.2/NGFF
VDD_1V8
C102 C103
1.0UF 0.01UF
10V 50V L9 120 Ohm
D 0402_CC 0402_CC VDD_1V8 D
C104 C105 C106
L10 1.0UF 0.01UF 0.01UF
GND 10V 50V 50V
0402_CC 0402_CC 0402_CC
120 Ohm
C107 C108 C109
1.0UF 0.01UF 0.01UF GND
10V 50V 50V
0402_CC 0402_CC 0402_CC # Standoff for M.2

11
20

16
PCIe MEMS OSC

3
VDD1.8_1
VDD1.8_2

VDDDIG1.8

VDDA1.8

VDDXTAL1.8
GND BH1 BH9 BH10
PCIE_CLKP SMTSO-M25 SMTSO-M25 SMTSO-M25
PCIE_CLKP 4
1 PCIE_CLKN
CPU CLK
X1_25 PCIE_CLKN 4
2 13 R131 0
Y3 X2 DIF0
U29
1 4 14 R132 0
R133 0 8 DIF0 R135 R136
4,6 I2C2_SCL_3V3
R134 0 9 SCLK_3.3 9FGV0241AKLF 0 0
4,6 I2C2_SDA_3V3 SDATA_3.3 17 R137 0 DNP DNP GND GND GND
2 3 Internal PU DIF1
CLK_PD# 22 18 R138 0
TP128 CKPWRGD_PD DIF1 REF_CLKP_CN
C110 25MHz C111 2230 2242 2260
18PF 18PF R139 0 PD 12 M.2 CLK
50V 50V OE0 4 Internal REF_CLKN_CN 3030 3042
SADR/REF1.8 TP36
0402_CC 0402_CC R140 0 PD 19 PD 120K
OE1
C R141 0 23 C
GND SS_EN_TRI
NOTE:
PCIE_DIG1

GNDXTAL
Use external clock as default.

GNDREF
GNDDIG
When using internal clockpopulate R135, R136, remove R131, R132, R137, R138.

GND_1
GND_2
M.2 PWR

GNDA

EPAD
GND
C349 0.1uF GND
TP98 U81 25V 0402_CC
1 6 VEXT_3V3 TP104 VPCIe_3V3

10
21

15

24

25
OE VCC
PCIe_nCLKREQ_3V3 2 4 PCIE_REQ NOTE:
A Y 3 5
This component share PCB package
3 5 2
GND NC When use 9FGV0241 PIN5: GND;PIN7:1.8V 1
C342 C340 R451 C341
74LVC1G125GM VDD_1V8 When use PI6CFGL201BZDIEX PIN5:1.8V;PIN7:3.3V 100UF 0.22uF 22K 0.01UF
GND 16V 50V Q14 50V

4
R144 0 DNP 1210_CC 0402_CC AON7405 0402_CC R35
R147 0 DNP GND TP99 TP100 TP101 TP116 TP117 TP118 TP119 62.0
1. For L1 Sub-states: Uses a bidirectional open-drain clock request (CLKREQ#) ‐ 50A Max ‐
signal for entry and exit this state. R148 0 GND Rds=10 mOhm
SUSCLK_3V3 R452 @ Vgs ‐4.5V

3
2. Clock delay should be smaller than 400ns, according to M.2 spec, PCIe_nRST_3V3 0 @ Id = ‐20A Q15
GND PCIe_nDIS_3V3 Vgs(th) = ‐1.7V ~ ‐2.8V
so CLKREQ# should be connected to OE pins instead of PD pin. Vds(max) = ‐30V
M2_UART_RXD
M2_UART_TXD 1
M2_UART_RTS

M.2 (NGFF) CN VPCIe_3V3

3
TP37 TP38 M2_UART_CTS
Q13 NX3008NBKW,115
J10 NX3008NBKW,115

2
PCIe_nDIS_3V3 R33 1K 1
B B

4,7 USB2_DP R300

DNP
0 M2_USB_DP
1
3 GND1 M.2 / NGFF 3V3_1
2
4 R36 1KDNP
R301 0 M2_USB_DN 5 USB_D+ 3V3_2 6 M2_LED1# VEXT_3V3 R34 C343
4,7 USB2_DN
7 USB_D- KEY E LED1 8 M2_PCM_CLK 1M 0.1uF
DNP M2_PCM_CLK 4

2
M2_SD_CLK 9 GND2 I2S_SCK 10 M2_PCM_SYNC 25V
4 M2_SD_CLK M2_SD_CMD SDIO_CLK I2S_WS M2_PCM_IN M2_PCM_SYNC 4
11 12 o 0402_CC
1.8V

4 M2_SD_CMD M2_SD_DATA0 SDIO_CMD I2S_SD_IN M2_PCM_OUT M2_PCM_IN 4

4 M2_SD_DATA0 13 14 i GND GND
M2_SD_DATA1 SDIO_DATA0 I2S_SD_OUT M2_LED2# M2_PCM_OUT 4
15 16
1.8V

4 M2_SD_DATA1 SDIO_DATA1 LED2

4 M2_SD_DATA2 M2_SD_DATA2 17 18 GND GND
M2_SD_DATA3 19 SDIO_DATA2 GND3 20 o M2_BT_WAKE VPCIe_3V3
4 M2_SD_DATA3 SDIO_DATA3 UART_WAKE
M2_SD_WAKE_HOST o 21 22 o R369 0 M2_UART_RXD
4 M2_SD_WAKE_HOST M2_SD_nRST SDIO_WAKE UART_RXD M2_UART_RXD 4
23
4 M2_SD_nRST SDIO_RST
1.8V

33 32 i R370 0 M2_UART_TXD C112 C113 C114 C115 C116 C117 C118 C119
GND5 UART_TXD M2_UART_RTS M2_UART_TXD 4
4 PCIE_TXP C120 0.22uF 50V 0402_CC 35 34 o R371 0 0.1uF 0.1uF 0.1uF 0.1uF 10uF 100UF 100UF 100UF
PET_P0 UART_CTS M2_UART_CTS M2_UART_RTS 4
4 PCIE_TXN C121 0.22uF 50V 0402_CC 37 36 i R372 0 25V 25V 25V 25V 10v 16V 16V 16V
PET_N0 UART_RTS M2_UART_CTS 4
39 38 R422 0 DNP 0402_CC 0402_CC 0402_CC 0402_CC CC0603 1210_CC 1210_CC 1210_CC
41 GND4 VEN_DEF1 40 R423 0 DNP DNP
4 PCIE_RXP PER_P0 VEN_DEF2 VDD_1V8 VDDIO For some modules
4 PCIE_RXN 43 42
45 PER_N0 VEN_DEF3 44 TP39
REF_CLKP_CN 47 GND6 COEX3 46 o GND
REF_CLKN_CN 49 REFCLK_P0 COEX_RXD 48 i
51 REFCLK_N0 COEX_TXD 50 SUSCLK_3V3 R30 0
GND7 SUSCLK REF_CLK_32K_3V3 4 PMIC_32K_OUT as default
4 PCIe_nCLKREQ_3V3 PCIe_nCLKREQ_3V3 i/o 53 52 i M2_PERST R31 0 PU as default Microcontroller Product Group
CLKREQ0 PERST0 PCIe_nRST_3V3 4
PCIe_nWAKE_3V3 o 55 54 M2_DIS2 R142 0 DNP
4 PCIe_nWAKE_3V3 PEWAKE0 W_DISABLE2 EXP_P0_7 4,18 6501 William Cannon Drive West
57 56 i M2_DIS1 R32 0
GND8 W_DISABLE1 PCIe_nDIS_3V3 4 Austin, TX 78735-8598
59 58 M2_I2C_SDA R152 0
A PET_P1 I2C_DATA I2C2_SDA 4,12,13,14 A
VPCIe_3V3 61 60 M2_I2C_SCL R153 0 This document contains information proprietary to NXP and shall not be used for engineering design,
1.8V

PET_N1 I2C_CLK I2C2_SCL 4,12,13,14

63 62 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
65 GND9 ALERT 64
67 PER_P1 RESERVED 66 ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
69 PER_N1 UIM_SWP/PERST1 68 Designer: Drawing Title:
R149 71 GND10 UIM_PWR_SNK/CLKREQ1 70 M2_LED1# C A R373 1K FL
WLAN Status
10K 73 REFCLK_P1 UIM_PWR_SRC/PEWAKE1 72 VPCIe_3V3 8MPLUS-BB
75 REFCLK_N1 3V3_3 74 D30 LED GREEN Drawn by: Page Title:
Enable internal PU of CPU. GND11 3V3_4
D6 M2_LED2# BT Status C A R374 1K FL M.2 PCIe
A C M2_BT_WAKE
4 M2_BT_WAKE_HOST
CON_MINI CARD_RA D31 LED_ORANGE Approved: Size Document Number Rev
NSR0320 GND GND <Approver> A3 SCH-46370 PDF: SPF-46370 B1
MDT420E01001
Date: Thursday, May 13, 2021 Sheet 10 of 21
5 4 3 2 1
 5 4 3 2 1

D
MicroSD 3.0 D

TP40 J11

4 SD2_nCD 9
DET
Micro-SD
# Push-Push
4 SD2_CMD R154 0 3
R155 0 5 CMD 13
4 SD2_CLK CLK GND4
4 SD2_DATA0 R156 0 7 12
R157 0 8 DAT0 GND3
4 SD2_DATA1 DAT1
4 SD2_DATA2 R158 0 1
R159 0 2 DAT2
4 SD2_DATA3 CD/DAT3 11
4 GND2 10
C VSD_3V3 6 VDD GND1
C
VSS

ESD5B5.0ST1G
2

ESD5B5.0ST1G
C123 C124 GND
TP41

TVS2

TVS1
47uF 0.1uF
10V 25V CONN_SD_CARD 9
0805_CC 0402_CC

1
TP62

4 SD2_RESET_B
GND

B B

Microcontroller Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ___ IUO: _X_ PUBI: ___

Designer: Drawing Title:
FL
A
8MPLUS-BB A

Drawn by: Page Title:

FL MicroSD
Approved: Size Document Number Rev
<Approver> A SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 11 of 21

5 4 3 2 1
 5 4 3 2 1

Camera CSI Interface

Camera 1# Camera 2#
D D

J12 J13
A1 B1 A1 B1
CSI1_CKN A2 A1 B1 B2 CSI1_DN0 CSI2_CKN A2 A1 B1 B2 CSI2_DN0
4 CSI1_CKN A2 B2 CSI1_DN0 4 4 CSI2_CKN A2 B2 CSI2_DN0 4
CSI1_CKP A3 B3 CSI1_DP0 CSI2_CKP A3 B3 CSI2_DP0
4 CSI1_CKP A3 B3 CSI1_DP0 4 4 CSI2_CKP A3 B3 CSI2_DP0 4
A4 B4 A4 B4
A5 A4 B4 B5 CSI1_DN1 A5 A4 B4 B5 CSI2_DN1
VDD_1V8 A5 B5 CSI1_DN1 4 VDD_1V8 A5 B5 CSI2_DN1 4
A6 B6 CSI1_DP1 A6 B6 CSI2_DP1
A6 B6 CSI1_DP1 4 A6 B6 CSI2_DP1 4
A7 B7 A7 B7
A8 A7 B7 B8 CSI_MCLK A8 A7 B7 B8 CSI2_MCLK R26 0 CSI_MCLK
12V TP43
A9 A8 B8 B9 CSI_nRST
CSI_MCLK 4 12V TP44
A9 A8 B8 B9 CSI2_nRST R303 0 CSI_nRST
A9 B9 CSI_nRST 4 A9 B9
R28 0 CSI_SYNC1 A10 B10 CSI1_I2C_SDA R160 0 I2C2_SDA 4,10,13,14 4 CSI2_SYNC
CSI2_SYNC R25 0 CSI_SYNC2 A10 B10 CSI2_I2C_SDA R161 0 I2C3_SDA 4,14,16
4 CSI1_SYNC A10 B10 CSI1_I2C_SCL CSI_PWDN R165 A10 B10 CSI2_I2C_SCL
4 CSI_PWDN PWDN A11 B11 R162 0 I2C2_SCL 4,10,13,14 0 PWDN2 A11 B11 R164 0 I2C3_SCL 4,14,16
A12 A11 B11 B12 CSI2_SYNC R163 0 DNP A12 A11 B11 B12
A13 A12 B12 B13 CSI1_DN2 A13 A12 B12 B13 CSI2_DN2
VEXT_3V3 A14 A13 B13 B14 CSI1_DP2
CSI1_DN2 4
A14 A13 B13 B14 CSI2_DP2
CSI2_DN2 4
A14 B14 CSI1_DP2 4 VEXT_3V3 A14 B14 CSI2_DP2 4
A15 B15 A15 B15
A16 A15 B15 B16 CSI1_DN3 A16 A15 B15 B16 CSI2_DN3
VDD_5V A16 B16 CSI1_DN3 4 A16 B16 CSI2_DN3 4
A17 B17 CSI1_DP3 A17 B17 CSI2_DP3
A17 B17 CSI1_DP3 4 VDD_5V A17 B17 CSI2_DP3 4
A18 B18 A18 B18
A18 B18 A18 B18
1 6 1 6
2 SH1 SH6 5 2 SH1 SH6 5
3 SH2 SH5 4 3 SH2 SH5 4
SH3 SH4 SH3 SH4
CON 2X18 CON 2X18
C C

GND GND
CSI_SYNC1 R29 0 DNP CSI_SYNC2 GND GND

VDD_1V8 VEXT_3V3 VDD_5V SYNC signal comes from one sensor to another. VDD_1V8 VEXT_3V3 VDD_5V
TP111 TP112

C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136
10uF 0.1uF 22uF 0.1uF 22uF 0.1uF 10uF 0.1uF 22uF 0.1uF 22uF 0.1uF
10v 25V 10V 25V 16V 25V 10v 25V 10V 25V 16V 25V
CC0603 0402_CC CC0603 0402_CC 0805_CC 0402_CC CC0603 0402_CC CC0603 0402_CC 0805_CC 0402_CC

GND GND

GND GND
U31
ESD protection CSI1_CKN

CSI1_CKP
10

9
1

2
CSI1_CKN

CSI1_CKP

U32 U33
B CSI1_DN0 10 1 CSI1_DN0 CSI1_DN2 10 1 CSI1_DN2 8 B
GND
3
CSI1_DP0 9 2 CSI1_DP0 CSI1_DP2 9 2 CSI1_DP2
7 4

GND 8 GND 8 6 5
3 3
IP4292CZ10-TBR
CSI1_DN1 7 4 CSI1_DN1 CSI1_DN3 7 4 CSI1_DN3
U34
CSI1_DP1 6 5 CSI1_DP1 CSI1_DP3 6 5 CSI1_DP3 CSI2_CKN 10 1 CSI2_CKN

IP4292CZ10-TBR IP4292CZ10-TBR CSI2_CKP 9 2 CSI2_CKP

GND 8
3

7 4
U35 U36
CSI2_DN0 10 1 CSI2_DN0 CSI2_DN2 10 1 CSI2_DN2 6 5

CSI2_DP0 9 2 CSI2_DP0 CSI2_DP2 9 2 CSI2_DP2 IP4292CZ10-TBR

GND 8 GND 8 Microcontroller Product Group

3 3
6501 William Cannon Drive West
CSI2_DN1 7 4 CSI2_DN1 CSI2_DN3 7 4 CSI2_DN3 Austin, TX 78735-8598
A A
This document contains information proprietary to NXP and shall not be used for engineering design,
CSI2_DP1 6 5 CSI2_DP1 CSI2_DP3 6 5 CSI2_DP3 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

IP4292CZ10-TBR IP4292CZ10-TBR ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
Designer: Drawing Title:
FL
8MPLUS-BB
Drawn by: Page Title:
FL MIPI CSI
Approved: Size Document Number Rev
<Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 12 of 21

5 4 3 2 1
 5 4 3 2 1

J14
DSI Display
D A1 B1 VDD_1V8 VEXT_3V3 VDD_5V D
DSI_CKN A2 A1 B1 B2 DSI_DN0
4 DSI_CKN A2 B2 DSI_DN0 4
DSI_CKP A3 B3 DSI_DP0
4 DSI_CKP A3 B3 DSI_DP0 4
A4 B4
A5 A4 B4 B5 DSI_DN1
VDD_1V8 A5 B5 DSI_DN1 4
A6 B6 DSI_DP1
A6 B6 DSI_DP1 4
A7 B7 C137 C138 C139 C140 C141 C142
A8 A7 B7 B8 DSI_PWM R305 0 10uF 0.1uF 22uF 0.1uF 22uF 0.1uF
12V TP47
A9 A8 B8 B9 DSI_nINT R304 0
DSI_BL_PWM 4
10v 25V 10V 25V 16V 25V
A9 B9 DSI_TS_nINT 4
A10 B10 DSI_TS_SDA R166 0 CC0603 0402_CC CC0603 0402_CC 0805_CC 0402_CC
TP48 A10 B10 I2C2_SDA 4,10,12,14
A11 B11 DSI_TS_SCL R167 0
4 DSI_EN A11 B11 I2C2_SCL 4,10,12,14
A12 B12
A13 A12 B12 B13 DSI_DN2
VEXT_3V3 A14 A13 B13 B14 DSI_DP2
DSI_DN2 4
A14 B14 DSI_DP2 4
A15 B15
A16 A15 B15 B16 DSI_DN3 GND
VDD_5V A16 B16 DSI_DN3 4
A17 B17 DSI_DP3
A17 B17 DSI_DP3 4
A18 B18
A18 B18
1 6 TP113
C 2 SH1 SH6 5 C
3 SH2 SH5 4
SH3 SH4
CON 2X18
GND GND

GND
ESD protection
U37 U38
DSI_DN0 10 1 DSI_DN0 DSI_CKN 10 1 DSI_CKN

DSI_DP0 9 2 DSI_DP0 DSI_CKP 9 2 DSI_CKP

GND 8 GND 8
B 3 3 B

DSI_DN1 7 4 DSI_DN1 7 4

DSI_DP1 6 5 DSI_DP1 6 5

IP4292CZ10-TBR IP4292CZ10-TBR

U39
DSI_DN2 10 1 DSI_DN2

DSI_DP2 9 2 DSI_DP2
Microcontroller Product Group
6501 William Cannon Drive West
GND 8 Austin, TX 78735-8598
3
This document contains information proprietary to NXP and shall not be used for engineering design,
DSI_DN3 7 4 DSI_DN3 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

DSI_DP3 6 5 DSI_DP3 ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
A Designer: Drawing Title: A
FL
IP4292CZ10-TBR 8MPLUS-BB
Drawn by: Page Title:
FL MIPI DSI
Approved: Size Document Number Rev
<Approver> A4 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 13 of 21

5 4 3 2 1
 5 4 3 2 1

LVDS Display
LVDS0 Display LVDS1 Display
J15 J16
D A1 B1 A1 B1 D
LVDS0_CLK_N A2 A1 B1 B2 LVDS0_TX0_N LVDS1_CLK_N A2 A1 B1 B2 LVDS1_TX0_N
4 LVDS0_CLK_N LVDS0_CLK_P A2 B2 LVDS0_TX0_P LVDS0_TX0_N 4 4 LVDS1_CLK_N LVDS1_CLK_P A2 B2 LVDS1_TX0_P LVDS1_TX0_N 4
A3 B3 A3 B3
4 LVDS0_CLK_P A3 B3 LVDS0_TX0_P 4 4 LVDS1_CLK_P A3 B3 LVDS1_TX0_P 4
A4 B4 A4 B4
A5 A4 B4 B5 LVDS0_TX1_N A5 A4 B4 B5 LVDS1_TX1_N
VDD_1V8 A6 A5 B5 B6 LVDS0_TX1_P LVDS0_TX1_N 4 VDD_1V8 A6 A5 B5 B6 LVDS1_TX1_P LVDS1_TX1_N 4
A6 B6 LVDS0_TX1_P 4 A6 B6 LVDS1_TX1_P 4
A7 B7 A7 B7
A8 A7 B7 B8 LVDS_BL_PWM A8 A7 B7 B8 R168 0 LVDS_BL_PWM
PER_12V A8 B8 LVDS_BL_PWM 4 PER_12V A8 B8
A9 B9 LVDS_TS_nINT A9 B9 R169 0 LVDS_TS_nINT
A9 B9 LVDS_TS_nINT 4 A9 B9
A10 B10 LVDS0_TS_SDA R170 0 A10 B10 LVDS1_TS_SDA R171 0
TP49 A10 B10 I2C2_SDA 4,10,12,13 TP50 A10 B10 I2C3_SDA 4,12,16
A11 B11 LVDS0_TS_SCL R172 0 LVDS_EN A11 B11 LVDS1_TS_SCL R173 0
4 LVDS_EN A11 B11 I2C2_SCL 4,10,12,13 A11 B11 I2C3_SCL 4,12,16
A12 B12 A12 B12
A13 A12 B12 B13 LVDS0_TX2_N A13 A12 B12 B13 LVDS1_TX2_N
VEXT_3V3 A14 A13 B13 B14 LVDS0_TX2_P LVDS0_TX2_N 4 VEXT_3V3 A14 A13 B13 B14 LVDS1_TX2_P LVDS1_TX2_N 4
A14 B14 LVDS0_TX2_P 4 A14 B14 LVDS1_TX2_P 4
A15 B15 A15 B15
A16 A15 B15 B16 LVDS0_TX3_N A16 A15 B15 B16 LVDS1_TX3_N
VDD_5V A17 A16 B16 B17 LVDS0_TX3_P LVDS0_TX3_N 4 VDD_5V A17 A16 B16 B17 LVDS1_TX3_P LVDS1_TX3_N 4
A17 B17 LVDS0_TX3_P 4 A17 B17 LVDS1_TX3_P 4
A18 B18 A18 B18
A18 B18 A18 B18
1 6 1 6
2 SH1 SH6 5 2 SH1 SH6 5
3 SH2 SH5 4 3 SH2 SH5 4
SH3 SH4 SH3 SH4
CON 2X18 CON 2X18
GND GND GND GND

C VDD_1V8 VEXT_3V3 VDD_5V PER_12V TP115 C

VDD_1V8 VEXT_3V3 VDD_5V PER_12V TP114

C147 C148 C155 C149 C150 C156 + C151

C152 C143 C144 C153 C154 C145 + C146 22uF 0.1uF 22uF 0.1uF 22uF 0.1uF 100uF
10uF 0.1uF 22uF 0.1uF 22uF 0.1uF 100uF 10V 25V 10V 25V 16V 25V 35V
10v 25V 10V 25V 16V 25V 35V CC0603 0402_CC CC0603 0402_CC 0805_CC 0402_CC cce6p8x6p8
CC0603 0402_CC CC0603 0402_CC 0805_CC 0402_CC cce6p8x6p8

GND GND
GND GND

U40
LVDS0_CLK_N 10 1 LVDS0_CLK_N

LVDS0_CLK_P 9 2 LVDS0_CLK_P

8
ESD protection GND
3

7 4
B B
U41 U42 6 5
LVDS0_TX0_N 10 1 LVDS0_TX0_N LVDS0_TX2_N 10 1 LVDS0_TX2_N
IP4292CZ10-TBR
LVDS0_TX0_P 9 2 LVDS0_TX0_P LVDS0_TX2_P 9 2 LVDS0_TX2_P

GND 8 GND 8 U43

3 3 LVDS1_CLK_N 10 1 LVDS1_CLK_N

LVDS0_TX1_N 7 4 LVDS0_TX1_N LVDS0_TX3_N 7 4 LVDS0_TX3_N LVDS1_CLK_P 9 2 LVDS1_CLK_P

LVDS0_TX1_P 6 5 LVDS0_TX1_P LVDS0_TX3_P 6 5 LVDS0_TX3_P

GND 8
IP4292CZ10-TBR IP4292CZ10-TBR 3

7 4

6 5

IP4292CZ10-TBR
U44 U45
LVDS1_TX0_N 10 1 LVDS1_TX0_N LVDS1_TX2_N 10 1 LVDS1_TX2_N

LVDS1_TX0_P 9 2 LVDS1_TX0_P LVDS1_TX2_P 9 2 LVDS1_TX2_P

Microcontroller Product Group
8 8 6501 William Cannon Drive West
GND GND Austin, TX 78735-8598
A
3 3 A
This document contains information proprietary to NXP and shall not be used for engineering design,
LVDS1_TX1_N 7 4 LVDS1_TX1_N LVDS1_TX3_N 7 4 LVDS1_TX3_N procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

LVDS1_TX1_P 6 5 LVDS1_TX1_P LVDS1_TX3_P 6 5 LVDS1_TX3_P ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
Designer: Drawing Title:
IP4292CZ10-TBR IP4292CZ10-TBR FL
8MPLUS-BB
Drawn by: Page Title:
FL LVDS DISPLAY
Approved: Size Document Number Rev
<Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 14 of 21

5 4 3 2 1
 5 4 3 2 1

HDMI2.0 Display with eARC RX

D U47 D
PCMF2HDMI2S
4 HDMI_TXP2
HDMI_TXP2 C1 A1 HDMI_TXP2_CN DCDC_5V TP125 DCDC_5V_CN VDD_3V3 VDD_3V3_CN
HDMI_TXN2 C2 A2 HDMI_TXN2_CN
4 HDMI_TXN2
U71 D9
HDMI_TXP1 C3 A3 HDMI_TXP1_CN A C
4 HDMI_TXP1
HDMI_TXN1 C4 A4 HDMI_TXN1_CN 3 2
4 HDMI_TXN1

HDMI TYPEA
IN OUT
CMF+ESD BAT54HT1

GND
C157 C158
Use two channel or single channel PCMF part for better TDR performance 1uF 1uF
16V AP2331SA-7 16V

1
0402_CC 0402_CC R1

B2
B1
0 R174 J17
27K
GND GND GND 1%
TYPE A
GND Benefit of using load switch HDMI_TXP2_CN HDMI_D2P 1 D2P
U46 for HDMI 5V Source: 2 G_D2
PCMF2HDMI2S HDMI_TXN2_CN HDMI_D2N 3
HDMI_TXP0 C1 A1 HDMI_TXP0_CN
Short circuit protection; HDMI_TXP1_CN 4
D2N
HDMI_D1P
4 HDMI_TXP0
HDMI_TXN0 C2 A2 HDMI_TXN0_CN Reverse current blocking; 5
D1P

4 HDMI_TXN0 Fast response. G_D1

HDMI_TXN1_CN HDMI_D1N 6 D1N
HDMI_TXCP C3 A3 HDMI_CLKP_CN HDMI_TXP0_CN HDMI_D0P 7
4 HDMI_TXCP D0P
HDMI_TXCN C4 A4 HDMI_CLKN_CN 8
4 HDMI_TXCN G_D0
CMF+ESD HDMI_TXN0_CN HDMI_D0N 9 D0N
HDMI_CLKP_CN HDMI_CLKP 10 CLKP
11 G_CLK
HDMI_CLKN_CN HDMI_CLKN 12 CLKN
HDMI_CEC_CN HDMI_CEC 13

B2
B1
CEC
C HDMI_Utility_CN HDMI_Utility 14 Utility
C
HDMI_DDC_SCL_CN HDMI_DDC_SCL 15 SCL
HDMI_DDC_SDA_CN HDMI_DDC_SDA 16 SDA
TP87 TP88 TP94 TP95 17 G_DDC
GND HDMI_5V_CN HDMI_5V 18 +5V
U30 HDMI_HPD_CN HPD(2.0~5.3V) 19 HPD
EARC_P_UTIL C161 1uF HDMI_Utility/eARC+ C1 A1 HDMI_Utility_CN
4 EARC_P_UTIL
16V 0402_CC
EARC_N_HPD C162 1uF HDMI_HPD/eARC- C2 A2 HDMI_HPD_CN GND
4 EARC_N_HPD

1
ESD5B5.0ST1G

ESD5B5.0ST1G

ESD5B5.0ST1G

ESD5B5.0ST1G
16V 0402_CC
HDMI_HPD_5V R175 1.2K 1% G1

D10

D11

D12

D13
CMF+ESD G2
G3
R176 G4
47K

2
1% PCMF1HDMI2S CON HDMI 1X19
B1

GND GND

GND

B Level shifter VDD_1V8 B

VDD_1V8 VDD_1V8 DCDC_5V_CN DCDC_5V_CN

VDD_1V8
C345
0.1uF
25V
C168 C169 C170 C171 0402_CC U79
1.0UF 0.1uF 1uF 0.1uF 6 1
VCC OE

1
10V 25V 16V 25V R186 Q5 GND
R177 R178 0402_CC 0402_CC 0402_CC 0402_CC 100K HDMI_HPD 4 2 HDMI_HPD_5V
4 HDMI_HPD Y A
10K 10K R179 R180 2.0V~5.3V
U48 1.5K 1.5K 5 3
GND GND 1% 1% HDMI_CEC 2 3 HDMI_CEC_CN NC GND
4 HDMI_CEC
1 8 74LVC1G125GM
VCCA VCCB
R181 0 2 7 HDMI_DDC_SCL_CN NX3008NBKW,115
4 HDMI_DDC_SCL A1 B1
R183 0 3 6 HDMI_DDC_SDA_CN D32 GND
4 HDMI_DDC_SDA A2 B2 A C
4 5 R185 10K
GND EN DCDC_5V_CN BAT54HT1

PCA9509ADP
HDMI_DDC_SCL GND Microcontroller Product Group
TP89
HDMI_DDC_SDA
TP90 6501 William Cannon Drive West
Austin, TX 78735-8598
A A
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ___ IUO: _X_ PUBI: ___

Designer: Drawing Title:
FL
8MPLUS-BB
Drawn by: Page Title:
FL HDMI Display
Approved: Size Document Number Rev
<Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 15 of 21

5 4 3 2 1
 5 4 3 2 1

Audio CODEC HP JACK

AUD_3V3

D R187 D
DCVDD 1.71V - 3.6V 100K
DBVDD 1.71V - 3.6V
AVDD 2.70V - 3.6V MICBIAS
AUD_3V3 AUD_5V VDD_1V8 SPKVDD 2.70V - 5.5V
C174 HP_JD R189 0 HP_J_D
U50 4.7uF
8 9 10V # HP_JD:
10 DCVDD DGND 28 CC0603
DBVDD AGND GND
LOW : REMOVE
26 24
21 SPKVDD1 SPKGND1 20 GND HIGH : PLUG
GND
32 SPKVDD2 SPKGND2 GND
AVDD

4 AUD_nINT R188 0 15 27 C175 4.7uF GND R190 C176

R192 0 13 ADCLRC/GPIO1 VMID 1 6.3V 0402_CC 10K L11 220PF
4 SAI3_TXFS DACLRC MICBIAS
4 SAI3_TXC R191 0 12 120 Ohm 50V
R194 0 o 16 BCLK 0402_CC J18
4 SAI3_RXD ADCDAT
R193 0 i 14 31 HP_L C177 22uF HPL HP_J_L
4 SAI3_TXD DACDAT HP_L
4 SAI3_MCLK R195 0 11 10V CC0603 2
MCLK

AUD_JACK
29 HP_R C178 22uF HPR HP_J_R HP_J_R 3
HP_R 10V CC0603 6
HP_MIC1P 2 30 5
LINPUT3/JD2 OUT3 TP51 120 Ohm HP_J_L
3 R196 C179 4
HP_MIC1N 4 LINPUT2 10K L12 220PF HP_J_MIC 1
HP_JD 7 LINPUT1 25 SPK_LP 50V
RINPUT3/JD3 SPK_LP SPK_LN

ESD5B5.0ST1G

ESD5B5.0ST1G

ESD5B5.0ST1G

ESD5B5.0ST1G
6 23 0402_CC KJ366EYS
5 RINPUT2 SPK_LN
RINPUT1 22 SPK_RP
C SPK_RP 19 SPK_RN GND GND C
R198 0 AUD_SCL 17 SPK_RN
4,12,14 I2C3_SCL SCLK 3.5mm POLE

2
R197 0 AUD_SDA 18
4,12,14 I2C3_SDA SDIN 33 GND
GND_PADDLE GND
HSL HSR GND MIC
MICBIAS R199 0
# I2C ADDR: 1A(0011010x) WM8960 CTIA Standard
GND

1
R200 C182

TVS3

TVS4

TVS5

TVS6
C181 1K 0.1uF
15PF 25V
16V 0402_CC

HP_MIC1N C183 0.1uF

VDD_1V8 AUD_5V AUD_3V3 25V 0402_CC GND

R201
1K L13 GND
120 Ohm
C184 C185 C186 C187 C188 C189 C190
4.7uF 0.1uF 0.1uF 4.7uF 0.1uF 10uF 0.1uF HP_MIC1P C191 0.1uF HP_MIC_P
6.3V 25V 25V 10V 25V 10V 25V 25V 0402_CC
0402_CC 0402_CC 0402_CC CC0603 0402_CC CC0603 0402_CC
C192 C193
15PF 15PF
GND GND

GND
GND 16V
0402_CC
HP MIC 16V
0402_CC

B B
GND GND
C194
15PF
16V
SPK_RP R202 0 0402_CC SPKOUTRP VDD_3V3 AUD_3V3
C195
15PF
16V
Speaker Power Control L14 120 Ohm
SPK_RN R203 0 0402_CC SPKOUTRN VDD_5V AUD_5V
Q6
C196
15PF 2 3
16V
0402_CC C197 R204 C15
0.22uF AO7401 4.7uF
1

CON1 50V 47K 10V

GND SPKOUTRP 1 0402_CC CC0603

Speaker GND
SPKOUTRN
SPKOUTLP
SPKOUTLN
2
3
4 R205
10K
GND

HDR 1X4
C198 DNP
15PF Microcontroller Product Group
16V
3

SPK_LP R206 0 0402_CC SPKOUTLP Q7 6501 William Cannon Drive West

Austin, TX 78735-8598
A A
C199 This document contains information proprietary to NXP and shall not be used for engineering design,
15PF R207 0 1 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
4 AUD_PWR_EN
16V
SPK_LN R208 0 0402_CC SPKOUTLN ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
R209 C200 NX3008NBKW,115 Designer: Drawing Title:
C201 100K 0.1uF FL
Note: 8MPLUS-BB
2

15PF 25V
16V 0402_CC 1. Default low to reduce pop noise Drawn by: Page Title:
0402_CC 2. High enable for speaker output FL Audio CODEC
Approved: Size Document Number Rev
GND GND <Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 16 of 21

5 4 3 2 1
 5 4 3 2 1

CAN Bus
D Dual CAN FD DB9 Female D

J19
M1
VDD_5V VDD_3V3
C202 C203 C204 C205 1
0.1uF 1.0UF 1.0UF 0.1uF 6
25V 10V 10V 25V CAN1_L 2
0402_CC 0402_CC 0402_CC 0402_CC R212 R426 CAN1_H 7

11
3
U51 10K 10K 3

1
8

VCC

VIO
GND GND D14 4
CAN1_RX_3V3 4 13 CAN1H 9
CAN1_TX_3V3 1 RXD1 CANH1 12 CAN1L 5
TXD1 CANL1 PESD2IVN24-T
10 CAN2H M2
CAN2_RX_3V3 7 CANH2 9 CAN2L

3
CAN2_TX_3V3 6 RXD2 CANL2 DB9
TXD2 14 CAN1_STBY_3V3
STB1 CAN1_STBY_3V3 4

GNDA
GNDB
8 CAN2_STBY_3V3
STB2 CAN2_STBY_3V3 4
GND GND

TJA1048T

2
5
GND_CHASSIS
C C

GND
GND GND

C206 C214
56PF 56PF

CAN1H 1 L19 2 R210 62.0 1%

50V
0402_CC
CAN1_H
CAN2H 1 L20 2 R214 62.0 1%
50V
0402_CC
CAN2_H DB9 Female
C207 0.01UF GND C215 0.01UF GND J20
CAN1L 4 3 R211 62.0 1% 50V 0402_CC CAN2L 4 3 R215 62.0 1% 50V 0402_CC M1
CAN1_L CAN2_L
100uH 100uH
1
6
C208 C216 CAN2_L 2
56PF 56PF CAN2_H 7
50V 50V 3

1
0402_CC 0402_CC 8
B D15 4 B
GND GND 9

Level shifter
5
PESD2IVN24-T
M2

3
DB9
VDD_1V8 VDD_3V3
C217 C218 C219 C220 GND GND
1.0UF 0.01UF 1.0UF 0.01UF
10V 50V 10V 50V GND_CHASSIS
0402_CC 0402_CC 0402_CC 0402_CC
U53
GND 3 2 GND
VCCA VCCB
R216 10K 4
VDD_1V8 R217 10K 5 1DIR
1 2DIR Microcontroller Product Group
R218 10K 16 1OE 6501 William Cannon Drive West
GND 2OE Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
CAN1_TX 6 15 CAN1_TX_3V3 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
4 CAN1_TX 1A1 1B1
A
4 CAN2_TX
CAN2_TX
CAN1_RX
7
8 1A2 1B2
14
13
CAN2_TX_3V3
CAN1_RX_3V3
DIR=H, A ‐> B ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
A

4 CAN1_RX 2A1 2B1

4 CAN2_RX
CAN2_RX 9
2A2 2B2
12 CAN2_RX_3V3 DIR=L, A <‐ B Designer:
FL
Drawing Title:

10 11 8MPLUS-BB
GND1 GND2 Drawn by: Page Title:
74AVC4T245GU FL Audio CODEC
TP106 TP107 TP108 TP109
GND GND Approved: Size Document Number Rev
<Approver> B SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 17 of 21

5 4 3 2 1
 5 4 3 2 1

Expansion Connectors
D
EXP CN I2C CN D

VEXP_3V3 VEXP_5V VEXT_3V3 VEXP_3V3

L25 VEXT_3V3
J21 1 2
3.3V 1 2 5V
I2C3_SDA_3V3 SDA.1 3 4 5V 120 OHM C223 1.0UF
4,5 I2C3_SDA_3V3 GND
I2C3_SCL_3V3 SCL.1 5 6 GND C224 10V 0402_CC
4,5 I2C3_SCL_3V3
UART3_CTS_3V3 GPIO.7 7 8 TXD UART3_TXD_3V3 22uF J22
GND 9 10 RXD UART3_RXD_3V3 10V 1 2
UART3_RTS_3V3 GPIO.0 11 12 GPIO.1 CC0603 R221 0 3 4
EXP_P1_0 4 4 I2C5_SCL_3V3
4 EXP_P1_1
GPIO.2 13 14 GND
4 I2C5_SDA_3V3 R222 0 5 6
4 EXP_P1_2
GPIO.3 15 16 GPIO.4
EXP_P1_3 4 7 8
3.3V 17 18 GPIO.5
EXP_P1_4 4 GND
ECSPI2_MOSI_3V3 MOSI 19 20 GND SSM-104-L-DV
ECSPI2_MISO_3V3 MISO 21 22 GPIO.6
EXP_P0_7 4,10
VDD_5V VEXP_5V
ECSPI2_SCLK_3V3 SCLK 23 24 CE0 ECSPI2_SS0_3V3
GND 25 26 CE1 L26
SDA.0 27 28 SCL.0 1 2 GND
4 EXP_P1_5
GPIO.21 29 30 GND
GPIO.22 31 32 GPIO.26 PWM4_3V3 120 OHM C226
4 EXP_P1_6
4 EXP_P1_7
GPIO.23 33 34 GND 22uF
PDM_STREAM_3 GPIO.24 35 36 GPIO.27 PDM_STREAM_2 16V
PDM_STREAM_1 GPIO.25 37 38 GPIO.28 PDM_STREAM_0 0805_CC
GND 39 40 GPIO.29 PDM_CLK

C TSM-120-01-F-DV-A GND C

GND GND

Level Shifter
VDD_1V8 VEXP_3V3 VDD_1V8 VEXP_3V3
FAN Power Control
C232 C233 C234 C235 VDD_5V FAN_5V FAN_5V
0.1uF 0.1uF 0.1uF 0.1uF
25V 25V 25V 25V Q16
TP82TP83TP84TP85 0402_CC 0402_CC TP86 0402_CC 0402_CC J27
11

11
1

1
U57 U58 2 3 1
GND GND GND GND 2
VCCA

VCCB

VCCA

VCCB
C348
SAI5_RXD0 R293 0 2 10 PDM_STREAM_0 SAI5_RXC R297 0 2 10 PDM_CLK R455 AO7401 4.7uF HDR 1X2
4 SAI5_RXD0 4 SAI5_RXC

1
SAI5_RXD1 R294 0 3 A1 B1 9 PDM_STREAM_1 3 A1 B1 9 10K 10V DNP
4 SAI5_RXD1 A2 B2 A2 B2
SAI5_RXD2 R295 0 4 8 PDM_STREAM_2 4 8 CC0603
4 SAI5_RXD2 A3 B3 A3 B3
SAI5_RXD3 R296 0 5 7 PDM_STREAM_3 SAI5_RXFS 5 7 PWM4_3V3
4 SAI5_RXD3 A4 B4 4 SAI5_RXFS A4 B4 GND GND
B R225 10K 12 R226 10K 12 B
GND

GND
VDD_1V8 OE VDD_1V8 OE

3
Q17
6

6
NTB0104GU12 NTB0104GU12 R456 0 1
4 FAN_EN

Note: GND Note: GND R457 NX3008NBKW,115

NTB part has strict requirement for capacitive load: <70pF NTB part has strict requirement for capacitive load: <70pF 10K

2
Just for backup.

VDD_1V8 VEXP_3V3 VDD_1V8 VEXP_3V3 GND GND

C228 C229 C230 C231

0.1uF 0.1uF 0.1uF 0.1uF
25V 25V 25V 25V
0402_CC 0402_CC 0402_CC 0402_CC
11

11
1

U55 U56
GND GND GND GND
VCCA

VCCB

VCCA

VCCB

ECSPI2_SS0 2 10 ECSPI2_SS0_3V3 UART3_TXD 2 10 UART3_TXD_3V3 Microcontroller Product Group

4 ECSPI2_SS0 A1 B1 4 UART3_TXD A1 B1
ECSPI2_MOSI 3 9 ECSPI2_MOSI_3V3 UART3_RXD 3 9 UART3_RXD_3V3
4 ECSPI2_MOSI A2 B2 4 UART3_RXD A2 B2 6501 William Cannon Drive West
ECSPI2_MISO 4 8 ECSPI2_MISO_3V3 UART3_CTS 4 8 UART3_CTS_3V3
4 ECSPI2_MISO A3 B3 4 UART3_CTS A3 B3 Austin, TX 78735-8598
ECSPI2_SCLK 5 7 ECSPI2_SCLK_3V3 UART3_RTS 5 7 UART3_RTS_3V3
A 4 ECSPI2_SCLK A4 B4 4 UART3_RTS A4 B4 A
This document contains information proprietary to NXP and shall not be used for engineering design,
GND

R223 10K 12 R224 10K 12 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
GND

VDD_1V8 OE VDD_1V8 OE
NTS0104GU12 ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
6

Designer: Drawing Title:

6

NTB0104GU12 FL
8MPLUS-BB
GND Drawn by: Page Title:
GND FL Expansion CN
Note: Note:
NTB part has strict requirement for capacitive load: <70pF NTS part has strict requirement for capacitive load: <150pF; Approved: Size Document Number Rev
Use NTS part instead of NTB part for UART, will have <Approver> A3 SCH-46370 PDF: SPF-46370 B1
better capacitive load support w/o performance degradation.
Date: Thursday, May 13, 2021 Sheet 18 of 21
5 4 3 2 1
 5 4 3 2 1

UART-USB Remote Debug VDD_1V8

C328 C329
UART Level Shifter
C330 C331
VCC_FT_3V3
1.0UF 0.1uF 1.0UF 0.1uF
VCC_FT_3V3 10V 25V 10V 25V
VCC_FT_3V3 VCC_FT_1V8 0402_CC 0402_CC 0402_CC 0402_CC

Power L21 GND 3

U61
VCCA VCCB
2 GND

C245 C246 C296 C297 C298 C299 C300 R429 10K 4

120 Ohm 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 0.1uF 0.1uF VDD_1V8 R430 10K 5 1DIR
GND 2DIR
C243 C244 C241 25V 25V 25V 25V 6.3V 25V 25V 1
VBUS_USB_DBG TP126 VCC_FT_3V3 4.7uF 0.1uF 0.1uF VCC_FT_1V8 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 16 1OE
L15 U59 10V 25V 25V POR_B_INVERT R435 0 2OE
CC0603 0402_CC 0402_CC
D 1 5 VCC_FT_3V3 GND GND 4 UART2_TXD R230 0 6 15 FTDIC_RX D
120 Ohm VIN VOUT L22 GND # A53 Debug R231 0 7 1A1 1B1 14 FTDID_RX
4 UART4_TXD 1A2 1B2

2
3 GND R232 0 8 13 FTDIC_TX
EN 4 UART2_RXD
C236 C237 C238 C239 VCC_FT_3V3 # M7 Debug 4 UART4_RXD R233 0 9 2A1 2B1 12 FTDID_TX
TVS7 1uF 0.1uF 1.0UF 2 4 4.7uF 120 Ohm 2A2 2B2
ESD5B5.0ST1G 16V 25V 10V GND BP 10V C242 10 11
0402_CC 0402_CC 0402_CC C240 CC0603 0.1uF GND1 GND2 DIR=H, A ‐> B
RT9193 -33PB 0.22uF 25V 74AVC4T245GU DIR=L, A <‐ B
1
50V 0402_CC UART2_TXD
TP57
0402_CC R333 R334 UART2_RXD
TP129 TP130 TP58
GND GND GND GND GND GND 1.5K 1.5K GND GND
GND 1% 1% UART4_TXD OE=H, disable, A/B High-Z as default

12
37
64

20
31
42
56
TP60

4
9
U60 UART4_RXD
J23 FT_SCL
TP61 OE=L, enable after POR_B de‐assert to high
S3

S1

VPHY
VPLL

VCORE1
VCORE2
VCORE3

VCCIO1
VCCIO2
VCCIO3
VCCIO4
USB205FB-C1013223 VCC_FT_1V8 REG_FT_1V8 16 FTA_TCK FT_SDA VDD_1V8
50 ADBUS0 17 FTA_TDI
1 VBUS_DBG VREGIN ADBUS1 18 FTA_TDO
D- VBUS

U62 PCMF1USB3S L24 120 Ohm 49 ADBUS2 19 FTA_TMS JTAG

2 USB_DBG_DN A2 C2 VREGOUT ADBUS3 21 FT_RESET_B
FT_USB_DN R327 22 ST_FT_USB_DN DNP C295 C294 ADBUS4 22 FT_SYS_nRST C346

CMF+ESD
3 USB_DBG_DP B1 4.7uF 0.1uF ADBUS5 23 FT_IO_nRST 0.1uF VDD_1V8
D+

FT_USB_DP R328 22 ST_FT_USB_DP 6.3V 25V ADBUS6 24 FT_ONOFF_B 25V

4 A1 C1 0402_CC 0402_CC ADBUS7 0402_CC
ID

6
ST_FT_USB_DN 7 26 FT_SCL U78
5 ST_FT_USB_DP 8 USBDM BDBUS0 27 SDA_TX FT_SDA GND
IO/I2C Expansion

VCC
USBDP BDBUS1
G

28 SDA_RX R431
GND GND BDBUS2 29 FT_IO_nINT POR_B R238 0 2
BDBUS3 A 10K
30 FT_GPIO1
S4

S2

BDBUS4 32 FT_GPIO2 VCC_FT_3V3 1

GND
R240 10K FT_EECS 63 BDBUS5 33 FT_GPIO3 5 NC1 4 POR_B_INVERT
VCC_FT_3V3 62 EECS BDBUS6 34 FT_GPIO4 NC2 Y
GND R236 10K FT_EEDATA 61 EECLK BDBUS7 LED_ORANGE

3
GND EEDATA 38 FTDIC_TX RX D16 C A R235 1K 74LVC1G04GM
FT_OSCI CDBUS0 39 FTDIC_RX TX D17 C A R237 1K
CDBUS1 40 # A53 Debug
X1 FT_OSCO CDBUS2 41 LED GREEN
12 MHz FT_OSCI 2 CDBUS3 43 GND
FT_OSCO 3 OSCI CDBUS4 44 VCC_FT_3V3
1 3 OSCO CDBUS5 45
CDBUS6 46
VCC_FT_3V3 U74 VCC_FT_1V8 TP127 CDBUS7 LED_ORANGE
C252 C253 48 FTDID_TX RX D20 C A R242 1K

4
27 PF 27 PF DDBUS0 52 FTDID_RX TX D21 C A R241 1K
1 5 L23 120 Ohm 16V 16V R329 10K 14 DDBUS1 53
# M7 Debug
VCC_FT_3V3
C324
3
VIN

EN
VOUT

C325
0402_CC 0402_CC
6
RESET

REF
DDBUS2
DDBUS3
DDBUS4
DDBUS5
54
55
57
LED GREEN TP124
Misc Remote Control
1.0UF 2 4 4.7uF 58
10V GND BP 6.3V GND C251 R330 DDBUS6 59
0402_CC C326 0402_CC 0.1uF 12K DDBUS7 "0" normal mode VCC_FT_1V8
RT9193-18GB 0.22uF 25V 13 60 FT_PW REN
TEST PWREN TP93

AGND

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
50V 0402_CC 36 FT_SUSPEND_B GND
SUSPEND TP96
0402_CC C335 0.1uF GND
"0" when USB in suspend mode 25V 0402_CC
GND GND GND GND GND GND GND FT4232H

10

1
5
11
15
25
35
47
51
U66
REMOTE_SEL R458 0 1 6
OE VCC
C FT_SYS_nRST 2 4 R436 0 SYS_nRST C
TP133 A Y
3 5 R437 0 DNP W DOG_B
GND NC W DOG_B 4
74AUP1G126GM
GND
OE=H, EN
GND
OE=L, DIS Default

VCC_FT_1V8

JTAG Interface JTAG Remote Control VCC_FT_1V8

R410 C327 0.1uF

JTAG Connector 10K 25V 0402_CC
GND
VDD_1V8 CPU DNP
U67
VCC_FT_3V3 VCC_FT_1V8 VDD_1V8 FT_SUSPEND_B R408 0 1 6
C309 C310 Remote Debug OE VCC
C307 C308 C305 C306 1.0UF 0.01UF FT_REMOTE_SEL 2 4 R39 0 REMOTE_SEL
TP134
A

1.0UF 0.01UF 1.0UF 0.01UF 10V 50V A Y

D22 10V 50V 10V 50V 0402_CC 0402_CC 3 5
0402_CC 0402_CC 0402_CC 0402_CC R409 GND NC
NSR0320
10K 74AUP1G126GM OE=H, EN R351
GND U8 10K
OE=L, DIS Default
C

GND GND 14
VDD GND
11
1

R243 R244 R245 R246 U7 CON_JTAG_TCK 16 0

10K 10K 10K 100 S1A 2 JTAG_TCK
VCCA

VCCB

1% FTA_TCK 2 10 LVL_SHF_TCK 1 D1 JTAG_TCK 4 GND GND

A1 YB1 CON_JTAG_TDI 3 S1B
J24 FTA_TDI 3 9 S2A 5 JTAG_TDI
CON_JTAG_TMS 2 1 VTREF A2 YB2 LVL_SHF_TDI 4 D2 JTAG_TDI 4
TMS
CON_JTAG_TCK 4 3 GND FTA_TMS 4 8 CON_JTAG_TMS 9 S2B
TCK
CON_JTAG_TDO 6 5 GND A3 YB3 S3A 7 JTAG_TMS
TDO
CON_JTAG_TDI 8 7 R247 0 DNP FTA_TDO 5 7 LVL_SHF_TMS 8 D3 JTAG_TMS 4
TDI
JTAG_RESET 10 9 R248 0 YA4 B4 CON_JTAG_TDO 12 S3B
S4A 10 JTAG_TDO
REMOTE_SEL_B LVL_SHF_TDO 1 D4 JTAG_TDO 4
D26 DNP HDR 2X5 12 11
GND

ONOFF Remote Control

POR_B A C OE S4B 15 REMOTE_SEL
4 POR_B Warm Reset, CPU ONLY GND R385 10K SEL
NSR0320 VCC_FT_3V3 74AVC4T3144 6 13
6

GND EN
3

D23 Q12
SYS_nRST A C SEL=H, OE=L, EN SEL=H, D <-> B(Remote Debug)
Cold Reset TMUX1574RSVR
R347 R381 1K ONOFF
NSR0320 REMOTE_SEL 1 SEL=L, OE=H, DIS Default 10K SEL=L, D <-> A(Connector) Default
NX3008NBKW ,115 GND

3
2

GND GND Q11

NX3008NBKW ,115
GND FT_ONOFF_B R382 0 1

10K
B FT_ONOFF_B=H, ONOFF=L B

FT_ONOFF_B=L, ONOFF=H Default

2
R383
GND

GND

Buttons Bootmode Remote Control

TP120

SW 1 # CPU ONOFF Button VDD_1V8 Boot Switch

CPU
1 3 ONOFF 4 ONOFF C321 C322

2 4
1.0UF
10V
0.01UF
50V
Remote Debug Expansion Interface for
SPST PB 0402_CC 0402_CC

U20
IO Expansion Power Measurement Board
GND 14
VDD

TP121 21 SW _BOOT_MODE0
SW _BOOT_MODE0

FT_BOOT_MODE0
16

1
S1A
0

D1
2 BOOT_MODE0
BOOT_MODE0 4
VCC_FT_3V3
C317 C318 C319 C320
VCC_FT_1V8 Receptacle
SW 2 # System Reset Button SW _BOOT_MODE1 3 S1B 1.0UF 0.1uF 1.0UF 0.1uF J25
1

2
3

4
R406 0 SYS_nRST 4 RESET 21 SW _BOOT_MODE1
FT_BOOT_MODE1
SW _BOOT_MODE2
4
9
S2A

S2B
D2
5 BOOT_MODE1
BOOT_MODE1 4
10V
0402_CC
25V
0402_CC
10V
0402_CC
25V
0402_CC
DCDC_5V
1
3
2
4
21 SW _BOOT_MODE2 S3A BOOT_MODE2
SPST PB 7 5 6

23
21
FT_BOOT_MODE2 D3 BOOT_MODE2 4
8 GND U70 GND 7 8
SW _BOOT_MODE3 12 S3B 1 P0_0 R386 100 FT_BOOT_MODE0 VBUS_USB_DBG 9 10
SEL=H, D <-> B(Remote Debug)

VDD_I2C
VDD
21 SW _BOOT_MODE3 S4A BOOT_MODE3 P0_0 P0_1 FT_BOOT_MODE1
10 2 R387 100 11 12
FT_BOOT_MODE3 1 D4 BOOT_MODE3 4 P0_1 P0_2 FT_BOOT_MODE2 FT_IO_01
11 3 R388 100 13 14
GND S4B 15 REMOTE_SEL SEL=L, D <-> A(BOOT Switch) Default P0_2 4 P0_3 R389 100 FT_BOOT_MODE3
4 PW R_MEAS_IO1
PW R_MEAS_IO1 15 16 FT_IO_02
SEL P0_3 5 P0_4 R390 100 FT_IO_01 PW R_MEAS_IO2 17 18 FT_IO_03
P0_4 P0_5 FT_IO_02
8M Plus IO_Ex 4 PW R_MEAS_IO2
6 13 GND
18 6 R391 100 19 20
GND EN ADDR P0_5 7 P0_6 R392 100 FT_IO_03 FT_SCL 21 22 FT_IO_04
FT_IO_nRST P0_6 P0_7 FT_IO_04
3.3V FT_SDA FT_IO_05
TMUX1574RSVR R412 0 24 8 R393 100 23 24
R427 R411 10K RESET P0_7 FT_GPIO1 25 26 FT_IO_06
EN=H Disable VCC_FT_3V3 P1_0 FT_REMOTE_SEL FT_GPIO2 FT_IO_07
FT4232 IO_EX
10K I2C IO EXP P1_0 10 R394 100 27 28
FT_SCL R363 0 FT_IOEXP_SCL 19 11 P1_1 R395 100 FT_IO_05 FT4232 IO 29 30 1.8V
EN=L Enable FT_SDA R364 0 FT_IOEXP_SDA 20 SCL P1_1 12 P1_2 R396 100 FT_IO_06 FT_GPIO3 31 32 FT_IO_08
SDA P1_2 13 P1_3 R397 100 FT_IO_07 FT_GPIO4 33 34 FT_IO_09
P1_3 P1_4 FT_IO_08
3.3V FT_RESET_B FT_IO_10
14 R398 100 35 36

System ID GND GND P1_4 15 P1_5 R399 100 FT_IO_09 FT_IO_nRST 37 38 FT_IO_11
FT_IO_nINT R449 0 22 P1_5 16 P1_6 R400 100 FT_IO_10 39 40
R413 10K INT P1_6 17 P1_7 R401 100 FT_IO_11
VCC_FT_3V3 P1_7
VCC_FT_3V3 DF40C-40DS-0.4V(51)

VSS

10K
10K
10K
10K
10K
10K
10K
EP
# I2C ADDR: 20(0100000x)
PCA6416AHF,128 GND GND

9
25

R415
R416
R417
R418
R419
R420
R421
C338
0.1uF FT Conencted First --> FT_3V3/1V8 ON --> FT_BOOT_MODE Input --> REMOTE_SEL HIGH --> Board Power/Repower --> VDD_1V8 ON --> POR_B
A A
25V
0402_CC FT_BOOT_MODE Output Switch enable BOOT_MODE Sampling
8

U80
GND Connection switch to Remote Debug GND
CPU Power ON First --> VDD_1V8 ON --> POR_B
VCC

FT_SCL R441 0 5
SDA 1 R440 0
VCC_FT_1V8
FT_SDA R442 0 6 NC1 2 VCC_FT_3V3 Switch enable BOOT_MODE Sampling
SCL NC2 3
R443 0 7 NC3 Switch select to Local Switch
GND

WP

AT24C16C Microcontroller Product Group

4

GND DNP
6501 W illiam Cannon Drive W est
Austin, TX 78735-8598
GND This document contains information proprietary to NXP and shall not be used for engineering design,
Address = 0x57 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ___ IUO: _X_ PUBI: ___

Designer: Drawing Title:
FL
8MPLUS-BB
Drawn by: Page Title:
FL Debug
Approved: Size Document Number Rev
<Approver> A1 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 19 of 21

5 4 3 2 1
 5 4 3 2 1

SYSTEM POWER
R251 3.3 1%

Main PWR (5-20V-->5V) C254

0.22uF
8A is maximum capability of the regulator TP67
D 50V System current TBD D

8
U63 0402_CC
1 5

BST
VBUS_IN VIN VOUT L16 1.5uH DCDC_5V
+ C255 4 7 1 2 C257 C258 C259 C260
100uF R252 NC SW R253 C256 0.1uF 100UF 100UF 100UF
50V 10K R254 25V 16V 16V 16V TP68
cce8p3x8p3 1% 43K 0402_CC 1210_CC 1210_CC 1210_CC
0603_CC # EN: 1.35V-4.5V MP8759GD 499K DNP 220PF DNP 1%
R24 10K # EN: internal 600K PD 12 R256 3 5
VCC_3V6 9 EN 499
R1 GND 2 VDD_5V
VCC
ESD5B5.0ST1G

GND DNP C264 R261 1 C261

2

PGND

AGND
5V_PG 3 11 Vfb=600mV 0.22uF 22K 0.01UF
TP69
C
PG FB
BZX585-B3V3
R258 100K 6 50V Q8 50V

4
TVS8 C265 MODE 0402_CC AON7405 0402_CC
D24 0.22uF R260 Vout = (R1+R2) * Vfb / R2

10
50V C263 R259 5.6K ‐ 50A Max ‐
0402_CC 1.0UF 100K # 5.2V/8A 1% Rds=10 mOhm
1

10V DNP R2 R263 @ Vgs ‐4.5V

0402_CC 4.7K @ Id = ‐20A
Vgs(th) = ‐1.7V min
Vds(max) = ‐30V C266 C267
1uF 100UF

3
GND GND GND GND GND 16V 16V
0402_CC 1210_CC

R264 22K 1
VDD_3V3 Q10
4 PMIC_ON_REQ R265 1K DNP NX3008NBKW,115
C R266 C269 C
100K 0.1uF

2
25V
0402_CC

3.3V for Peripherals TP70

GND

PWR LED
DCDC_5V U64 L17 Standoff for CPU board
8 1 1 2 VDD_3V3
VIN1 SW1 VEXT_3V3
1

C270 C271 11 9 0.47uH BH2 BH3 BH4 BH11 BH12

47UF 0.1uF VIN2 SW2 STANDOFF M2.5
STANDOFF M2.5
STANDOFF M2.5
STANDOFF STANDOFF
M2.5 M2.5
16V 25V 2 R268 C272 C273 C274 C275
2

CC1210 0402_CC R267 OUT 187K 1000pF 22uF 22uF 0.1uF

100K
R1 1% 50V 10V 10V 25V
MP2147GD 0402_CC CC0603 CC0603 0402_CC R270
GND 1K
R269 10K 5 3 Vfb=600mV 5%
VDD_3V3 6 EN FB 4 C276 1000pFDNP GND GND GND GND GND GND
R271 1K DNP MODE/VCON RAMP 50V 0402_CC
4 EXT_PWREN1
R272 C277 7 10

A
R37 1K DNP 100K 0.22uF PG GND R273
4 VEXT_3V3_EN
10V
R2 41.2K D25 Base board screw holes
0402_CC GND 1%
Vout = (R1+R2) * Vfb / R2
LED RED
Default: ON # 3.3V/4A BH5
.635" LONG
BH6
.635" LONG
BH7
.635" LONG
BH8
.635" LONG
B B

C
GND
EXT_3V3_PG GND
TP71

GND

GND GND GND GND

12V for Peripherals
GND Testpoints
C278
0.22uF TP105 TP72 TP73 TP74 TP75 TP76 TP77 TP78 TP79 TP80
50V
10

U49 0402_CC L18

2 9 1 2
BST

VBUS_IN VIN SW 10uH PER_12V

+ C279 C281 C282
100uF GND C283 1.0UF 11 C280 R276 + 100uF + 100uF
50V 10V 0402_CC VCC 5.6PF 1M 35V 35V
cce8p3x8p3 R282 100K 6 50V 1% cce6p8x6p8 cce6p8x6p8
VDD_3V3 PER_12V_PG PG 0402_CC DNP GND
TP81
14 Vfb=800mV
R1
R281 1K 4 FB
4 EXT_PWREN2 EN
GND 1 Microcontroller Product Group
PGND1
PGND2

# EN: internal 1M PD MODE

AGND

15 7 GND
13 FREQ BIAS 5 R280 6501 William Cannon Drive West
SS NC 71.5K Austin, TX 78735-8598
A
MP2263GD 1%
Vout = (R1+R2) * Vfb / R2 This document contains information proprietary to NXP and shall not be used for engineering design,
A
Default: OFF, only power on when
3
8
12

R450 R278 C332 R446 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
Type‐C input is 15V or 20V. 100K 165K 0.01UF 0 R2
1% 50V
0402_CC
# 12V/3A Designer: Drawing Title:
ICAP Classification: CP: ___ IUO: _X_ PUBI: ___

GND FL
8MPLUS-BB
GND GND GND GND GND Drawn by: Page Title:
FL Power
Approved: Size Document Number Rev
<Approver> A3 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 20 of 21

5 4 3 2 1
 5 4 3 2 1

Boot Mode and CFG Switch

i.MX8M Plus ROM Fuse i.MX8M Plus Boot Mode
Full Line Physical
Address Address 7 6 5 4 3 2 1 0 BOOT_MODE3 BOOT_MODE2 BOOT_MODE1 BOOT_MODE0 Boot Modes
OVERRIDE_FLEXSPI_BT_SEL_VAL
OVERRIDE_NAND_PG_PER_BLK_VAL 00 - FlexSPI (Hyperflash 1.8V) SW4 [1] SW4 [2] SW4 [3] SW4 [4] SW4 [1-4]
00 - 32 pages OVERRIDE_FLEXSPI_BT_SEL 01 - FlexSPI (Flash with 4B READ(1x13 default FLEXSPI_AUTO_PROBE_EN FLEXSPI_AUTO_PROBE_TYPE
01 - 64 pages 0 - Do not overriude supported) 00 - QuadSPI NOR
D 0x470[15:0] 0x470[7:0] 10 - 128 pages 1 - Override 0 - Disable 01 - MxicOctal D
10 - Default Octal mode (Micron, supported on
11 - 32 pages 8QXP B0 already)
10 - MicronOctal 0 0 0 0 Boot From Internal Fuses
1 - Enable 11 - AdestoOctal
11 - Default Octal mode (Mxic, Nice to have)

FLEXSPI_FEQ_SEL 0 0 0 1 USB Serial Download

000 - 100 MHz
001 - 133 MHz
0x480[15:0] 0x480[7:0] Reserved FLEXSPI_DUMMY_CYCLE_SEL 010 - 166 MHz
011 - 200 MHz USDHC3 (eMMC boot only, SD3 8-bit)
100 - 80 MHz 0 0 1 0 Default
101 - 20 MHz

ROM_NO_LOG SDP_DISABLE FORCE_BT_FROM_FUSE FLEXSPI_HOLD_TIME_SEL WDOG_TIMEOUT_SELECT 0 0 1 1 USDHC2 (SD boot only, SD2)
00 - 500us 00 - 2.0s
0x480[31:16] 0x480[23:16] NOC_ID_REMAP_BYPASS if blown, ROM will not Disable USB serial Boot from programmed 01 - 1ms 01 - 1.5s
log event to log buffer download fuses, not Boot Mode Pins 10 - 3ms 10 - 1.0s
11 - 10ms 11 - 0.5s
0 1 0 0 NAND 8-bit single device 256 page
SDMMC_BUS_WIDTH SD_SPEED: USDHC_VOL_SEL USDHC_MFG_VOL_SEL
USDHC_PWR_EN EMMC_FAST_BT 00 - 8-bit 00 - Normal/SDR12 EMMC_SPEED: For Normal Boot Mode For Mfg Mode IO Voltage
0x490[15:0] 0x490[7:0] 0 - No power cycle 0 - Regular 01 - 4-bit 01 - High/SDR25 00 - Normal IO Voltage 0 - 3.3V 0 1 0 1 NAND 8-bit single device 512 page
1 - Enabled via 1 - Fast Boot 10 - 8-bit DDR (MMC 4.4) 10 - SDR50 01 - High 0 - 3.3V 1 - 1.8V
11 - 4-bit DDR (MMC 4.4) 11 - SDR104 1 - 1.8V
RECOVERY_SDMMC USDHC_DLL_EN 0 1 1 0 QSPI 3B Read
_BOOT_DIS USDHC_PAD_SION_EN 0 - Disable DLL for
0x490[31:16] 0x490[23:16] 0 - Enable 0 - Disable Reserved SD/eMMC
1 - Disable IMG_CNTN_SET1_OFFSET 1 - Enable 1 - Enable DLL for
SD/eMMC
0 1 1 1 QSPI Hyperflash 3.3V
USDHC_PWR_INTERVAL
SD_CALI_STEP 00 - 20ms USDHC_PWR_DELAY USDHC_PWR_POLARITY EMMC_FAST_BT_ACK
C 0x4A0[15:0] 0x4A0[7:0] '00' - 1 01 - 10ms 0 - 5ms 0 - Low USDHC_OVRD_ 0 - Boot Ack Disabled 1 0 0 0 ecSPI Boot C

TBD 10 - 5ms 1 - 2.5ms 1 - High PAD_SETTING_UP1 1 - Boot Ack Enabled

11 - 2.5

0x4A0[31:16] 0x4A0[23:16] Reserved

1 0 0 1 Reserved

NAND_GPMI_DDR_DLL_VAL NAND_CS_NUM
(GPMI Read DDR DLL Target Value) (Nand Number Of Devices) 1 0 1 0 Reserved
0000 - 7 00 - 1
0x4B0[15:0] 0x4B0[7:0] Reserved 0001 - 1 Reserved 01 - 2
0111 - 0 10 - 4
1111 - 15 11 - Reserved 1 0 1 1 Reserved
FlexSPI NAND CS Interval FlexSPI NAND Column Address Width
00-100ns 00-12
0x4B0[31:16] 0x4B0[23:16] Reserved FlexSPI NAND Busy Bit Offset Override 01-200ns 01-13 1 1 0 0 Reserved
10-400ns 10-14
11-50ns 11-15

1 1 0 1 Reserved

Full Line Physical

Address Address 7 6 5 4 3 2 1 0 1 1 1 0 Reserved
BOOT_MODE_FUSES
OVERRIDE_USDHC_BT_SEL OVERRIDE_USDHC_BT_SEL_VAL
BootRom will retrieve boot mode from these fuses instead of BOOT_MODE pins if 00 - uSDHC1 SD OVERRIDE_NAND_PG_PER_BLK 1 1 1 1 Reserved
0x470[15:0] 0x470[15:8] * BOOT_MODE_PINS=0x0 or 0 - Do not override 01 - uSDHC1 eMMC 0 - Do not override
10 - uSDHC2 eMMC 1 - Override
* BT_FUSE_SEL blown
1 - Override 11 - uSDHC3 SD
B B

BT_LPB (Core/DDR/Bus) BT_FREQ_SEL

'00'/'01' - LPB Disable BT_LPB_POLARITY ICACHE_DIS WDOG_EN (ARM/DDR) DCACHE_DIS
0x480[15:0] 0x480[15:8]
Boot Switch
'10' - Div by2 (GPIO polarity) L1 I-Cache TZASC_EN '0' - Disabled 0 - 800 / 800 MHz
'11' - Div by 4 DISABLE '1' - Enabled 1 - 400 / 400 MHz Disable L1 and L2 D-Cache
VDD_1V8
ECSPI_PORT_SEL ECSPI_CS_SEL(SPI only) SW4
000 - eCSPI1 ECSPI_ADDR_SEL 00 - CS#0 (default) RECOVER_ECSPI_BOOT_EN SW_BOOT_MODE3
0x480[31:16] 0x480[31:24] DCACHE_BYPASS_DIS 1 8 R283 2.2K
001 - eCSPI2 0 - 3-bytes (24-bit) 01 - CS#1 '0' - Disabled 19 SW_BOOT_MODE3 SW_BOOT_MODE2 2 7 R284 2.2K
010 - eCSPI3 1 - 2-bytes (16-bit) 10 - CS#2 '1' - Enabled 19 SW_BOOT_MODE2 SW_BOOT_MODE1 3 6 R285 2.2K
19 SW_BOOT_MODE1
11 - CS#3 19 SW_BOOT_MODE0
SW_BOOT_MODE0 4 5 R286 2.2K

DHN-04

100K
100K
100K
100K
USDHC_DLL_SEL SDMMC_DLL_DLY[6:0]
0x490[15:0] 0x490[15:8] 0 - DLL Slave Mode for Delay target for USDHC DLL, it is applied to slave mode target delay
1 - DLL Override Mode or override mode target delay depends on DLL Override fuse bit value.

R287
R288
R289
R290
0x490[31:16] 0x490[31:24] USDHC_OVRD_PAD_SETTING_LOW8[7:0]

NAND_TG_PREAMBLE_RD_LATENCY
(Toggle Mode 33MHz Preamble Delay, Read Latency)
'000' - 16 GPMICLK cycles. GND
NAND_FCB_SERCH_COUNT '001' - 1 GPMICLK cycles.
00 - 2 '010' - 2 GPMICLK cycles. TP122 VDD_1V8 TP123
0x4A0[15:0] 0x4A0[15:8] BT_TOGGLE_MODE 01 - 2 NAND_RST_TIME
'011' - 3 GPMICLK cycles.
10 - 4 '100' - 4 GPMICLK cycles.
11 - 8 '101' - 5 GPMICLK cycles. 4 JTAG_MOD
JTAG_MOD R313 2.2K DNP

'110' - 6 GPMICLK cycles.

'111' - 7 GPMICLK cycles.
'1111'- 15 GPMICLK cycles. Caution:
BOOT_MODE0, BOOT_MODE1, BOOT_MODE2, BOOT_MODE3, JTAG_MOD and POR_B must be
0x4A0[31:16] 0x4A0[31:24] NAND_OVERRIDE_PAD_SETTING[7:0] pulled to "111111" for i.MX8M Plus to enter Boundary Scan mode.
A A

NAND_READ_RETRY_SEQ_ID[3:0]
0000 - don't use read retry(RR) sequence embedded in ROM Microcontroller Product Group
0001 - Micron 20nm RR sequence 6501 William Cannon Drive West
0010 - Toshiba A19nm RR sequence NAND_ROW_ADDR_BYTES Austin, TX 78735-8598
0011 - Toshiba 19nm RR sequence 00 - 3 This document contains information proprietary to NXP and shall not be used for engineering design,
0x4B0[15:0] 0x4B0[15:8] 0100 - SanDisk 19nm RR sequence 01 - 2 Reserved Reserved procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
0101 - SanDisk 1ynmRR sequence 10 - 4
0110 - Hynix 20nm A Die RR sequence ICAP Classification: CP: ___ IUO: _X_ PUBI: ___
11 - 5 Designer: Drawing Title:
0111 - Hynix 26nm RR sequence FL
1000 - Hynix 20nm B Die RR sequence 8MPLUS-BB
1001 - Hynix 20nm C Die RR sequence Drawn by: Page Title:
Others - Reserved FL BOOT_CFG
Approved: Size Document Number Rev
0x4B0[31:16] 0x4B0[31:24] RNG_TRIM[7:0] <Approver> A2 SCH-46370 PDF: SPF-46370 B1

Date: Thursday, May 13, 2021 Sheet 21 of 21

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