Design strategies for Signal Integrity, Power Integrity

and EMI EMC issues in Computing boards and

Systems

Abstract— In the modern world, complexity of electronic source of power supply, to the integrated circuits and active
products has increased due to the demand for higher devices that consist of boards and packages with planes,
performance such as faster data transfers, better image routed traces and decoupling capacitors [1].
processing, higher computing power, and greater functionality.
The technological advancements towards multi-core CPU and Emission control and susceptibility in this comprehensive
GPGPU environments in a single Printed Circuit Board has environment is another challenging aspect. The applicable
brought up various design challenges and constraints for emission and susceptibility requirements are dependent upon
compute and signal processing systems. One such challenge is to the intended installations and standards for qualification [4].
meet the Signal, Power Integrity and stringent EMI/EMC This paper discusses the challenges faced and issues mitigated
standards for the equipment based on the installation platform. during PCB testing, EMI/EMC qualifications of the system,
The operating frequencies of processor clocks and switching
frequencies of interfaces are ranging from few MHz to 10 GHz. troubleshooting methodologies and design improvements
The improper terminations of the high-speed signals not only implemented for Signal, Power integrity, EMI/EMC
affect the system performance but also its surrounding system compliance.
performance through emissions. Hence it is very much essential
to sensitize on various challenges involved in Signal, Power II. PROBLEM STATEMENTS AND SOLUTIONS
Integrity, EMI EMC qualification of a high-end Computing and
Signal Processing system. The approach followed for SI, PI, EMI/EMC compliance
may be broadly classified as:
Keywords—Multi-core, Signal Integrity, Power Integrity, 1. PCB Development
EMI/EMC. a. Signal routing and SignalIntegrity
b. Power distribution and Power integrity
I. INTRODUCTION 2. System Integration
Computing and Signal Processing systems are an a. Integration of all sub-modules
integrated eco-system of Intel Xeon/Core i7 processors, b. EMI EMC Testing and Corrective actions
NVIDIA Graphics processor, Intel FPGAs, Xilinx FPGAs,
storage and very sensitive power sections. Current high-speed (1.a) Signal Routing and Signal Integrity
regime, interconnects are no longer transparent. Interconnects Problem Statement-1: Loss of communication link and
degrades the fidelity of the signals coming off the chips. intermittent glitches of display in Display Port (DP) interface
Failure to consider these problems and eliminate them from was occurred very often.
the beginning, there is a good chance that the product will Identified Root Cause: Display port has four lanes of differential
have performance issues. The crux of signal integrity is really pairs with the data rate of 5.4 GHz/lane. The differential pairs
about the electromagnetic fields of the signals interaction with were routed in different signal layers, which resulted
the boundary conditions of the dielectrics and conductors. discontinuities among the signal group of DP port despite the
From the circuits view, the distortion of voltages and currents proper length matching between differential pairs.
signals interaction is caused by the transmission lines
discontinuities. The power integrity of the power distribution
network or PDN is to provide a low-impedance reference path
to signals. A high impedance of a PDN yields inadequate
current delivery to the receiver. Thus, this can be a root cause
for signal integrity issues such as: Voltage ripples, Jitter,
timing violations, false switching, Bit errors, Noise
propagation and crosstalk throughout the board. A PDN is the
path or interconnect from the voltage regulator model or Fig 1. Signal Grouping and Routing in Same layer
Realized Solution: Signal grouping, stringent length matching, performed on all the critical signals and ensure the measured
controlled impedance, routing of all differential pairs of the eye height & width is within specification limits.
display port in the same layer of PCB as shown in Fig 1 solved (1.b)Power Distribution and Power Integrity
the issue. Problem Statement-4: A fault in specific power section was
resulted malfunctions and damage across different sections of
Problem Statement-2: Clock and signals for high-speed the board. This is a case of common mode fault when there is
interfaces in FPGA or processor was not detected properly by multipath distribution of power source between various power
the device though the signal was available. sections of the board.
Identified Root Cause: AC coupling capacitance values and Identified Root Cause: When the source power net is distributed
physical placement of these capacitors on the board were the to different sections, the failure or load fluctuation in one
factors for loss of signal quality received by the devices. device is creating a source voltage drop in another device
which in turn affects the power supply operations. This is
more prominent in case of daughter cards and COTs module
integration.
Realized Solution: Distribution of power source through ferrite
beads and fuses made common power source into multiple
independent local power nets which was helpful for debugging
and avoiding common mode faults as shown in Fig 4.

Fig 2. AC Coupling capacitors – Proximity

Realized Solution: AC coupling capacitors are usually
recommended at nearest proximity of the receiving end of the
link. Placement of coupling capacitors within the close
proximities and maintaining equal length distributions for all
the differential pairs after the coupling as shown Fig.2 has
significantly improved the performance in this scenario. Fig 4. Power distribution across different sections
Problem Statement-5: Thermal hotspots at some places at PCB
Problem Statement-3: High frequency signal was routed near and thermal dissipation of the board were not uniform.
power section of the board which resulted the data corruption Identified Root Cause: Thermal distributions were in
in the data signal. appropriate at some PCB area because of high operating
Identified Root Cause: This scenario was specifically observed currents. This was happening due to in sufficient power
where the high speed data signal was routed very close to distribution across layers and randomness in via placement.
switching plane of the power circuitry.

Guard trace

Fig 5. Power Integrity – High Current Density Pattern

Fig 3. Guard trace for isolation from switching plane
Realized Solution: Guard trace was routed between high-speed
signal and switching power plane as shown in Fig 3, which
had nullified the data corruption in data signal [2].
In addition to the above-discussed solutions, component
selection at various stages is ensured for noise control. These
include ferrite beads at entry of power sections, magnetics and
line filters to couple high frequency signals from external
sources, ESD diodes and appropriate series and end
terminations. Also, signal integrity analysis has to be Fig 6. Power Integrity – Improved Current Density Pattern
Realized Solution: Thermal sensitive areas on the board were harmonics of this frequency were captured with substantial
identified and effective power distribution was achieved by emission levels.
appropriate Via’s and their pattern. Fig 5 shows the high
current density up to 98.9mA/mil2 on a PCB with non-copper
filled via’s. Fig 6 shows the improved current density pattern
where maximum current density is coming down
to68.7mA/mil2. This was achieved by increased via count,
pattern of via dropping and vias filled with copper. Fig 7
shows a portion of via’s placement for an area with multiple
power nets.

Fig 8. Failure case - CE102

Realized Solution: The EMI filter characteristics were

modified to improve attenuation factor at the identified
frequency range by introduction of common mode choke. Fig
Fig 7. Vias for power distribution across layers
9 shows substantial decrease in emissions.
Also, power integrity analysis has to be performed on all
the critical power nets for the DC drop and decoupling
analysis.

(2.a) Integration of All Sub-modules

Problem Statement-6: When the sub-modules of the system
were integrated, it was observed that graphics unit
functionality was affected and one of the display port stopped
working.
Identified Root Cause: The switching frequency emission
from the power supply module casing was conductively
coupled to nearest graphics section which was affecting one of
the ports.
Realized Solution: Non-metallic fixtures are used for
assembly of power supply module on chassis. This has Fig 9. Pass case - CE102
provided electrical isolation from the power supply casing.
Other important aspects that were ensured in the design Problem Statement-8: During radiated emission tests RE102,
include: system had passed for some platforms (Navy-Fixed and Air-
 EMI Filter is the first element in supply chain force) but failed for different platforms (Navy Mobile and
 Minimized Internal Wiring Ground Army). Fig 10 shows the emission limits for different
 Isolation of critical sections and mini enclosures platforms and the measured values from system.
 Board to Board interconnects with minimal stub length
 Alignment of external connectors at chassis boundaries
 Restriction of air gaps with Jam-nuts in connectors
 EMI gaskets for chassis cover

(2.b) EMI EMC Testing and Corrective Actions

Problem Statement-7: Conductive emission tests CE102
based on MIL461E [5] have shown emissions above threshold
level at some frequency range as shown in Fig 8.
Identified Root Cause: The frequency of emissions was
around 72 KHz which is the switching frequency (75 KHz) of
power supply module. It was observed that the 1st, 2nd and 3rd
Fig 10. Failure case - RE102 (VPOL)
Identified Root Cause: The system marginally passed for III. CONCLUSION
Navy-Fixed and Air-force but failed for Navy Mobile and With the emergence of faster protocols and multi-core
Ground Army. The source for higher emissions was identified architectures in an array of application domains, it is important
as Ethernet communication links. This was concluded based to understand the major design characteristics that affect SI, PI
on repetitive experimentation by isolation of individual cables and EMI/EMC performance of the system. In this article we
and also based on the operating frequency range of the tried to present case-studies with solutions for the problems
interface. The emitted system noise was at the frequency of which are tightly coupled with SI, PI and EMI/EMC domains.
2MHz - 200MHz band. As more applications are developed that can take advantage of
Realized Solution: Following improvements are made in multi-core, designs will continue to evolve with more
design to control the radiated emissions which has brought sophisticated issues with respect to these factors. The upward
down the emissions significantly as shown in Fig 11: trend of onboard bandwidth and downward trend of system
 Introduction of double shielding for external cables to size and operations will place greater thrust on performance.
effectively fill the gaps. The designs and strategies should continuously evolve to face
 Reduction of impedance of ground reference of a these challenges.
system and single point ground reference through
ferrite bead was provided to minimize the emission [3]. REFERENCES
 Metallic enclosure for power supply module
[1] Signal and Power Integrity - Simplified by Eric Bogatin
[2] High-Speed Signal Propagation -Advanced Black Magic
by Howard W.Johnson & Martin Graham
[3] EMI Troubleshooting Cookbook for Product Designers -
Patrick G. Andre and Kenneth Wyatt
[4] PCB design techniques for lowest-cost EMC compliance -
M. K. Armstrong
[5] MIL STD 461-E/F

Fig 11. Pass case - RE102 (VPOL)

Problem Statement-9: During conducted susceptibility tests

CS115 (30nsec Pulse @30Hz for 1min on each cable), USB
device was not working properly during the test.
Identified Root Cause: Cable braids for the cable were not
having proper 360º shielding which resulted in interference of
actual signal with the induced pulse.
Realized Solution: Cable quality was improved with good
quality braids and additional braids added at connecting
junctions. This has prevented noise interference into the cable
and system has passed the test. This precaution measure has
improved RE102 test performance also. Shielding is a tradeoff
between cost and good performance in frequency range.
Other important aspects that were ensured in the design
include w.r.t., emissions and susceptibility tests are:
 Chamber was calibrated for ambient conditions before
every test and were ensured to be within limits.
 Cable shield bonding with proper contact to chamber
ground.
 The terminations, connector bonding, 360⁰ shield and
grounding path are ensured to protect the system under
test from external source of interference.