UNIT-1

Functional units of digital system

The internal architectural design of computers differs from one system model
to another. However, the basic organization remains the same for all
computer systems. The following five units (also called “The functional
units”) correspond to the five basic operations performed by all computer
systems.

Input Unit
● Data and instructions must enter the computer system before any
computation can be performed on the supplied data. The input unit
that links the external environment with the computer system
performs this task.
● Data and instructions enter input units in forms that depend upon the
particular device used. For example, data is entered from a keyboard
in a manner similar to typing, and this differs from the way in which
data is entered through a mouse, which is another type of input
device.
 In short, an input unit performs the following functions.

1. It accepts (or reads) the list of instructions and data from the outside
world.
2. It converts these instructions and data in computer acceptable format.
3. It supplies the converted instructions and data to the computer system
for further processing.

Output Unit
An output unit is just the reverse of that of an input unit. It supplied
information and results of computation to the outside world. Thus it links the
computer with the external environment. As computers work with binary
code, the results produced are also in the binary form. Hence, before
supplying the results to the outside world, it must be converted to human
acceptable (readable) form. This task is accomplished by units called output
interfaces.

In short, the following functions are performed by an output unit.

1. It accepts the results produced by the computer which are in coded

form and hence cannot be easily understood by us.
2. It converts these coded results to human acceptable (readable) form.
3. It supplied the converted results to the outside world.

Storage Unit
● The data and instructions that are entered into the computer system
through input units have to be stored inside the computer before the
actual processing starts. Similarly, the results produced by the
computer after processing must also be kept somewhere inside the
computer system before being passed on to the output units.
● The intermediate results produced by the computer must also be
preserved for ongoing processing. The Storage Unit or the primary /
main storage of a computer system is designed to do all these things.
It provides space for storing data and instructions, space for
intermediate results and also space for the final results.

In short, the specific functions of the storage unit are to store:

1. All the data to be processed and the instruction required for processing
(received from input devices).
2. Intermediate results of processing.
3. Final results of processing before these results are released to an
output device.
Central Processing Unit (CPU)
● The main unit inside the computer is the CPU. This unit is responsible
for all events inside the computer. It controls all internal and external
devices, performs “Arithmetic and Logical operations”. The
operations a Microprocessor performs are called “instruction set”
of this processor. The instruction set is “hard wired” in the CPU and
determines the machine language for the CPU.
● Processors differed from one another by the instruction set. If the same
program can run on two different computer brands they are said to be
compatible. Programs written for IBM compatible computers will not
run on Apple computers because these two architectures are not
compatible.

The control Unit and the Arithmetic and Logic unit of a computer system are
jointly known as the Central Processing Unit (CPU). The CPU is the brain of
any computer system. In a human body, all major decisions are taken by the
brain and the other parts of the body function as directed by the brain.
Similarly, in a computer system, all major calculations and comparisons are
made inside the CPU and the CPU is also responsible for activating and
controlling the operations of other units of a computer system.

Arithmetic and Logic Unit (ALU)

● The arithmetic and logic unit (ALU) of a computer system is the
place where the actual execution of the instructions take place during
the processing operations. All calculations are performed and all
comparisons (decisions) are made in the ALU. The data and
instructions, stored in the primary storage prior to processing are
transferred as and when needed to the ALU where processing takes
place.
● No processing is done in the primary storage unit. Intermediate results
generated in the ALU are temporarily transferred back to the primary
storage until needed at a later time. Data may thus move from
primary storage to ALU and back again as storage many times before
the processing is over. After the completion of processing, the final
results which are stored in the storage unit are released to an output
device.
● The arithmetic and logic unit (ALU) is the part where actual
computations take place. It consists of circuits that perform arithmetic
operations (e.g. addition, subtraction, multiplication, division over data
 received from memory and capable to compare numbers (less than,
equal to, or greater than).
● While performing these operations the ALU takes data from the
temporary storage are inside the CPU named registers.
● Registers are a group of cells used for memory addressing, data
manipulation and processing. Some of the registers are general
purpose and some are reserved for certain functions. It is a high-speed
memory which holds only data from immediate processing and results
of this processing. If these results are not needed for the next
instruction, they are sent back to the main memory and registers are
occupied by the new data used in the next instruction.

Control Unit
How the input device knows that it is time for it to feed data into the storage
unit? How does the ALU know what should be done with the data once it is
received? And how is it that only the final results are sent to the output
devices and not the intermediate results? All this is possible because of the
control unit of the computer system. By selecting, interpreting, and seeing to
the execution of the program instructions, the control unit is able to maintain
order and directs the operation of the entire system.

● It does not perform any actual processing on the data, the control unit
acts as a central nervous system for the other components of the
computer. It manages and coordinates the entire computer system. It
obtains instructions from the program stored in main memory,
interprets the instructions, and issues signals that cause other units of
the system to execute them.

BUSES
Definition - What does Bus mean?
A bus is a subsystem that is used to connect computer components and transfer data between
them. For example, an internal bus connects computer internals to the motherboard.

A bus may be parallel or serial. Parallel buses transmit data across multiple wires. Serial buses
transmit data in bit-serial format.
Control Bus
The motherboard's control bus manages the activity in the system. The control bus, like the other
buses, is simply a set of connections among the parts in the computer. All parts "agree to
recognize" that if one connection carries a voltage and the next one does not, it means that the
central processor reads from memory. If the connections reverse roles, the processor writes to
memory. Other connections deal with the "chunking" of data 8, 16, 32 or 64 bits at a time. Still
others determine if data is being shuttled to the central processor from memory or the keyboard.
This signaling system prevents data from going to the wrong place.

Data Bus
The data bus acts as a conduit for data from the keyboard, memory and other devices. It passes
information at speeds up to billions of characters per second. The central processor reads the
data, performs calculations, and moves new data back to memory, the hard drive and other
locations. The control bus determines which direction the data is moving.

Address Bus
The computer must be able to access every character of memory rapidly, so every character has
its own address number. The central processor specifies which addresses it wants to read or write
and the address bus carries this information to a memory controller circuit, which locates and
fetches the information. Some locations, called random-access memory, hold program
instructions and temporary calculation results. Other locations point to the hard drive, mouse and
keyboard. The control bus specifies which of these two sets of addresses become active for a
particular memory operation.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by
the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to the
0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

Three-State Bus Buffers

A bus system can also be constructed using three-state gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of which are
signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a
high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 ● The outputs generated by the four buffers are connected to form a single bus line.
● Only one buffer can be in active state at a given point of time.
● The control inputs to the buffers determine which of the four normal inputs will communicate
with the bus line.
● A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.

● The transfer of information from a memory unit to the user end is called a Read operation.
● The transfer of new information to be stored in the memory is called a Write operation.
● A memory word is designated by the letter M.
● We must specify the address of memory word while writing the memory transfer operations.
● The address register is designated by AR and the data register by DR.
● Thus, a read operation can be stated as:
 1. Read: DR ← M [AR]

● The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
● And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1

● The Write statement causes a transfer of information from register R1 into the memory word
(M) selected by address register (AR).

What is Bus Arbitration?

● A device that initiates data transfers on the bus at any given time is called a bus master.
● In a computer system, there may be more than one bus master such as a DMA controller
or a processor etc.
● These devices share the system bus and when a current master bus relinquishes another
bus can acquire the control of the processor.
● Bus arbitration is a process by which next device becomes the bus controller by
transferring bus mastership to another bus.

Types of Bus Arbitration

There are two types of bus arbitration namely

1. Centralised Arbitration.
2. Distributed Arbitration.
Only single bus arbiter performs the required arbitration and it can be either a processor or a
separate DMS controller.
There are three arbitration schemes which run on centralized arbitration.
● a) Daisy Chaining − It is a simple and cheaper method where all the masters use the
same line for making bus requests.
● b) Polling Method − In this method, the controller is used to generate address lines for
the master. For example, if there are 8 masters connected in a system at least 3 address
lines are required.
● c) Independent Request − In this scheme, each bus has its own bus request and a grant.
The built-in priority decoder selects the highest priority requests and asserts the system.

Daisy chaining
● All masters make use of the same line for bus request. In response to the bus request the
controller sends a bus grant if the bus is free. The bus grant signal serially propagates
through each master until it encounters the first one that is requesting access to the bus.

Advantages –
 ● Simplicity and Scalability.
● The user can add more devices anywhere along the chain, up to a certain maximum
value.

Disadvantages –

● The value of priority assigned to a device is depends on the position of master bus.
● Propagation delay is arises in this method.
● If one device fails then entire system will stop working.

(ii) Polling method –

In this method, the devices are assigned unique priorities and complete to access the bus, but the
priorities are dynamically changed to give every device an opportunity to access the bus.

 In this the controller is used to generate the addresses for the master. Number of address line
required depends on the number of master connected in the system.
 For example, if there are 8 masters connected in the system, at least three address lines are
required.

 In response to the bus request controller generates a sequence of master address. When the
requesting master recognizes its address, it activated the busy line ad begins to use the bus.

Advantages –

● This method does not favor any particular device and processor.
● The method is also quite simple.
● If one device fails then entire system will not stop working.

Disadvantages –

● Adding bus masters is different as increases the number of address lines of the circuit.
(iii) Independent Request method –In this method, the bus control passes from one
device to another only through the centralized bus arbiter.

 In this scheme each master has a separate pair of bus request and bus grant lines and each pair
has a priority assigned to it.
 The built in priority decoder within the controller selects the highest priority request and
asserts the corresponding bus grant signal.

Advantages –

● This method generates fast response.

Disadvantages –

● Hardware cost is high as large no. of control lines are required.

Distributed Arbitration
 ● Here, all the devices participate in the selection of the next bus master.
● Each device on the bus is assigned a4 bit identification number.
● When one or more devices request control of the bus, they assert the start arbitration
signal and place their 4-bit identification numbers on arbitration lines through ARB3.
● Each device compares the code and changes its bit position accordingly.
● It does so by placing a 0 at the input of their drive.
● The distributed arbitration is highly reliable because the bus operations are not dependant
on devices.

Register`
Register are used to quickly accept, store, and transfer data and instructions that are
being used immediately by the CPU,

Types of Registers :
Memory Address Register (MAR): This register holds the memory addresses of data and
instructions. This register is used to access data and instructions from memory during the
execution phase of an instruction.
Memory Data Register (MDR):MDR which contains the data to be written into or readout of
the addressed location.
Accumulator Register: It hold the respond of operand of instruction.
Data Register: Temporary register as MDR.
Instruction Register: It having instruction address.
Instruction Buffer Register:Temporary register as IR .
Program Counter : It hold the address of instruction.
Index Register : It is a circuit that receive ,store & output instruction changing code in a
computer .

Processor Organization
● There are several components inside a CPU, namely, ALU, control unit, general purpose
register, Instruction registers etc. Now we will see how these components are organized
inside CPU.
● There are several ways to place these components and inteconnect them. In the fig, the
arithmatic and logic unit (ALU), and all CPU registers are connected via a single
common bus. This bus is internal to CPU and this internal bus is used to transfer the
information between different components of the CPU.
● This organization is termed as single bus organization, since only one internal bus is
used for transferring of information between different components of CPU. We have
external bus or buses to CPU also to connect the CPU with the memory module and I/O
devices.
● The external memory bus is also shown in the figure connected to the CPU via the
memory data and address register MDR and MAR.The number and function of registers
R0 to R(n-1) vary considerably from one machine to another. They may be given for
general-purpose for the use of the programmer.
● Alternatively, some of them may be dedicated as special-purpose registers, such as index
register or stack pointers.In this organization, two registers, namely Y and Z are used
which are transperant to the user. Programmer can not directly access these two
registers. These are used as input and output buffer to the ALU which will be used in
ALU operations. They will be used by CPU as temporary storage for some instructions.
 Most of the operation of a CPU can be carried out by performing one or more of the
following functions in some prespecified sequence:
● 1. Fetch the contents of a given memory location and load them into a CPU register.

● 2. Store a word of data from a CPU register into a given memory location.

● 3. Transfer a word of data from one CPU register to another or to the ALU.

● 4. Perform an arithmatic or logic operation, and store the result in a CPU register.

To perform a memory fetch operation

● we need to complete the following tasks:The CPU transfers the address of the required
memory location to the Memory Address Register (MAR).The MAR is connected to the
memory address line of the memory bus, hence the address of the required word is
transfered to the main memory.
● Next, CPU uses the control lines of the memory bus to indicate that a Read operation is
initiated. After issuing this request, the CPU waits until it receives an answer from the
memory, indicating that the requested operation has been completed.
 ● This is accomplished by another control signal of memory bus known as Memory-
Function-Complete (MFC).The memory set this signal to 1 to indicate that the contents of
the specified memory location are available in memory data bus.As soon as MFC signal
is set to 1, the information available in the data bus is loaded into the Memory Data
Register (MDR) and this is available for use inside the CPU.
As an example, assume that the address of the memory location to be accessed is kept in register
R2 and that the memory contents to be loaded into register R1. This is done by the following
sequence of operations:
1. MAR [R2]
2. Read
3. Wait for MFC signal
4. R1 [MDR]

Storing a word into memory

The procedure of writing a word into memory location is similar to that for reading one from
memory. The only difference is that the data word to be written is first loaded into the MDR, the
write command is issued. As an example, assumes that the data word to be stored in the memory
is in register R1 and that the memory address is in register R2.

The memory write operation requires the following sequence:

1. MAR [R2]

2. MDR [R1]

3. Write

4. Wait for MFC

Register Transfer Operation

Register transfer operations enable data transfer between various blocks connected to the
common bus of CPU. We have several registers inside CPU and it is needed to transfer
information from one register another. As for example during memory write operation data from
appropriate register must be moved to MDR. Since the input output lines of all the register are
connected to the common internal bus, we need appropriate input output gating. The input and
output gates for register Ri are controlled by the signal Ri in and Ri out respectively.Thus, when
Ri in set to 1 the data available in the common bus is loaded into Ri . Similarly when, Ri out is
set to 1, the contents of the register Ri are placed on the bus. To transfer data from one register to
other register, we need to generate the appropriate register gating signal
For example,
to transfer the contents of register R1 to register R2,
the following actions are needed: lEnable the output gate of register R1 by setting R1out to 1. --
This places the contents of R1 on the CPU bus. lEnable the input gate of register R2 by setting
R2 in to 1. -- This loads data from the CPU bus into the register R2.
Performing the arithmetic or logic operation: l

Generally ALU is used inside CPU to perform arithmetic and logic operation. ALU is a
combinational logic circuit which does not have any internal storage. Therefore, to perform any
arithmetic or logic operation (say binary operation) both the input should be made available at
the two inputs of the ALU simultaneously. Once both the inputs are available then appropriate
signal is generated to perform the required operation. We may have to use temporary storage
(register) to carry out the operation in ALU . The sequence of operations that have to carried out
to perform one ALU operation depends on the organization of the CPU. Consider an
organization in which one of the operand of ALU is stored in some temporary register Y and
other operand is directly taken from CPU internal bus. The result of the ALU operation is stored

in another temporary register Z

Therefore, the sequence of operations to add the contents of register R1 to register R2 and store
the result in register
R3 should be as follows:
1. R1out, Yin

2. R2out, Add, Zin

3. Zout, R3in

General Register organization

• Generally CPU has seven general registers. Register organization show how registers
are selected and how data flow between register and ALU. A decoder is used to select a
particular register.The output of each register is connected to two multiplexers to form
the two buses A and B. The selection lines in each multiplexer select the input data for
the particular bus.
 • The A and B buses form the two inputs of an ALU.The operation select lines decide the
operation to be performed by ALU. The result of the operation is available at the output
bus. The output bus connected to the inputs of all registers, thus by selecting a destination
register it is possible to store the result in it.

EXAMPLE:
To perform the operation R3 ← R1+R2 We have to provide following binary selection
variable to the select inputs.

1. SEL A : 001 -To place the contents of R1 into bus A.

2. SEL B : 010 - to place the contents of R2 into bus B
3. SEL OPR : 00010 – to perform the arithmetic addition A+B
4. SEL REG or SEL D : 011 – to place the result available on output bus in R3.

CONTROL WORD

• The combined value of a binary selection inputs specifies the control word.
• It consist of four fields SELA, SELB,and SELD or SELREG contains three bit each and
SELOPR field contains five bits thus the total bits in the control word are 14-bits.
 3 3 3 5

SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

Encoding of ALU operations

 OPR
Select Operation
Symbol
00000 Transfer A
TSFA
00001 Increment A
INCA
00010 ADD A + B
ADD
00101 Subtract A - B
SUB
00110 Decrement A
DECA
01000 AND A and B
AND
01010 OR A and B
OR
01100 XOR A and B
XOR
01110 Complement A
COMA
10000 Shift right A
SHRA
11000 Shift left A
SHLA

Symbolic Designation
Microoperation SELA SELB SELD OPR
Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
MICROOPERATION SEL A SEL B SEL D SELOP CONTROL WORD
OR R
SELREG

R2 = R1+R3 R1 R3 R2 ADD 001 011 010 00010

Stack Organization

• The stack in digital computers is a group of memory locations with a register that
holds the address of top of element.
• There are many real-life examples of a stack. Like A pile of books, a stack of
dinner plates.
• Stack is also known as the Last In First Out (LIFO) list. It is the most important
feature in the CPU. It saves data such that the element stored last is retrieved
first. A stack is a memory unit with an address register. This register influence the
address for the stack, which is known as Stack Pointer (SP). The stack pointer
continually influences the address of the element that is located at the top of the
stack.
• It can insert an element into or delete an element from the stack. The insertion
operation is known as push operation and the deletion operation is known as pop
operation. In a computer stack, these operations are simulated by incrementing
or decrementing the SP register.
 �Register Stack
The stack can be arranged as a set of memory words or registers. Consider a
64-word register stack arranged as displayed in the figure. The stack pointer
register includes a binary number, which is the address of the element present at
the top of the stack. The three-element A, B, and C are located in the stack.

The element C is at the top of the stack and the stack pointer holds the address of C
that is 3. The top element is popped from the stack through reading memory word at
address 3 and decrementing the stack pointer by 1. Then, B is at the top of the stack
and the SP holds the address of B that is 2. It can insert a new word, the stack is
pushed by incrementing the stack pointer by 1 and inserting a word in that incremented
location.

� The stack pointer includes 6 bits, because 26 = 64, and the SP cannot exceed 63 (111111
in binary). After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 =
1000000). SP holds only the six least significant bits. If 000000 is decremented by 1 thus
the result is 111111.
� Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is
null, then the one-bit register ‘EMTY’ is set to 1. The data register DR holds the binary
information which is composed into or readout of the stack.
� First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not
full (FULL = 0), a new element is inserted using the push operation.
The push operation is executed as follows −
� SP←SP + 1 It can increment stack pointer
� M[SP] ← DR It can write element on top of the stack If (SP = 0) then (FULL ← 1)Check
if stack is full
� EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved in
the SP. The word from DR is inserted into the stack using the memory write operation.
The first element is saved at address 1 and the final element is saved at address 0. If the
stack pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the condition
when the SP was in location 63 and after incrementing SP, the final element is saved at
address 0. During an element is saved at address 0, there are no more empty registers in
the stack. The stack is full and the ‘EMTY’ is set to 0

A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation includes the following sequence of micro-operations
� DR←M[SP] It can read an element from the top of the stack
� SP ← SP – 1 It can decrement the stack pointer
� If (SP = 0) then (EMTY ← 1) Check if stack is empty
� FULL ← 0 Mark the stack not full
� The top element from the stack is read and transfer to DR and thus the stack pointer is
decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to
1. This is the condition when the element in location 1 is read out and the SP is
decremented by 1.

Memory Stack
A stack can exist as a stand-alone unit as in Fig or can be implemented in a random-
access memory attached to a CPU. The implementation of a stack in the CPU is done by
assigning a portion of memory to a stack operation and using a processor register as a
stack pointer.
�
The stack pointer SP points at the top of the stack. The three registers are connected to a
common address bus, and either one can provide an address for memory.
�
PC is used during the fetch phase to read an instruction. AR is used during the execute
phase to read an operand.
�
SP is used to push or pop items into or the stack. As shown in Fig. , the initial value of SP
is 4001 and the stack grows with decreasing addresses.
�
Thus the first item stored in the stack is at address 4000, the second item is stored at
address 3999, and the last address that can be used for the stack Is 3000.
�
We assume that the items in the stack communicate with a data register DR .
 A new item is inserted with the push operation as follows:
� SP ← SP – 1
� M[SP] ← DR
� The stack pointer is decremented so that it points at the address of the next word. A
memory write operation inserts the word from DR into the top of the stack

A new item is deleted with a pop operation as follows:

DR ← M[SP]
SP ← SP + 1

Addressing Modes:

The most common addressing techniques are:

m Immediate
m Direct
m Indirect

m Register

m Register Indirect

m Displacement

To explain the addressing modes, we use the following notation:

A = contents of an address field in the instruction that refers to a memory
R = contents of an address field in the instruction that refers to a register
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of location X
Immediate Addressing:
The simplest form of addressing is immediate addressing, in which the operand is actually
present in the instruction:
OPERAND = A
This mode can be used to define and use constants or set initial values of variables.

Direct Addressing:
A very simple form of addressing is direct addressing, in which the address field contains the
effective
address of the operand:
EA = A
It requires only one memory reference and no special calculation.
Indirect Addressing:

With direct addressing, the length of the address field is usually less than the word length, thus
limiting the address range. One solution is to have the address field refer to the address of a
word in memory, which in turn contains a full-length address of the operand. This is know as
indirect addressing:
EA = (A)

Register Addressing:
Register addressing is similar to direct addressing. The only difference is that the address field
referes to
a register rather than a main memory address:
EA = R
The advantages of register addressing are that only a small address field is needed in the
instruction and no memory reference is required. The disadvantage of register addressing is
that the address space is very limited.
Register Indirect Addressing:
Register indirect addressing is similar to indirect addressing, except that the address field refers
to a register instead of a memory location. It requires only one memory reference and no special
calculation.
EA = (R)
Register indirect addressing uses one less memory reference than indirect addressing.
Because, the first information is available in a register which is nothing but a memory address.
From that memory location, we use to get the data or information. In general, register access is
much more faster than the memory access.

Diaplacement Addressing:
A very powerful mode of addressing combines the capabilities of direct addressing and register
indirect addressing, which is broadly categorized as displacement addressing:
EA = A + (R)

Three of the most common use of displacement addressing are:

L

Relative addressing
l Base-register addressing

l Indexing

Relative Addressing:
For relative addressing, the implicitly referenced register is the program counter (PC). That is,
the current instruction address is added to the address field to produce the EA. Thus, the
effective address is a displacement relative to the address of the instruction.

Base-Register Addressing:

A register to hold the base address of a segment, and the instruction must
reference it explicitly.

Indexing:
The address field references a main memory address, and the reference register contains a
positive displacement from that address.