UNIT-1

NUMBER SYSTEM AND COMBINATIONAL LOGIC

LECTURE-10
HALF ADDER AND FULL ADDER
In data processing, addition of operands is one of the most basic operations performed by different
electronic devices like computers, calculators, etc. The electronic circuit that is designed to perform the
addition of two or more numbers, more specifically binary numbers, is known as adder. As we know,
the logic circuits use binary number system to perform the operations, hence the adder is also referred to
as a binary adder.
Depending on the number of binary digits that the adder circuit can add, adders (or binary adders) are of
two types:
• Half Adder
• Full Adder
Half Adder?

Half adder is a combinational logic circuit that is designed to add two binary digits. The half adder
provides the output along with a carry (if any). The half adder circuit can be designed by connecting an
XOR gate and one AND gate.

It has two input terminals and two output terminals for sum (S) and carry (C).

Half Adder Truth Table

If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder with
A, B as inputs and Sum, Carry as outputs can be tabulated as follows.

If you observe the truth table, the sum output of the binary addition carried out above is similar to that of
an Ex-OR operation, while the carry output is similar to that of an AND operation. The same can be
verified with help of Karnaugh Map.
We can derive the Boolean Expression of Sum as follows:

Sum = A’ B + A B’

Sum = A ⊕ B

Hence, the logic diagram for sum is shown below.

We can derive the Boolean Expression of Carry as follows:

 Carry = A B

The logic diagram for carry is shown below.

If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR of A
and B and logic function to calculate carry C is AND of A and B. Combining these two, the logical
circuit to implement the combinational circuit of Half Adder is shown below.

Half Adder using NAND Gates

Five NAND gates are required in order to design a half adder. The circuit to realize half adder using
NAND gates is shown below.

Half Adder Logic diagram by using NAND gate

Half Adder using NOR Gates

Five NOR gates are required in order to design a half adder. The circuit to realize half adder using NOR
gates is shown below

Limitations of Half Adder

The reason these simple binary adders are called Half Adders is that there is no scope for them to add
the carry bit from previous bit. This is a major limitation of half adders when used as binary adders
especially in real time scenarios which involves addition of multiple bits. To overcome this limitation,
full adders are developed.

Full Adder Circuit

A Full Adder is a Combinational Logic Circuit which performs binary addition on two-digit numbers.
Full adders are complex and difficult to implement when compared to half adders.

Full adder is a digital circuit used to calculate the sum of three binary bits, which is the main difference
between this and half adder. Two of the three bits are same as before which are A, the augend bit and B,
the addend bit. The additional third bit is carry bit from the previous stage and is called Carry–in,
generally represented by CIN. It calculates the sum of three bits along including the carry. The output
carry is called Carry–out and is represented by COUT.

The block diagram of a full adder with A, B and CIN as inputs and S, COUT as outputs is shown below
Full Adder Truth Table

The truth table for full adder is shown below.

Based on the truth table, the Boolean functions for Sum (S) and Carry–out (COUT) can be derived using
K–Map.
The K-Map for Sum output (S) of a Full Adder is shown below:

Using the truth table and the above K-Map, the Boolean Expression of Sum (S) output of a Full Adder
can be derived as:

S = A’ B’ CIN + A’ B C’IN + A B’ C’IN + A B CIN

S=A’(B’CIN+B C’IN)+A(B’C’IN+B CIN)

S=A’(B⊕ C) + A (B ⊕ C)
S=A⊕ B⊕ C

The K-Map for Carry output (COUT) of a Full Adder is shown below:
The simplified Boolean equation for COUT is:

COUT = A B + A CIN + B CIN

Full Adder Circuit Diagram

Implementation of Full Adder using Half Adder

We know the equations for S and COUT of a Full Adder from earlier calculations as:

S = A’ B’ CIN + A’ B C’IN + A B’ C’IN + A B CIN

COUT = A B + A CIN + B CIN

we can rewrite COUT as follows:

COUT = A’B CIN +AB’ CIN +AB CIN +AB CIN
COUT = CIN ( A’B +AB’) +AB (CIN +C’IN )
COUT = CIN ( A⊕ B) +AB

The Block diagram of the full adder using two half adders is shown in Figure 4:

The logic diagram of the full adder using two half adders is shown in Figure-3:
From the logic diagram of the full adder using half adders, it is clear that we require two XOR gates,
two AND gates and one OR gate for the implementation of a full adder circuit using half-adders.

However, the implementation of full adder using half adder has a major disadvantage that is the
increased propagation delay. That means, the input bits must propagate through several gates in
succession that increases the total propagation delay of the full adder circuit

Full Adder using NAND Gates

As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement any logic
design. The circuit of full adder using only NAND gates is shown below.

Full Adder using NOR Gates

Difference between Half Adder and Full Adder

The following table shows the main differences between half adder and full adder circuit.