ECE 310

Microprocessors and
Microcontrollers
Introduction to Microprocessors (2)
Mohammed Sharaf Sayed
[email protected]
 Lecture Outline

• What is Microprocessor?
• Address Bus, Data Bus, and Control Bus
• Tristate Bus
• Clock Generation
• Connecting Microprocessor to I/O Devices
o I/O Mapped I/O Interface
o Memory Mapped I/O Interface
• Data Transfer Schemes
o Parallel Data Transfer
o Serial Data Transfer
• Architectural Advancements of Microprocessors
o Pipelining
o Cache Memory
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 What is Microprocessor?

• Microprocessor is mainly ALU and Control Unit

integrated on a single IC chip.
• Microcomputer is mainly ALU, Control Unit and
Memory integrated on a single IC chip.
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 What is Microprocessor?

• The microprocessor chip has to be interfaced to

memory and I/O units to work as a computer for
any application.
• Address, data and control signals are required to
interface the microprocessor to memory and I/O
devices.
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 Address Bus, Data Bus, and Control Bus

• A bus is defined as a path over which digital

information is transferred from any of the several
sources to any of the several destinations.
• A microprocessor chip has an address bus, a data bus,
and a control bus associated with it.
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 Address Bus, Data Bus, and Control Bus

• The data bus is bi-directional as the microprocessor

accepts as well as sends data
• The address bus is unidirectional since address
locations are sent by microprocessor to memory and
I/O devices.
• The control signals :
– like Read from memory or I/O or Write to memory or I/O are
output by microprocessor to memory or I/O devices.
– like Interrupt Request, DMA request, Reset, Halt, etc. are
sent to microprocessor by I/O devices.
 The control bus is bi-directional, however any particular line
will have information flow in one direction only.
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 Tristate Bus

• Tristate gates have an extra input called enable/disable,

which permits the logic gate to either behave normally
or else disconnect the output of the gate from rest of
7 the output.
 Clock Generation

• The clock generator chip had two pins between which a

crystal or an RC circuit could be connected for the
generation of basic frequency desired.
• However, microprocessors, that were designed after
1978 (Intel 8085, M6809, etc.) had the clock generator
circuit embedded in the microprocessor chip.
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 Connecting Microprocessor to I/O Devices

• I/O Mapped I/O Interface:

 I/O devices are identified by port numbers and memory
locations by addresses.
 The memory read/write operations and I/O read/write
operations are performed by different software instructions.
 In case of read/write from an I/O device, the I/O signal is ON
and the address on the address bus is decoded as the port
number and an I/O device is selected.
 In case of read/write from memory, the MEMORY signal is
ON and a particular location of memory is selected.

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 Connecting Microprocessor to I/O Devices

• Because of separate memory and I/O signals, there is

no confusion between device address (port number)
10 and memory address.
 Connecting Microprocessor to I/O Devices

• Memory Mapped I/O Interface:

 There is no signals to differentiate between I/O and
MEMORY access.
 It means that I/O addresses (port numbers) and memory
addresses must not be the same.
 Using the same memory read/write instructions, which are
quite versatile and powerful in general.
 More compact and more efficient handling of I/O devices can
be achieved if they are interfaced to microprocessor in this
way.

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 Connecting Microprocessor to I/O Devices

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 Data Transfer Schemes

• Data transfer schemes depend heavily on the

environment (on-line or off-line processing), type of
I/O device (capable of parallel or serial data transfer,
synchronous or asynchronous) and the application.

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 Data Transfer Schemes

• Parallel Data Transfer (Programmed I/O):

– Depending on the type of the device, data transfer may be
synchronous or asynchronous.
– Synchronous data transfer is used when
the I/O device matches in speed with
the microprocessor.
– When the I/O device is slower than the
microprocessor, asynchronous data
transfer is used.
– This scheme is quite inefficient, since
the microprocessor is kept busy for the
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slower I/O device.
 Data Transfer Schemes

• Parallel Data Transfer (Interrupt I/O):

– The microprocessor do its job while the device is getting
ready and when the device is ready, the microprocessor can
transfer the data.
– Interrupt is the facility provided by the microprocessor to
the outside environment by which the attention of the
microprocessor can be diverted to do some higher priority
job.
– The microprocessor should scan the signal on the interrupt
pin during every machine cycle. When the interrupt signal is
present, it should suspend the current job.
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 Data Transfer Schemes

• Parallel Data Transfer (Interrupt I/O):

– The stack is used to
store the status of
the suspended job.
– The microprocessor
services the
interrupt request
by executing an
Interrupt Service
Routine.

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 Data Transfer Schemes

• The operation sequence for interrupt operation:

a) Normal program execution by microprocessor.
b) Microprocessor initiates the device through a code/signal
(e.g. start convert signal to initiate ADC conversion).
c) The device when ready to send the data sends an interrupt
signal on one of the interrupt pins.
d) Microprocessor checks the validity of interrupt request by
checking whether
» the interrupt system is enabled.
» the particular interrupt is not disabled.
» any higher priority interrupt is not pending or being
processed.

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 Data Transfer Schemes

e) If an interrupt request is valid, the microprocessor

» completes the current instruction execution.
» saves the status register and Program Counter(PC) in
stack.
» issues interrupt acknowledgement signal.
» determines the address of interrupt servicing routine
and stores the starting address in PC.
f) The program branches to Interrupt Servicing Routine.
g) The last instruction of Interrupt Servicing Routine is
‘Return’. When this instruction is executed, the PC and the
Status Register are loaded back from stack.
h) The normal program execution is resumed.

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 Data Transfer Schemes

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 Data Transfer Schemes

• Parallel Data Transfer (Direct memory access):

– In programmed I/O and interrupt I/O, data is transferred to
the memory through the microprocessor registers.
– This process is quite uneconomical for bulk data transfer.
– In such cases the device is allowed to transfer the data
directly to memory, bypassing the microprocessor.
– The I/O device requests the microprocessor for Direct
Memory Access (DMA) by sending a signal on a special pin.

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 Data Transfer Schemes

• The operation sequence in case of Direct Memory

Access is as follows:
1. The microprocessor checks for DMA request signal once in
each machine cycle.
2. The I/O device sends signal on DMA request pin.
3. The microprocessor tristates address, data and control
buses.
4. The microprocessor sends acknowledgement signal to I/O
device on DMA acknowledgement pin.
5. The I/O device uses the bus system to perform data
transfer operation on memory.
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 Data Transfer Schemes

• The operation sequence in case of Direct Memory

Access is as follows:
6. On completion of data transfer, the I/O device withdraws
DMA request signal.
7. The microprocessor continuously checks the DMA request
signal, when the signal is withdrawn, the microprocessor
resumes the control of buses and resumes normal
operation.

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 Data Transfer Schemes

• Serial Data Transfer:

– The data is transferred bit by bit on a single line.
– This minimizes the number of interconnecting wires.
– The microprocessor providing serial data transfer facility will
have two pins for input and output of serial data and special
software instructions to affect the data transfer.

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 Architectural Advancements of Microprocessors

• Nowadays, microprocessors have several techniques

to increase its speed such as pipelining, cache
memory, multitasking, and multiprocessing.
• Pipelining:
– Pipelining in computer is used to enhance the execution
speed.
– A number of processing elements or processors are used in
pipelining.
– For a single task there is no advantage derived from a
pipelined processor.
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 Architectural Advancements of Microprocessors

• Pipelining:
– Let us consider an example in which there is continuous flow
of tasks T(1), T(2), T(3), T(4) … each of which can be divided
into four sub-tasks [e.g., task T(1) will have sub-tasks T1(1),
T2(1), T3(1) and T4(1)] as before.
– Now the pipeline will look like.

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 Architectural Advancements of Microprocessors

• Pipelining:
– The task T(1) consisting of sub-tasks T1(1), T2(1), T3(1) and
T4(1) will get completed at the end of cycle 4.
– The task T(2) consisting of sub-tasks T1(2), T2(2), T3(2) and
T4(2) will get completed at the end of cycle 5.
– Similarly task T(3) will get completed at the end of cycle 6.
– Thus all tasks after task T(1) take one cycle to get completed.
– Thus for subsequent tasks, 4 times enhancement in speed
has been achieved.
– If the number of tasks are very large, the total speed
enhancement (including task T(1)) approximates to 4.
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 Architectural Advancements of Microprocessors

• Pipelining:
– The pipelining concept has been adopted in the instructions
execution; ‘Instruction Pipeline’.
– An instruction execution contains the following four
independent sub-tasks.
(a) Instruction Fetch (b) Instruction Decode
(c) Operand Fetch (d) Execute
– If four hardware modules or processing elements are
designed to execute these four sub-tasks, 4 times
enhancement in the execution speed is possible.
– This however is the maximum theoretical enhancement
possible since not all instructions are independent.
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 Architectural Advancements of Microprocessors

• Pipelining:
– For dependent instructions, Control unit inserts stall or
wasted clock cycles into pipeline until such dependencies
are resolved.
– Example: the result of instruction I1 is the operand for
instruction I2, then the operand fetch for I2 has to wait for I1
to get completed.
– Branch instructions can also affect the processing pipeline.
– Example, if instruction I2 is a branch instruction, the
execution of instructions I3 and I4 in the pipeline becomes
meaningless as program will branch to a new location.
In such cases, the entire pipeline must be flushed.
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 Architectural Advancements of Microprocessors

• Pipelining:
– Intel 8086, 80186, 80286 and 80386 have a 2-stage pipeline,
i.e. Bus Interface Unit (Instruction Fetch) and Execution Unit
(Instruction Execution).
– Intel 80486 has a 5-stage instruction pipeline whereas
Pentium processor has a 20-stage instruction pipeline.

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 Architectural Advancements of Microprocessors

• Cache Memory:
– Increasing memory throughput will increase the execution
speed of the processor.
– One or more fast buffers named cache between the
processor and the main memory are used to increase the
execution speed.
– The cache memory has cycle time compatible with the
processor speed.
– The cache memory consists of a few kilobytes of high speed
Static RAM (SRAM), whereas the main memory consists of a
few Megabytes to Gigabytes of slower but cheaper Dynamic
RAM (DRAM).
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 Architectural Advancements of Microprocessors

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 Architectural Advancements of Microprocessors

• Cache Memory Operation (read):

– When the CPU wants to read a byte or word, it outputs
address on the Address Bus.
– The cache controller checks whether the required contents
are available in cache memory.
– If the addressed byte/word is available in cache memory,
the cache controller enables the cache memory to output
the addressed byte/word on Data Bus.
– If the addressed byte/word is not present in cache memory,
the cache controller enables the DRAM controller.
– The DRAM controller sends the address to main memory to
get the byte/word.
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 Architectural Advancements of Microprocessors

• Cache Memory Operation (read):

– Since DRAM is slower, this access will require some wait
states to be inserted.
– The byte/word which is read is transferred to CPU as well as
to cache memory.
– If CPU needs this byte/word again, it can be accessed
without any wait state.
 The percentage of accesses where the CPU finds the desired
byte/word in cache is called hit rate.

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 Architectural Advancements of Microprocessors

• Cache Memory Operation (write):

– If the cache controller finds that the addressed byte/word is
present in the cache memory then the controller will write
the new byte/word to the cache memory without any wait
state.
– It intimates the CPU that the write operation is complete.
– The cache controller then writes the byte/word to main
memory.
– This methodology is called the Posted Write Through
Method.
– The write to main memory is transparent to the CPU.

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 Architectural Advancements of Microprocessors

• Cache Memory Operation (Cache Directory):

– To keep track of which main memory locations are currently
present in cache memory, the cache controller uses a cache
directory.
– Each location in the cache is represented by an entry in the
directory.
– The exact format of the cache directory depends on the
cache scheme used.

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 Architectural Advancements of Microprocessors

• Cache Memory:
– Pipelined CPUs access memory from multiple points in the
pipeline.
– Modern processors have incorporated both specialized
caches as well as cache hierarchy.
– Different physical caches for each of these points are used in
the architecture.

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 Lecture Summary
• We have discussed the following topics:
 What is Microprocessor?
 Address Bus, Data Bus, and Control Bus
 Tristate Bus
 Clock Generation
 Connecting Microprocessor to I/O Devices
o I/O Mapped I/O Interface
o Memory Mapped I/O Interface
 Data Transfer Schemes
o Parallel Data Transfer
o Serial Data Transfer
 Architectural Advancements of Microprocessors
o Pipelining
o Cache Memory
37
 Mohammed Sharaf Sayed
[email protected]