EE 2101 Experiment 1 IIT Patna

Study of Capacitance in AC Circuits

Experiment No 1 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours

1.1 Objective:
(i) To study the current voltage relationship in an ac circuit containing a capacitance and a
resistance in series.
(ii) To study the variation of reactance of the capacitor with the frequency of the ac source and
hence determine the capacitance
(iii) To draw the phasor diagram and hence to determine the loss factor of the capacitor
(iv) Study the frequency response of RC circuit

Figure 1.1 RC circuit

1.2 Apparatus: (i) Paper capacitor (ii) Carbon resistance (iii) Function generator (iv)
Oscilloscope or electronic voltmeter

1.3 Procedure & Experimental Results:

I Study the current voltage relationship and variation of reactance with frequency
(objective 1 and 2)
1. Set up the circuit as shown in figure 1.1. The resistance and capacitance should be chosen so
that VR and Vc are in same order. You may chose a frequency of 500 Hz, R=100 ohm and
capacitor as supplied during the class. Set the output voltage of function generator
conveniently low value. Measure the rms voltage VR and Vc .
2. Keeping the frequency constant increase the input voltage V in several steps up to a
convenient value. At each step measure VR and Vc and write in the table 1.1. Also calculate
current at each step.

Table 1.1A VR versus Vc data

Frequency of ac source f =….. Hz R=…… Ohm
Input Voltage Voltage across R Voltage across C I= VR/R
V( volt) VR(volt) VC (volt) (amp)
….. …… …… ….
…... …… …… .....

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 Experiment 1 IIT Patna

3Make similar table 1.1B, 1.1C etc for other frequencies. You may start from 500 Hz and go
up to 3 KHz in step (at least do for five different frequencies). Plot VC – I for each frequency.
4 For each frequency the slope of the VC – I straight line gives 1/ZC and may be calculated
using table 1.2.
Table 1.2 Determination of the capacitive reactance at different frequencies

Frequency f (Hz) ∆VC (from VC – I plot) Corresponding ∆I Slope

(Volt) (from VC – I plot) (1/ZC=∆I/∆VC)
(amp)
….. …… …… ….
…... …… …… .....

5. Plot 1/ZC versus f and from the plot calculate the value of C.
Table 1.3 Determination of the capacitance C from 1/ZC - f plot

∆(1/ZC) Corresponding ∆f (Hz) Slope m`= ∆(1/ZC)/ ∆f C=m`/2π

…..... …… ……… …......

6. Plot XC against f. What is the nature of the graph?

II Draw the phasor diagram (Objective 3)

7. Draw the phasor diagram using V, VR and VC .Draw the diagram for at least three sets of
frequency.
Table 1.4 Data for phasor diagram

Choice of scale for phasor diagram: 1cm represents … volt

No of sets Frequency, f (Hz) Input voltage V(volt) Voltage across R Voltage
VR (volt) across C-r
(volt)
I ………. …… ……… …......
II
III

No of sets f (Hz) Phasor length of Phasor length of VR Phasor

input voltage (cm) (cm) length of
VC (cm)
I ………. …… ……… …......
II
III

8. Calculate the loss factor.

Table 1.5 Determination of phase angle (the angle by which current leads the source
voltage), loss factor from phasor diagram.
Prepare appropriate table
III Draw the frequency response of the circuit
9. Derive the transfer function of the system in S domain where the output is (i) voltage across
R, (ii) voltage across C.
10. Fixed a convenient input voltage. Vary the input frequency from very low to very high,
measure amplitude and phase angle of output voltage.

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 Experiment 1 IIT Patna

Table 1.6A Input output voltage amplitude and phase

Input voltage……… V, Resistance …… ohm, Capacitance ……..microFarad
Input Input Amplitude Amplitude Phase angle Phase angle across
frequency amplitude across across across Capacitance (deg)
(Hz) (volt) resistance capacitance resistance (deg)
(volt) (volt)
…..... …..... …..... …..... …..... ….....
……. ……. ……. ……. ……. …….
……. ……. ……. ……. ……. …….

Table 1.6B Table for drawing Bode plot

frequency TF (against TF (against TF (against TF (against

(Hz) capacitor) capacitor) resistor) gain resistor) Phase
gain in dB Phase angle in dB angle in deg
in deg
…..... …..... …..... …..... ….....
……. ……. ……. ……. …….
……. ……. ……. ……. …….

11. Draw Bode plot when (i) output voltage is taken across capacitor, (ii) output voltage is taken
across capacitor.
12. Can the circuit be used as a low pass filter? What is the bandwidth of the system? What is the
cut off frequency of the circuit?

1.4 Few Questions for Viva Voce

(i) Can you perform the similar experiment using the resistance and inductance in
series? What will be the current voltage characteristics? Can you determine the
value of inductance from that experiment? What will be the frequency response
of the circuit? Can it be used as high pass filter?
(ii) Can you perform the experiment with an ac voltage having a triangular
waveform?
(iii) What is leakage resistance of a capacitor?
(iv) How do you account for the losses in an imperfect capacitor?
(v) At what angular frequency in Bode plot will theta will be equal to 45 degree?
(vi) What do you mean by loss factor and loss angle?
(vii) What will be the reading of a DC voltmeter connected across the sinusoidal
voltage source?
(viii) What is admittance? What is susceptance?
(ix) What type of capacitor you have used in the experiment?
(x) What is loss angle of an inductor?
(xi) Is the inductance coil resistance r is same at all frequencies?

1.5 Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) Katsuhiko Ogata, “Modern Control Engineering”, Prentice-hall Of India Pvt Ltd, 4th edition, 2007.
(iii) C.K.Alexander and M.N.O.Sadiku, “Fundamentals of Electric Circuits”, Tata Mgraw Hill, 3rd edition,
2007.

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Indian Institute of Technology Patna
Dept. of Electrical Engineering
Bihta, Patna, Bihar – 801103
EE2101 – Analog Circuits Lab

Experiment- 2: Characterization of an NMOS

1. Objectives: The following I-V curves need to be traced and characteristic parameters to be
calculated from them

(i) ID vs VGS for three different values of VDS ( = 1 V, 5 V and 7 V) for VGS ≤ 5 V. (see Fig. 1)
(ii) Using the previous ID vs VGS curves determine: (a) VTH
(iii) ID vs VDS for four different values of VGS ( = 1 V, 2 V, 3 V and 4 V) for VDS ≤ 8 V.
(iv) Using the previous ID vs VDS curves determine: (a) Ron (in deep triode region), (b) Channel
length modulation coefficient, λ (in saturation region), (c) ro (in saturation region), (d) β (see
the formula below), (e) transconductance, gm.
(v) ID vs Vs curve for a diode connected NMOS and finding VTH from it (assuming λ=0). Take
VDD=3 V.

2. Instruments/Compenents Required: Multi output Power supply, Multimeter, Breadboard, N-

Type MOSFET (BS107A/2N7000), Resistance and Connecting wires as per requirements.

3. Circuit Diagrams:

Fig. 1 For objectives (i) and (ii) Fig. 2 For objectives (iii) and (iv)

Fig. 3 For objectives (v)

 4. Useful Equations:

W
1. β = µnCox
L

Drain current without channel length modulation,

1 W
 2 µnCox L [2(VGS − VTH )VDS − VDS ], in triode
2

2. ID = 
 1 µnCox W (VGS − VTH ) 2 , in saturation
 2 L
1
3. For (iv)(a): Ron for VDS  2(VGS − VTH ), i.e in deep triode
W
µnCox (VGS − VTH )
L
1 + λVDS 2
4. =
For (iv)(b) : I D 2 I D1 .
1 + λVDS 1
∆VDS 1
5. =
For (ii)(c): rO =
∆I D λ ID
W W
=
6. For (ii)(d): gm 2 µnCox= I D µnCox (VGS − VTH ).
L L

Note: Do not keep ID more than 250mA for longer duration.

 Experiment 3 IIT Patna

Construct a Common Emitter Transistor

Amplifier and Study its Performance

Experiment No 3 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours

3.1 Objective:
(i) Design a RC coupled amplifier.
(ii) Draw frequency response of the amplifier and hence determine the bandwidth.
(iii) Study the effect of negative feedback on voltage gain and bandwidth of the amplifier.

Figure 3.1 Single stage RC coupled amplifier

3.2 Apparatus: (i) a npn transistor (SL100B) (ii) signal generator (iii) DC voltage generator (iv)
Resistors as calculated (v) Capacitors as calculated (vi) Electronics Voltmeter

3.3 Procedure & Experimental Results:

1. Determine the value of resistors and capacitors for mid frequency voltage gain =100. You
may take β =……. hie = 1KΩ , VCC=12V, Take collector power dissipation (say 50 mW) well
below the max rated value. You may take stability factor as S = β / 20 . Check / keep the max
power dissipation on each resistance well below the maximum allowed value (0.25W).
2. Set up the circuit with the calculated value of resistor and capacitor in bread board.

Table 3.1 Circuit Component Used

Mid band voltage gain(AVM )=100, hie =…., hfe=…., VCC=….V
Transistor Type Resistor Capacitors
Calculated Used Calculated Used

….. …… ……
…... …… ……

Table 3.2 Data for quiescent point

Vcc=12 V
VBG VCG VEG VCE VBE

….. …… ……

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EE 204 Experiment 3 IIT Patna

3. Apply alternating signal of small voltage (say 40mv) input.

4. With the help of CRO observe the input and output signal.
5. Keeping the value of input voltage constant vary the frequency from low (say 100 Hz) to very
high (say 10 MHz). Calculate the voltage gain at each frequency.

Table 3.3 Data for frequency vs gain curve

Input frequency Output Voltage Voltage gain

voltage (Vi)
….. …… ……
…... …… ……

6. Plot voltage gain against frequency on semi log graph paper. Calculate the bandwidth of the
transistor. Also draw one typical IP/OP wave form in graph paper.
Table 3.4 Determination of half power frequencies and BW

Mid frequency 0.707 AVM Lower half power Upper half power BW (f2- f1)
gain (AVM) (from frequency (f1Hz) frequency (f2Hz) (Hz)
graph)
….. …… …… …. ……

7. Choose the oscillator frequency in the mid frequency range. Keep it constant. Observe the
waveforms of the input voltage and the output voltage on the CRO screen simultaneously.
8. Set the input voltage amplitude to a low value (30mv) and measure the corresponding
amplitude of the output voltage.
9. Increase the input voltage amplitude in suitable steps and for each input voltage record the
amplitude of the output voltage. Continue the measurements till the output waveform is
clipped.
10. Plot the output voltage amplitude against the input voltage amplitude.
Table 3.5 Data for the amplifier linearity
Frequency = ….. Hz
input voltage amplitude Output voltage amplitude
….. ……
…… ……..

11. Disconnect the emitter bypass capacitor. Make a table similar to Table 3.3 to take the readings
for frequency versus gain. Plot frequency versus gain in same semilog graph paper. Also
make table similar to Table 3.4 to calculate BW. Compare the results with that of earlier case
(with emitter bypass capacitor connected).
3.4 Few Questions for Viva Voce
(i) What is the purpose of Cc and CE?
(ii) How does RE improve the stability?
(iii) What are the roles of R1 and R2?
(iv) What is the nature of frequency response of the amplifier?
(v) What is stability factor of an amplifier?
2.4. Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) J. Millman and C.C.Halkias, “Integrated Electronics”, Tata McGraw Hill Publishing Company
Limited, New Delhi, Tata McGraw-Hill edition 1991.

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 Experiment 4 IIT Patna

TO Draw the Characteristics of a JFET

Experiment No 4 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours
4.1 Objective:
(i) Draw the JFET characteristics
(ii) Determine the transconductance

Figure 4.1 JFET common source configuration

4.2 Apparatus: (i) a n channel silicone junction JFET (typically BFW11) (ii) signal generator
(iii) DC voltage source (iv) Resistors (RD=1M ohm and R1=1K ohm) (v) Electronics Voltmeter.
4.3 Procedure & Experimental Results:
1. Carefully identify the gate, source and drain leg of the transistor from manual. Make the
circuit as shown in figure 4.1. Make appropriate table (Table 4.1) for used circuit components
JFET ratings.
2. Adjust the voltage source VGG so that the gate to source voltage becomes VGS is zero volt.
3. Increase VDD in step from zero volt (upto VDS=15V) and measure VDS and voltage drop across
RD and hence determine the current ID.
Table 4.2 Data for drain characteristics
VGS=….. V
Drain to source Drain current (ID)
voltage (VDS) Increasing VDS Decreasing VDS Mean

VRD ID VRD ID

…... …… …… ……. ……. ……..

4. Decrease VGS in step of 0.5 volt (VGS= -0.5V, VGS= -1V) etc up to -2.5V. Repeat step 3.
5. Plot VDS versus ID for with VGS as a parameter.
6. Now keep VDS as 15V fixed. Vary VGS from -2.5V to 0 volt by varying VGG. Determine the
value of ID. Make appropriate table to capture the experimental data (table 4.3).
7. Plot the transfer characteristics (VGS versus IGsat).
8. Calculate transconductance (gm) from the graph for at least three pair of points. Calculate
mean gm. Make appropriate table (Table 4.4) for calculation.
4.4 Few Questions for Viva Voce
(i) What is the pintch off? Why input impedence of FET is very high?
(ii) Why FET is called a unipolar device? What are the advantages of FET over
bipolar transistor?
4.5 Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) J. Millman and C.C.Halkias, “Integrated Electronics”, Tata McGraw Hill Publishing Company
Limited, New Delhi, Tata McGraw-Hill edition 1991.

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 Experiment 5 IIT Patna

Study the Performance of A JFET Amplifier

Experiment No 5 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours
5.1 Objective:
(i) Design a common source JFET amplifier
(ii) Study the performance of designed amplifier

RD

D
C2
C1 VDD
G
V0

R1 S
Vi CS
RS

Figure 5.1 JFET as an amplifier

5.2 Apparatus: (i) A n channel silicone junction JFET (typically BFW11/ BFW10) (ii) Signal
generator (iii) DC voltage source (iv) Resistors and capacitors as calculated (v) Electronics Voltmeter.
5.3 Procedure & Experimental Results:
1. Calculate the resistors and capacitors and collect the nearest value of them. Make appropriate
table to report the calculated value and used value (Table 5.1). Also note down the type of
JFET, Maximum permissible VDS and maximum permissible ID.
2. Connect the circuit as shown in figure 5.1. Take VDD as 15 volt. Make appropriate table for
different DC voltages and currents (Table 5.2).
3. Give a small convenient ac voltage with low frequency as input. Measure the output voltage
and calculate the gain. Keeping the input voltage constant vary the frequency from very low
to very high calculate the gain for each step.

Table 5.3 Data for frequency vs gain

Input frequency Output Voltage Voltage gain
voltage (Vi)
….. …… …… ……..
…... …… …… ………

4. Plot the voltage gain against frequency in semilog graph paper.

5. Compare the results with that of obtained from CE amplifier (Experiment 3)

5.4 Few Questions for Viva Voce

(i) What is the bipolar junction transistor configuration analogous to the common
source mode of JFET?
(ii) Can you operate the JFET in common drain configuration? What is the analogous
mode of operation in BJT?
(iii) Is there any advantage of using JFET compare to BJT?
5.5 Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) J. Millman and C.C.Halkias, “Integrated Electronics”, Tata McGraw Hill Publishing Company
Limited, New Delhi, Tata McGraw-Hill edition 1991.

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 Experiment 6 IIT Patna

Study the Performance of an Integrator Using

OP AMP

Experiment No 6 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours
6.1 Objectives
(i) Study the performance of an integrator designed with OP AMP
(ii) Determine the value of capacitance

Figure 6.1 Integrator circuit using OP AMP

6.2 Apparatus (i) An Op AMP IC (typically 741C) (ii) DC stabilised power supply, (iii) Signal
generator (iv) Electronics voltmeter (v) CRO and (vi) few resistor and capacitor
6.3 Procedure & Experimental Results
1. Set up the circuit as shown in figure 6.1. Take the value of R=10K Ω and C=0.1 µF . Connect
suitable value of R1 and R2 for operating frequency greater that 200 Hz.
2. If offset null adjustment is required adjust it by using 10K Ω potentiometer. Prepare suitable
table for that.
3. Now from function generator put the 1V signal with the waveform (i) Sine (ii) Triangular (iii)
Ramp and (iv) Square wave. Draw the input and output waveform in graph paper.
4. Set the sine wave with the frequency as 200 Hz as input. Measure the input and output peak
voltage using CRO.
5. Increase the input frequency in suitable steps and repeat the step 4.
Table $$ Frequency response of the integrator
R=………, R1=………., R2=…………..
Input signal Input amplitude Output amplitude Abs(Vm/V0)
frequency (f) voltage (Vm) voltage (Vo)

6. Repeat the steps 1 to 5 for other value of R (6.8K, 4.7K, and 3.3K). Make similar tables.
7. Plot abs(Vm/V0) against f for each values of R and measure the slope (m) of the resulting
straight line in each case. Make suitable table to calculate the slope of the straight line.
8. Plot m against R. Calculate the capacitance value. Prepare suitable table.
6.4 Few Questions for Viva Voce
(i) What is the purpose of R1 and R2? What is the gain of this integrator circuit?
(ii) Can you design the experiments for measuring (a) input offset voltage (b) input
offset current (c) input bias current and (d) CMRR
(iii) Can you construct an integrator using simple R-C circuit?
(iv) What are SSI, MSI, LSI and VLSI?
6.5 Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) R. A. Gayakwad, “Op-amps and Linear Integrated Circuits”, Prentice Hall India, 2004.

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 Experiment 7 IIT Patna

Design a Wein-Bridge Oscillator

Experiment No 7 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 6 hours
7.1 Objective:
(i) Study of RC lead lag network
(ii) Construct a Wein Bridge oscillator

Vi
R V0

Fig 7.1 RC lead lag network Fig 7.2 Weing Bridge oscillator

7.2 Apparatus: (i) Power supply (ii) Op Amp (iii) resistors (typically R=15.9K, R2=470 ohm
and 1K pot) and capacitors (typically 0.01 µF ) (iv) Diodes (v) Electronics voltmeter (vi) CRO
7.3 Procedure & Experimental Results:
I Study of RC lead lag network (Objective 1)
1. Set up the circuit as shown in figure 7.1 using 0.01 µF and a resistance say 15.9K ohm. Make
a table to report the value of resistors and capacitors used to design circuit 7.1 (Table 7.1).
2. Switch on the ac input source and set its output voltage to a convenient value. Keeping Vi
constant vary the frequency from very low to very high. At different frequency measure the
voltage V0 and phase angle. Prepare appropriate table to report the observation (Table 7.2).
3. Plot the frequency versus gain and frequency versus phase angle between input and output
voltage. From the graph find out the phase cross over frequency and compare it with
theoretical value (Table 7.3).
II Wein Bridge Oscillator (Objective 2)
4. Design the circuit as shown in figure 7.2. Use the value of R3 =2.2K. Measure the frequency
and the amplitude of the output for at least five different positions of pot (Table 7.4).
5. Now Keeping the pot position fixed use different value of R3 (say 3.3K, 4.7K, 6.8K, 10K,
10K, 22K etc). Measure the output voltage and frequency for each case (Table 7.5).
6. Change the combination of C and R to obtain the output oscillation at least five different
frequencies in between 100 Hz to 100 KHz (Table 7.6).
7. Design the Wein Bridge oscillator to obtain $$ KHz ($$ = Group No) output frequency.
Solder the circuit in stripboard. The terminals which would be available are (i) +ve supply (ii)
–ve supply (iii) ground (iv) output (v) knob for varying output voltage.
7.4 Few Questions for Viva Voce
(i) What is Barkhausen criteria? What are the functions of the resistor R3 and two diodes?
(ii) What is the range of frequency usually generated by a Wein bridge oscillator?
(iii) What are the different oscillators used for sinusoidal output? Can you design them?
7.5 Reference
(i) D. Chattopadaya and P.C.Rakshit, “An advanced course in practical physics”, New Central Book
Egency Pvt Ltd, Kolkata, 8th edition 2007.
(ii) J. Millman and C.C.Halkias, “Integrated Electronics”, Tata McGraw Hill Publishing Company
Limited, New Delhi, Tata McGraw-Hill edition 1991.
(iii) R. A. Gayakwad, “Op-amps and Linear Integrated Circuits”, Prentice Hall India, 2004.

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 Experiment 8 IIT Patna

Design a Butterworth Filter

Experiment No 8 EE 2101 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours
7.1 Objective:
(i) Design second and forth order Butterworth low pass filter.

7.2 Apparatus: As required for the experiment.

7.3 Procedure & Experimental Results:

1. Calculate the components necessary to design a second order low pass active filter with the
cut off frequency $$ KHz ($$ = Group No). Please note that the gain of the filter should be
variable.
2. Derive the expression for voltage gain.
3. Tune the filter such that the pass band gain becomes 3.
4. Take readings necessary to draw the frequency response of the circuit. From the plot calculate
(i) cut off frequency, and (ii) slope of the decaying curve.
5. Design a forth order low pass filter with the same cut off frequency. Repeat the steps 2 to 4.
Note that two frequency response plots are to be superimposed in a same semi log graph
paper.

7.4 Few Questions for Viva Voce

(i) Why the filter designed in this experiment is called as active filter?
(ii) What are the advantages of active low pass filter compare to RC filter designed in
earlier experiment?
(iii) Can you design high pass and band pass active filters?
(iv) What are Butterworth polynomials?
(v) What are the different pole configurations in different order Butterworth filter?
(vi) Can you design odd order active filters?

7.5 Reference
(i) J. Millman and C.C.Halkias, “Integrated Electronics”, Tata McGraw Hill Publishing Company
Limited, New Delhi, Tata McGraw-Hill edition 1991.
(ii) R. A. Gayakwad, “Op-amps and Linear Integrated Circuits”, Prentice Hall India, 2004.

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EE 204 Question Bank IIT Patna

Question Bank for Exam 204

End Semester Exam EE 204 Analog Circuits Laboratory IIT Patna

Designed by Dr. Shovan Bhaumik Duration: 3 hours

I Experiments using simple circuit elements (resistor, capacitor and inductor)

(i) Study of inductance in ac circuit.
(ii) Investigation on parallel resonating circuit.
II Experiments on Diode and Transistor
(i) Half wave and full wave rectifier using semi conductor diode (including bridge
rectifier).
(ii) Output characteristics and transfer characteristics of a transistor in common emitter
configuration.
(iii) Determine the hybrid parameters of transistors using ac source.
III Experiments on Op Amp
(i) Op Amp as an inverting and non inverting amplifier.
(ii) Adder, subtractor, average, differentiator, integrator and logarithmic calculation using
Op Amp.
(iii) Design a circuit for the solution of simultaneous equations using Op Amp.
(iv) Measurement of CMRR of an Op Amp.
(v) D/A converter using Op Amp.
(vi) Half wave rectifier using Op Amp.
(vii) Square wave generator and triangular wave generator using Op Amp.
(viii) Voltage follower, differential amplifier, current to voltage, voltage to frequency
converter.
(ix) Any order low pass, high pass active filter.
(x) Band pass, band reject filter.
III Timer (555)
(i) Monostable, astable multivibrator.
(ii) Square wave generator.

Note: The question bank includes all the experiments performed in classes.

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Five Cycle Semi-Log

 1998 David Bourne