Chapter 4

Combinational Logic
 Combinational Circuits
„ Logic circuits for digital systems may be combinational
or sequential.
„ Combinational logic circuits
„ consist of logic gates
„ outputs = present combination of inputs
„ Sequential logic circuits
„ employ storage elements & logic gates
„ outputs are a function of the inputs & the state of
storage elements (a function of previous inputs)
 Block Diagram of Combinational Circuit
„ A combinational circuits
2 possible combinations of input values
n
„

n input Combinational m output

variables Logic Circuit variables

„ m outputs : m Boolean functions of n input

variables
„ Specific functions
„ Adders, subtractors, comparators,

decoders, encoders, and multiplexers

„ MSI circuits or standard cells
 Purpose of Analysis
„ The analysis of a combinational circuit
„ to determine the function that the circuit
implements.
„ Given a logic diagram. Find
„ make sure that it is combinational not

sequential
„ No feedback path
„ a set of Boolean functions
„ a truth table
„ a possible explanation of the circuit operation
 Analysis Procedure
„ Step 1. Make sure that the given circuit is
a combinational circuit
„ the circuit has logic gates
„ without feedback
„ without memory elements

„ Step 2. Obtain
„ the Boolean functions, or
„ the truth table (one by one)
 A Straight-Forward Procedure
F2 = AB+AC+BC
T1 = A+B+C
T2 = ABC
T3 = F2'T1
F1 = T3+T2

A B C F2 F2’ T1 T2 T3 F1 F2
0 0 0 0 1 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Truth Table

„ The truth table

 Design Procedure
„ The design procedure of combinational circuits
„ State the problem (system specifications)
„ determine the inputs and outputs
„ the input and output variables are assigned symbols
„ derive the truth table
„ derive the simplified Boolean functions of each inputs
„ draw the logic diagram and verify the correctness
# of gates # of inputs to gate
implementation
constraints : propagation time # of interconnections
driving capability of each gate
 Example: BCD Î Excess-3 (1/3)
BCD Î Excess-3
System A Conversion System B 1. Spec: BCD Î Excess-3
(BCD) circuit (Excess-3) 2. 4 inputs, 4 outputs
 Example: BCD Î Excess-3 (2/3)

w = A+BD+BC
K-map
x = B’D+B’C+BC’D
Karnaugh-map y = C’D’+CD
minimization z=D
 Example: BCD Î Excess-3 (3/3)
Logic diagram (not unique implementation)

w = A+BD+BC
x = B’D+B’C+BC’D’
y = C’D’+CD
z=D
 Adder
half adder
„ addition
↓
„ the most basic
full adder (FA)
arithmetic operation
↓… ↓ n
„ binary adder
n-bit binary adder (n FAs in
„ half adder cascade)
„ addition of 2 bits ↓
„ full adder subtractor (complementing
circuit)
„ addition of 3 bits
↓
„ (2 bits & a previous
adder-subtractor
carry)
 Half Adder (1/2)
„ Half adder (sum of two input bits)
„ 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10
„ two input variables: x, y
„ two output variables: C (carry), S (sum)
„ truth table

„S = x'y+xy'=x y (XOR)
„C = xy (AND)
 Half Adder (2/2)

carry sum

S = x'y+xy'
C = xy

Î not unique implementation

 Full Adder (1/3)
„ The arithmetic sum of three input bits
„ three input bits
„ x, y: two significant bits

„ z: the carry bit from the previous lower significant bit

„ two output bits: C, S

1. Specifications
2. Determine the inputs and
outputs
3. Derive the truth table
4. K-map minimization
5. Draw the logic diagram

One-bit adder
 Full Adder (2/3)
S C

S = x’y’z + x’yz’
+xy’z’ + xyz
C = xy + xz + yz
 Full Adder (3/3)
„ S = x'y'z+x'yz'+ xy'z'+xyz
„ C = xy + xz + yz
„ S = z⊕ (x⊕y)
= z'(xy'+x'y)+z(xy'+x'y)'= …
= xy'z+x'yz+ xy a half adder
another implementation
a full adder == 2 half adders + 1 OR gate
 A 4-bit Binary Adder
Don’t use the truth table
C3 C2 C1 C0 with 29 entries

4-bit binary
ripple-carry adder
Why?
C4 C3 C2 C1

(C1ÎC2 ÎC3 ÎC4)

C4 and C3 output the wrong value at the beginning (Îbehavior of hardware circuit)
But C4 becomes correct as soon as C3 is correct + a little delay.
C3 becomes correct as soon as C2 is correct + a little delay. ……
 Carry Propagation (1/2)
„ when the correct outputs are available
„ the critical path counts (the worst case)
„ (A1,B1,C1) > C2 > C3 > C4
„ > 8 gate levels

2x4=8 gates delay for carry bit in

a 4-bit adder. How about 8-bit adder?
 Carry Propagation (2/2)
S2
S0 A2
A0
B2
B0

C1 C3
C0
C2 a full adder
a full adder
A1 S1 A3
B1 B3

C2
C1 C3
a full adder a full adder
 Binary Ripple-Carry Adder
„ Carry propagation time
„ 2 gate levels for each FA
„ 2n gate levels for an n-bit binary ripple-carry
adder
„ low speed !

„ Improvements
„ Employ faster gates to reduce delays
Carry lookahead scheme (more cost, less delay)
„ Circuit complexity (cost) v.s. delay time (speed)
 Reduction of Carry Propagation Delay
„ employ faster gates
„ look-ahead carry (more complex mechanism,
yet faster)
„ carry propagate: Pi = Ai⊕Bi
„ carry generate: Gi = AiBi
„ sum: Si = Pi⊕Ci
„ carry: Ci+1 = Gi+PiCi Ci+1 must wait for Ci
„ C1 = G0+P0C0 Î break this waiting-data dependency

„ C2 = G1+P1C1 = G1+P1(G0+P0C0) Let C1, C2 and C3

= G1+P1G0+P1P0C0
all depend on C0 only

„ C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

 Carry Lookahead
Break the data dependency !!!
Let C1, C2 and C3 all depend on
C0 only.
„ C1 = G0+P0C0
„ C2 = G1+P1C1
= G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
„ C3 = G2+P2C2
= G2+P2G1+P2P1G0+
P2P1P0C0
 4-bit Carry Lookahead Adder
Less propagation delay
 4-bit Binary Adder/Subtractor
If M=0, D3=B3
If M=1, D3=B3’
A=7, B=3;
A=0111, „ 4-bit adder – a standard component
B=0011
A-B 111
1
0111 D3
1100
10100

v=0

V=0 Î no overflow
A=3, B=7;
A=0011, B=0111
A-B 1 If M=0, calculate A+B (adder)
011
0011
v=0
1000
If M=1, calculate A+(-B)=A+(1’s of B+1)
01100 =A-B (subtractor)
 Signed Binary Numbers
Decimal
Decimal Signed-mag.
Signed-mag. Signed-2’s
Signed-2’s C.
C. Signed-1’s
Signed-1’s C.
C.
+7
+7 0111
0111 0111
0111 0111
0111
+6
+6 0110
0110 0110
0110 0110
0110
+5
+5 0101
0101 0101
0101 0101
0101
+4
+4 0100
0100 0100
0100 0100
0100
+3
+3 0011
0011 0011
0011 0011
0011
+2
+2 0010
0010 0010
0010 0010
0010
+1
+1 0001
0001 0001
0001 0001
0001
+0
+0 0000
0000 0000
0000 0000
0000
-1
-1 1001
1001 1111
1111 1110
1110
-2
-2 1010
1010 1110
1110 1101
1101
-3
-3 1011
1011 1101
1101 1100
1100
-4
-4 1100
1100 1100
1100 1011
1011
-5
-5 1101
1101 1011
1011 1010
1010
-6
-6 1110
1110 1010
1010 1001
1001
-7
-7 1111
1111 1001
1001 1000
1000
(2’s complement)
 Overflow (1/2)
„ The storage space is limited (ex. n-bit register)
„ Add two positive numbers and obtain a
negative number (overflow)
„ Add two negative numbers and obtain a
positive number (overflow)
„ V = 0, no overflow; V = 1, overflow
8-bit register (1-bit for sign and 7-bit for magnitude, +127 ~ -128 )

The answer is – 1101010= -106 overflow error - 0010110=-22

 Overflow (2/2)
„ What is an Overflow
„ Addition/subtraction of two n-digit numbers
Î a sum of (n+1) digits
„ Why detect “overflow”
„ Computers need to detect “overflow” and set a flip-flop
for further use
Insert
a bit „ How to detect “overflow” for signed numbers
+70 0 0 1000110 „ By observing the carry into the sign bit position and out
+80 0 0 1010000
0 1 0010110 of the sign bit position
sign „ How can you avoid the situation of overflow in your circuit?
extra If -128<= a,b <= 127, use a 9-bit register for the sum (a+b).
carry bit (1-bit for sign, 1-bit for extra carry and 7-bit for magnitude)
 Decimal Adder
input carry

9 inputs

output carry 5 outputs

„ 4 bits are required to code a decimal digit

„ There is a wide variety of possible decimal adder circuits,
depending on the code (e.g. BCD, Ex-3).
„ Here we consider a decimal adder for BCD code.
„ max BCD sum = 9 + 9 + 1(input carry) = 19
„ Design approaches for BCD
„ A truth table with 2 entries
9

„ use two binary full adders (binary to BCD)

BCD Adder: The truth table
If the binary sum<=9, BCD sum=binary sum.
If the binary sum > 9, BCD sum= 6+ binary sum.
5-variable K-map
K=0 K=1
Z 8 Z 4 \ Z 2Z 1
Z2

1 1 1 1
x x x x
1 1 1 1 x x x x
Z8
1 1 x x x x

Z1

C = K+Z8Z4+ Z8Z2

S8 S4 S2 S1= Z8 Z4 Z2 Z1+6
 BCD Adder

C = K+Z8Z4+ Z8Z2

If the binary sum<=9,

BCD sum=binary sum.

C
If the binary sum > 9,
BCD sum= 6+ binary sum.

if C = 1, S = Z + 0110
if C = 0, S = Z + 0000

Ignore the output carry

(equal to C -- redundant)
 Binary Multiplier
„ Partial products
– AND operations

Fig. 4.15
Two-bit by two-bit binary multiplier.
 4-bit by 3-bit Binary Multiplier

B3 B2 B1 B0
A2 A1 A0
A0B3 A0B2 A0B1 A0B0
A1B3 A1B2 A1B1 A1B0
A2B3 A2B2 A2B1 A2B0
C6 C5 C4 C3 C2 C1 C0

Four-bit by three-bit
binary multiplier
 Magnitude Comparator
„ The comparison of two n-bit numbers
„ outputs: A>B, A=B, A<B

„ Design Approaches
„ the truth table (2n inputs, 3 outputs)

„ 2n inputs Æ
2n possible combinations in the

truth table (too cumbersome)

„ 3 binary output variables

(A>B), (A=B), (A<B)

„ use inherent regularity of the problem

„ reduce design efforts

„ reduce human errors

 Regularity for Comparison
„ Algorithm -> logic
„ A = A3A2A1A0 ; B = B3B2B1B0
„ A=B if A3=B3, A2=B2, A1=B1and A1=B1
„ equality: xi= AiBi+Ai'Bi' (exclusive-nor)
„ (A=B) = x3x2x1x0 (If xi=1 Î Ai=Bi Î both o or both 1)
„ (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
„ (A>B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
„ Implementation
„ xi = (AiBi'+Ai'Bi)'
Four-Bit Magnitude Comparator
 Decoder
„ A n-to-m decoder
n
„ a binary code of n bits = 2 distinct information
n
„ n input variables; up to 2 output lines (8 K-maps ???)
„ only one output can be active (high) at any time
 Three-to-Eight-Line Decoder
D0
x yz 00 01 11 10

0 1

D1
x yz 00 01 11 10

0 1

… D7 8 K-maps
too cumbersome !!
 Decoder with An Enable
The decoder is
enabled when E is
equal to 0
(active-low enable)
is disabled when E
is 1

Two-to-four-line decoder
0
with enable input
 4x16 Decoder
3X8
w x y z D0 D1 D2 D3
0 0 0 0 1 0 0 0 ……..0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1 Extend to 4 inputs 16 outputs directly
1 1 1 0
1 1 1 1 D0=w’x’y’z’ D1=w’x’y’z …….
 4x16 Decoder: Two 3X8 decoders
w x y z D0 D1 D2 D3
Enable when w=0
0 0 0 0 1 0 0 0 ……..0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1 Enable when w=1
 Combination Logic Implementation
„ each output of a decoder= a minterm
„ use a decoder (“minterm generator”) and an external OR
gate to implement any Boolean function of n input variables
„ A full-adder
S(x,y,x)=Σ(1,2,4,7) 1,2,4,7
001, 010
100, 111, S=1

C(x,y,z)=Σ(3,5,6,7)
011, 101
3,5,6,7
110, 111, C=1
 Encoders
The inverse operation of a decoder
only one input = 1 at any given time

z = D1 + D3 + D5 + D7 The encoder can be implemented

y = D2 + D3 + D6 + D7 with three OR gates.
x = D4 + D5 + D6 + D7 Don’t use K-map directly !!! Why?
Implementation of a 8-to-3 Encoder
x D4+D5+D6+D7

y D2+D3+D6+D7

z D1+D3+D5+D7
 Priority Encoder
„ resolve the ambiguity of illegal inputs (more inputs
are equal to 1)
„ only one of the input is encoded

D3 has the highest priority, D0 has the lowest priority

X: don't-care conditions (0 or 1) , V: valid output indicator
 Simplification of a Priority Encoder
D0D1 D2D3 D0D1 D2D3
Implementation of a Priority Encoder
x = D2 + D3
y = D3 + D1D2′
V = D0 + D1 + D2 + D3
 Multiplexers (Selectors)
„ select binary information from one of many
input lines and direct it to a single output line
2 input lines, n selection lines and one output
n
„

line
2-to-1-line multiplexer

S Y
0 I0
1 I1
(don’t use K-map)
 4-to-1-line multiplexer

Controllability
AND gate
I
Y

S
S=0, Y=0 (block input)
S=1, Y=I (pass input)
OR gate
I Y

S
S=1, Y=1 (block input)
S=0, Y=I (pass input)
Quadruple Two-to-One-Line Multiplexer
E

E S output Y
1 X all 0’s
0 0 select A
0 1 select B

4-bit 2-to-1-line multiplexer

 Three-state gates
„ Output states: 0, 1, and high-impedance
„ High-impedance state behaves like an open
circuit, which means that the output appears
to be disconnected and the circuit has no
logic significance.

A three-state buffer

(Q: what is buffer ?)

 Multiplexer with three-state gates

S Y
0 D0
1 D1
Bus need three-state gates
 IC Industry in Taiwan

邏 粒 切

Circuits are implemented on IC (integrated circuit)

ICÎ CircuitsÎ gatesÎ transistors
 Hierarchical Components in PCB

1. Describe the circuits with

Hardware Description Language
(HDL )

2. Synthesis ( ) the circuits

…. by using EDA tools

application specific integrated circuit

(ASIC )
IC or chip
 Semi Custom IC Design ( IC )
Semi Custom ICDesign
a. Product specification
b. Modeling with HDL
c. Synthesis (by using suitable standard cell) -- implemented with
d. Simulation and verification suitable tools

e. Physical placement and layout

f. Tape-out (real chip) -- implemented by suitable Fab companies
g. Testing -- implemented by suitable tools and mechanisms

more flexible, shorter design cycle, suitable for smaller production

PLD FPGA or CPLD

Xilinx, Altera
Two different solutions :
Real ASIC chip
Fab (TSMC, UMC, ..)
Standard cell
less flexible, long design cycle, larger-scale production to reduce price
 Hardware Description Language (HDL)

• Hardware description language allows you to

describe circuit at different levels of abstractions, and
allows you to mix any level of abstraction in the
design
• Two of the most popular HDLs
-- Verilog -- VHDL
• HDLs can be used for both the cell-based synthesis
and FPGA/CPLD implementation
• Only Verilog is introduced here
 Why Verilog?
Verilog History
1. Verilog was written by gateway design automation in
the early 1980
2. Cadence acquired gateway in 1990
3. Cadence released Verilog to the pubic domain in 1991
4. In 1995, the language was ratified as IEEE standard 1364

Why Verilog ?
1. Choice of many design teams
2. Most of us are familiar with C- like syntax/semantics
 Verilog Features
Features:
„ Procedural constructs for conditional, if-else, case and
looping operations
„ Arithmetic, logical, bit-wise, and reduction operations for
expression
„ Timing control

Basics of Verilog Language:

- Verilog Module - Identifier - Keyword
- Four Value Logic - Data Types - Numbers
- Port Mapping - Operator - Comments
 Verilog Module (1/2)
module module_name (port_name);
(1) port declaration

(2) data type declaration

module functionality or structure
(3)

endmodule module Add_half(sum, c_out, a, b);

input a, b;
(1) output sum, c_out;

(2) wire c_out_bar;

xor (sum, a, b);

(3) nand (c_out_bar, a, b);
c_out_bar c_out not (c_out, c_out_bar);

endmodule
 Verilog Module (2/2)
Verilog Module: basic building block

module DFF module ALU module MUX

-------------------- -------------------- --------------------
-------------------- -------------------- --------------------
------------------- ------------------- -------------------
- - -
- - -
- - -
------------------ ------------------ ------------------
------------------ ------------------ ------------------
endmodule endmodule endmodule
 Structural Description
Verilog allows three kinds of descriptions for circuits:
(1) Structural description (2) Data flow description
(3) Behavioral description

Structural description:
1. module OR_AND_STRUCTURAL(IN,OUT);

2. input [3:0] IN;

output OUT; TEMP[0]
3. u1
4. wire [1:0] TEMP;
u2
5. or u1(TEMP[0], IN[0], IN[1]); TEMP[1]

6. or u2(TEMP[1], IN[2], IN[3]);

7. and (OUT, TEMP[0], TEMP[1]); Synthesized (synthesis) +
8. endmodule optimized by tools
 Data Flow Description
Data flow description
1. module OR_AND_DATA_FLOW(IN, OUT);
2. input [3:0] IN;
3. output OUT;
Synthesized and
optimized by tools 4. assign OUT = (IN[0] | IN[1]) & (IN[2] | IN[3]);

5. endmodule

NOTE:
What is the difference between C and Verilog ?

C : only one iteration (once) is implemented for assignment

Verilog : hard-wired circuit for assignment
 Behavioral (RTL) Description (1/2)
Behavioral description #1

1. module OR_AND_BEHAVIORAL(IN, OUT);

2. input [3:0] IN;

3. output OUT;
4. reg OUT;

5. always @(IN)
6. begin
7. OUT = (IN[0] | IN[1]) & (IN[2] | IN[3]);
8. end
9. endmodule
Activate OUT while any voltage transition
(0 1 or 1 0) happens at signal IN
 Behavioral (RTL) Description (2/2)
Behavioral description #2
module or_and(IN, OUT);
input [3:0] IN; output OUT; reg OUT; (Note)
Truth Table always @(IN)
IN[0] IN[1] IN[2] IN[3] OUT
0 0 0 0 0 begin
0 0 0 1 0 case(IN)
0 0 1 0 0 4'b0000: OUT = 0; 4'b0001: OUT = 0;
0 0 1 1 0
0 1 0 0 0 4'b0010: OUT = 0; 4'b0011: OUT = 0;
0 1 0 1 1 4'b0100: OUT = 0; 4'b0101: OUT = 1;
0 1 1 0 1
4'b0110: OUT = 1; 4'b0111: OUT = 1;
0 1 1 1 1
1 0 0 0 0 4'b1000: OUT = 0; 4'b1001: OUT = 1;
1 0 0 1 1 4'b1010: OUT = 1; 4'b1011: OUT = 1;
1 0 1 0 1
1 0 1 1 1
4'b1100: OUT = 0; 4'b1101: OUT = 1;
1 1 0 0 0 4'b1110: OUT = 1; default: OUT = 1;
1 1 0 1 1 endcase
1 1 1 0 1 Synthesized and
1 1 1 1 1 end
optimized by tools
endmodule
 Half Adder (1/5)

sum= a ⊕ b

c_out = ab
 Half Adder (2/5)

Structural description

module Add_half(sum, c_out, a, b);

input a, b;
output sum, c_out;
wire c_out_bar;
and (e, a, b,c,d);
xor (sum, a, b); a
nand (c_out_bar, a, b); b
e
c
not (c_out, c_out_bar); d
endmodule
 Half Adder (3/5)
Data flow description

module Add_half(sum, c_out, a, b);

input a, b;
output sum, c_out; a sum
half
adder c_out
assign {c_out, sum} = a + b; b
endmodule
Synthesized and
optimized by tools
assign: continuous assignment
 Half Adder (4/5)
Behavioral description #1

module Add_half(sum, c_out, a, b);

input a, b;
output sum, c_out;
reg sum, c_out;

always @ (a or b)
begin
sum = a ^ b;
c_out = a & b;
end
endmodule
 Half Adder (5/5)
Behavioral description #2
module Add_half(sum, c_out, a, b);
input a, b; 2'b10:begin
output sum, c_out; sum = 1; c_out = 0;
reg sum, c_out; end
always @(a or b) default:begin
begin sum = 0; c_out = 1;
case({a,b}) end
2'b00:begin endcase a\b 0 1
sum = 0;c_out = 0; end 0 0 1 sum
end endmodule 1 1 0
2'b01:begin
a\b 0 1
sum = 1; c_out = 0;
end 0 0 0 c_out
1 0 1