PIC24FJ128GA010 FAMILY

Figure 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

AVDD
VR Select
VR+ 16
AVSS

VREF+
VR-
VREF- Comparator
VINH
VR- VR+
S/H DAC
VINL
AN0

AN1 VINH
10-Bit SAR Conversion Logic
AN2
MUX A

AN3
Data Formatting
AN4

AN5
VINL
AN6 ADC1BUF0:
ADC1BUFF
AN7

AN8 AD1CON1
AD1CON2
AN9
AD1CON3
AN10 VINH AD1CHS
MUX B

AD1PCFG
AN11
AD1CSSL
AN12
VINL
AN13

AN14 Sample Control Control Logic

Conversion Control
AN15
Input MUX Control
Pin Config. Control

DS39747F-page 180  2005-2012 Microchip Technology Inc.

 PIC24FJ128GA010 FAMILY
REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON(1) — ADSIDL — — — FORM1 FORM0
bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS
SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE
bit 7 bit 0

Legend: C = Clearable bit HCS = Hardware Clearable/Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: A/D Operating Mode bit(1)

1 = A/D Converter module is operating
0 = A/D Converter is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
10x = Reserved
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
bit 4-3 Unimplemented: Read as ‘0’
bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
bit 1 SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold amplifier is sampling input
0 = A/D Sample-and-Hold amplifier is holding
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is NOT done

Note 1: The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out
the conversion values from the buffer before disabling the module.

 2005-2012 Microchip Technology Inc. DS39747F-page 181

PIC24FJ128GA010 FAMILY
REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
VCFG2 VCFG1 VCFG0 r — CSCNA — —
bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits:

VCFG<2:0> VR+ VR-

000 AVDD AVSS
001 External VREF+ pin AVSS
010 AVDD External VREF- pin
011 External VREF+ pin External VREF- pin
1xx AVDD AVSS

bit 12 Reserved
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexor Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling Buffer 08-0F, user should access data in 00-07
0 = A/D is currently filling Buffer 00-07, user should access data in 08-0F
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (ADC1BUFx<15:8> and ADC1BUFx<7:0>)
0 = Buffer configured as one 16-word buffer (ADC1BUFx<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexor settings for the first sample, then alternates between the MUX B and
MUX A input multiplexor settings for all subsequent samples
0 = Always uses MUX A input multiplexor settings

DS39747F-page 182  2005-2012 Microchip Technology Inc.

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REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: A/D Conversion Clock Source bit

1 = A/D internal RC clock
0 = Clock is derived from the system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0 ADCS<7:0:> A/D Conversion Clock Select bits
11111111
····· = Reserved
01000000
00111111 = 64 * TCY
·····
00000001 = 2 * TCY
00000000 = TCY

 2005-2012 Microchip Technology Inc. DS39747F-page 183

PIC24FJ128GA010 FAMILY
REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8

R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexor Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 14-12 Unimplemented: Read as ‘0’
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexor Setting bits
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
·····
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexor Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 6-4 Unimplemented: Read as ‘0’
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexor Setting bits
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
·····
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0

DS39747F-page 184  2005-2012 Microchip Technology Inc.

 PIC24FJ128GA010 FAMILY
REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PCFG<15:0>: Analog Input Pin Configuration Control bits

1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin configured in Analog mode; I/O port read is disabled, A/D samples pin voltage

REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSSL<15:0>: A/D Input Pin Scan Selection bits

1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan

 2005-2012 Microchip Technology Inc. DS39747F-page 185

PIC24FJ128GA010 FAMILY
EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)

TAD = TCY (ADCS + 1)

TAD
ADCS = –1
TCY

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD RIC  250 Sampling RSS  5 k(Typical)

Switch
VT = 0.6V
Rs ANx RSS

CHOLD
VA CPIN ILEAKAGE = DAC Capacitance
6-11 pF VT = 0.6V 500 nA = 4.4 pF (Typical)
(Typical)
VSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC = Interconnect Resistance
RSS = Sampling Switch Resistance
CHOLD = Sample/Hold Capacitance (from DAC)

Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

DS39747F-page 186  2005-2012 Microchip Technology Inc.

 PIC24FJ128GA010 FAMILY
FIGURE 21-3: A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))

11 1111 1111 (1023)

11 1111 1110 (1022)

10 0000 0011 (515)

10 0000 0010 (514)
10 0000 0001 (513)
10 0000 0000 (512)
01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)

00 0000 0001 (1)

00 0000 0000 (0)

1023*(VR+ – VR-)
512*(VR+ – VR-)

(VINH – VINL)
VR+ – VR-

VR+
VR-
0

1024

1024

1024
Voltage Level
VR- +

VR- +

VR- +

 2005-2012 Microchip Technology Inc. DS39747F-page 187