FPGA PROGRAMMING TECHNOLOGIES

FPGAs consist of a large number of logic blocks interspersed with a programmable

interconnect. The logic block is programmable in the sense that the same building block can be
“programmed” or “configured” to create any desired circuitry. There is also programmability in
the interconnections between the logic blocks. Several techniques have been used to achieve the
programmable interconnections between FPGAs. The term “programming technology” is used
here to denote the technology by which the programmability in an FPGA is achieved. In some
devices, the reconfigurability is achieved by changing the contents of static RAM cells. In some
devices, it is achieved by using flash memory cells. In others, it is achieved by fusing metal
links. In general, FPGAs use one of the following programming methods:

Static RAM programming technology

EPROM/EEPROM/flash programming technology
AntiFuse programming technology

Static RAM programming technology

The SRAM programming technology involves creating reconfigurability by bits stored in static
RAM (SRAM) cells. The logic blocks, I/O blocks, and interconnects can be made
programmable by using configuration bits stored in SRAM. Reconfigurable logic blocks can
easily be implemented as look-up tables (LUTs), which is the same approach as the ROM
method. Sixteen SRAM cells can implement any function of four variables i.e., 2 4. The
programmable interconnect can also be achieved by SRAM. The key idea is to use pass
transistors to create switches and then control them using the SRAM content. Consider the
arrangement in Figure 1(a). The SRAM cell is connected to the gate of the pass transistor.
When the SRAM cell content is 0, the pass transistor is OFF; hence, no connection exists
between points A and B. A closed path can be achieved by turning the pass transistor ON by
making the SRAM cell content 1. SRAM bits can be used to construct routing matrices by using
multiplexers as shown in Figure 1(b). Changing the contents of the SRAM in the arrangement
in Figure 1(b) will allow the designer to change what is connected to point X. The bits that are
stored in the SRAM for deciding the LUT functionality or interconnection are called
configuration bits.
An SRAM cell usually takes six transistors, as illustrated in Figure 2. Four cross-coupled
transistors are required to create a latch, and two additional transistors are used to control
passing data bits into the latch. When the Word Line is set to high, the values on the Bit Line
will be latched into the cell. This is the write operation. The read operation is performed by
precharging the Bit Line and Bit Line' to a logic 1 and then setting Word Line to high. The
contents stored in the cell will then appear on the Bit Line. Some SRAM cell implementations
use only five transistors. One advantage of using static RAM is that it is volatile and you can
write new contents again and again. This provides flexibility during prototyping and
development. Another advantage is that the fabrication steps for making SRAM cells are not
different from the steps for making logic. The major disadvantage of the SRAM programming
technology is that five or six transistors are used for every SRAM cell. This adds a tremendous
cost to the chip. For example, if an FPGA has 1 million programmable points, it means that
approximately 5 or 6 million transistors are employed in achieving this programmability.

Being volatile can become a disadvantage when an FPGA is used in the final product. Hence,
when SRAM FPGAs are used, a nonvolatile device such as an EPROM should be used to
permanently store the configuration bits. Typically, what is done is to use the EPROM as a
“boot ROM,” The EPROM contents are transferred to the SRAM when power comes up.
Xilinx FPGAs were the first FPGAs to use SRAM as the programming technology. In fact, it is
the flexibility and reprogrammability of SRAM FPGAs that caused FPGAs to become widely
popular. Now, many companies use the SRAM programming technology for their FPGAs.
EPROM/EEPROM/flash programming technology

In the EPROM/EEPROM programming technology, EPROM cells are used to control

programmable connections. Assume that EPROM/EEPROM cells are used instead of the
SRAM cells in Figure 1. A transistor with two gates—a floating gate and a control gate—is
used to create an EPROM cell. Figure 3 illustrates an EPROM cell. The pull-up resistor
connects the drain of the transistor to the power supply (labeled VDD in the figure). To turn the
transistor off, charge can be injected on the floating gate using a high voltage between the
control gate and the drain of the transistor. This charge increases the threshold voltage of the
transistor and turns it off. The charge can be removed by exposing the floating gate to
ultraviolet light. This lowers the threshold voltage of the transistor and makes it function
normally.

EPROMs are slower than SRAM; hence, SRAM-based FPGAs can be programmed faster.
EPROMs also require more processing steps than SRAM. EPROM-based switches have high
ON resistance and high static power consumption. The EEPROM is similar to EPROM, but
removal of the gate charge can be done electrically. Flash memory is a form of EEPROM that
allows multiple locations to be erased in one operation. Flash memory stores information in
floating gate transistors as in traditional EPROM. The floating gate is isolated by an insulating
oxide layer; hence, any electrons placed there are trapped. The cell is read by placing a specific
voltage on the control gate. When the voltage to read is placed, electrical current will or will not
flow depending on the threshold voltage of the cell, which is controlled by the number of
electrons trapped in the floating gate. In some devices, the information is stored as absence or
presence of current. In some advanced devices, the amount of current flow is sensed; hence,
multiple bits of information can be stored in a cell. To erase, a large voltage differential is
placed between the control gate and the source, which pulls electrons off. Flash memory is
erased in segments/ sectors; all cells in a block are erased at the same time.
AntiFuse programming technology

In some FPGAs, the programmable connections between different points are achieved by what
is called an “antifuse.” The “antifuse” programming element changes from high resistance
(open) to low resistance (closed) when a high voltage is applied to it. Antifuses are often built
using dielectric layers between N+ diffusion and polysilicon layers or by amorphous silicon
between metal layers. Antifuses are normally OFF; permanently connected links are created
when they are programmed. The process is irreversible; hence, antifuse FPGAs are only one-
time programmable. Programming an antifuse requires applying a high voltage and currents in
excess of normal currents. Special programming transistors larger than normal transistors are
incorporated into the device in order to accomplish the programming. There are various antifuse
technologies; a popular one is the Via antifuse technology.

Antifuse technology has the advantage that the area consumed by the programmable switch is
small. Another advantage is that antifuse-based connections are faster than SRAM- and
EEPROM-based switches. The disadvantage of the antifuse technology is that it is not
reprogrammable (one time programmable). It is a permanent connection; if an error or design
change necessitates reprogramming, a new device is required.
Characteristics of the Major FPGA Programming Technologies