Computer Interfacing(CSE)

Lecture 1
Standard Interfaces

Dr. Adel Agamy

[email protected]
Assistant Professor
Electrical Engineering Department
Faculty of Engineering
Aswan University
 Administration
• Instructor
Dr. Adel Agamy
• Teaching Assistant
Eng. Fatma Gamel
• References
[1] THE INTEL MICROPROCESSORS Architecture,
Programming, and Interfacing, by BARRY B. BREY
[2] Embedded System Interfacing by Marilyn Wolf
[3] Brain-Computer Interface Using Deep Learning Applications
M.G. Sumithra, Rajesh Kumar Dhanaraj, et all
 Grading System

Lecture activities 10

Section activities, performance, etc 10

Project 10

Midterms 20

Final 100

Total 150

Dr. Understanding
Adel Agamy Computers: Today and Tomorrow, 13th Edition
 Course Contents
1. Chapter 2 [2]: Standard Interfaces
2. Chapter 10 [1]: Memory Interface
3. Chapter 11 [1]: Basic I/O Interface
4. Chapter 12 & 13 [1]:Interrupts &DMA
5. Chapter 1 [3] : introduction to BCI
• The goal of this course is to introduce
hardware and software design
techniques and issues for interfacing
computers and peripheral devices
Computer Interface
Computer Interface
 Standard Interfaces

Common standard interfaces:

The RS-232 serial interface commonly used on
personal computers.
• The I2C interface which is used to communicate with
devices along a relatively simple bus; we also discuss
the I2S bus used for digital audio and the CAN bus
used in automotive systems.
• The Universal Serial Bus (USB), which has gone
through several revisions as a common standard for PC
interfacing.
• WiFi, a wireless network widely used for PCs and also
for IoT systems.
 Standard Interfaces

• Zigbee, a wireless network designed for embedded

systems.
• Two wireless interfaces, Bluetooth and Bluetooth Low
Energy (BLE). Despite sharing a common root name,
these two interfaces vary in some interesting and
important ways.
• LoRaWAN, a low power wide area network.
 The RS-232

•Serial data transmission is used for digital

communication between
sensors and computers
computers and computers
Computers and periperal devices (printer, stylus,
mouse, ..)
One of the most widely used communication techniques
to interface external equipment
 RS-232
Serial communication protocol: 1 bit at a time,
sequentially
Parallel transmission: 1 word at a time (i.e. n bits in
parallel)
Advantages of serial transmission: very simple wiring
Transmission Characteristics of RS-232
maximum distance of 20 metres
Maximum bit rate 19 600 bps
Alternative serial communication standards:
RS-422 (up to 10 Mbps over distance of 1.2km)
USB-1 & USB-2
 RS-232

Connectors
‰DB25S is a 25 pin connector with
full RS-232 functionality
‰The computer socket has a
female
outer casing with male connecting
pins
‰The terminating cable connector
has a male outer casing with
female connecting pins
Memory & Memory
Interface

13
 n Data
 k address lines are Input Lines
decoded to address 2k n

words of memory. Memory

k Address Lines
k Unit
 Each word is n bits.
 Read and Write are single 1 2k Words
Read
control lines defining the n Bits per Word
1
Write
simplest of memory
operations. n

n Data
Output Lines
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 Organized as an indexed array of words.
 Value of the index for each word is the memory
address.
 Often organized to fit the needs of a particular
computer architecture.

15
 Example memory contents:
 A memory with4 Memory Address Memory
address bits & 8 data
bits has: Binary Decimal Content
 k = 4 and n = 8 so 00 0 0 0 10001111
24 = 16 addresses labeled 00 0 1 1 11111111
0 to 15. 00 1 0 2 10110001
24 = 16 words of 8-bit 00 1 1 3 00000000
data
Then memory
organization is
2kx n = 24 x 8
= 16 x 8 1 1 11 15 11001100

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 The number of bits that a semiconductor
memory chip can store.
 It can be in units of Kbits (kilobits), Mbits
(megabits)…….
 Capacity = 2k x n
 k address bits = 2k addresses
 n data bits
 n is the “width” of the data path

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Example memory contents:
 A memory with 3 address Memory Address Memory
bits & 8 data bits has: Binary Decimal Content
 k = 3 and n = 8 000 0 10001111
23 addresses of 8-bit 001 1 11111111
data 010 2 10110001
2kx n = 23 x 8 = 64B 011 3 00000000
 Usually memory capacity 100 4 10111001
is presented in bits 101 5 10000110
 However, when 11 0 6 00110011
describing PC memory 111 7 11001100
capacity bytes is used as
unit of memory.
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 Speed of memory is commonly named “Access time “
 Access time : is measured as the time elapsed from the moment the
address is provided to the address pins to the moment that the data is
available at the data pins.

 A few nanoseconds to hundred nanoseconds.

 Depending on the IC technology used

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 A given memory chip has 12 address pins and 8
data pins. Find:
1. The organization
2. The capacity

 A 512K memory chip has 8 pins for data. Find:

1. The organization
2. The number of address pins for this memory chip

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 A given memory chip has 12 address pins and 8
data pins. Find:
1. The organization=> 4096 x8, often
represented as 4Kx8.
2. The capacity = 32K bits

 A 512K memory chip has 8 pins for data. Find:

1. The organization => 64kx8.
2. The number of address pins for this memory
chip = I6 address lines
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 Computer memory includes two major classes.
I. Nonvolatile: computer retains data when the
power is shut off
▪ Read Only Memory (ROM)
▪ Ex: PROM, EPROM, flash ROM, …
II. Volatile: computer loses data when the power is
shut off
▪ Random Access Memory (RAM)
▪ Some times it is referred as RAWM (read and write memory)
▪ SRAM, DRAM

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  Random Access Memory (RAM) is a volatile primary storage
location that the processor uses to store our data during
processing.
 Read Only Memory (ROM) is a non volatile memory and as a
result its content is permanent.
 The main difference between ROM and RAM is that RAM is
written under normal operation, whereas ROM is programmed
outside the computer and normally is only read.

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 Is nonvolatile memory, generally installed during manufacturing

 programmed during fabrication at the factory

 Protects the information required to start and run the computer
 Holds instructions for performing the power-on self test (POST)
and basic input/output system (BIOS) information
 Requires attention only if it needs to be replaced or upgraded

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 PROM memory devices are also available, although they are
not as common today.
 The PROM (programmable read-only memory) is a user
programmable memory.
 Programmed in the field by burning open tiny NI-chrome or
silicon oxide fuses.
 Burning ROM by ROM programmer(burner).
 Once it is programmed, it cannot be erased.

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 The EPROM (erasable programmable read-
only memory) is commonly used when
software must be changed often
 An EPROM is erased by EPROM erasure
 An EPROM is programmed in the field on a
device called an EPROM programmer(burner)
 Also erasable if exposed to high-intensity
ultraviolet light depending on the type of
EPROM(UV-EPROM)
 It disadvantage is it can not be programmed
while being used, therefore, EEPROM was
invented.

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 Electrically erasable in the system for instant.
 Select the byte to be erased
 Program and erase its contents while it is in the system board.
 It is more expensive.

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 Flash has replaced the EPROM in most computer systems for
the BIOS.

 some systems contain a password stored

in the flash memory device
 Flash memory has its biggest impact in memory cards for
digital cameras and memory in MP3 audio players.
 Electrically erasable.

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 It Is a volatile memory
 Used to hold temporary instructions and data for
manipulation while the system is running.
 Term random is applied because the CPU can access or
place data to and from any addressable RAM on the
system.

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 Static RAM memory devices
retain data for as long as DC Select

power is applied.
 called volatile memory B
S Q
C

because they will not retain data

C
R Q
without power B
RAM cell
 Array of storage cells used to
implement static RAM
 Storage Cell

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• The 6116 has an organization of 2Kx8,
•A0 – A11 are for address inputs, where 12 address
lines gives 212 = 2K.
•I/O0 - I/O7 for data I/O, where 8-bit data lines
gives an organization of 2Kx8.
•WE (write enable) is for writing data into SRAM
(active low).
•OE (output enable) is for reading data out of
SRAM (active low)
•CS (chip select) is used to select the memory
chip.
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 Because RAM is often large, it requires many SRAMs at great
cost or a few DRAMs (dynamic RAMs) at much reduced cost.
 IC manufacturers have provided a dynamic RAM controller with
address multiplexers
and timing circuitry necessary for refreshing.
 DRAM is often placed on small boards called SIMMs (Single In-
Line Memory Modules)
 The process of recharging these capacitors is called refreshing
 DRAM is called volatile. without refreshing the data would be
lost.

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▶ Static RAM( SRAM): the high speed memory chip
▶ Internal cache (L1) :
▶ External Cache(L2):
▶ primary use of a cache is to increase the speed of
data From RAM to the CPU.
▶ Write through: CPU send all data directly to RAM.
▶ Write back: send data directly to cache.( some
caches store data for a time and send it to RAM
later.

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 The processor can usually address a memory space that is
much larger than the memory space covered by an individual
memory chip.
 In order to splice a memory device into the address space of
the processor, decoding is necessary.
 For example, the 8088 issues 20-bit addresses for a total of
1MB of memory address space.

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 The processor can usually address a
memory space that is much larger than
the memory space covered by an
individual memory chip. Memory
 In order to splice a memory device into Space
the address space of the processor, 1 MB
decoding is necessary. 20-bit
 For example, the 8088 issues 20-bit
addresses for a total of 1MB of memory
address space.
 The BIOS on a 2716 EPROM has
only 2KB of memory and 11
address pins.
 A decoder can be used to decode
the additional 9 address pins and11-bit
BIOS Memory
2KB
allow the EPROM to be placed in Space
any 2KB section of the 1MB 1 MB
address space. 20-bit
 To determine the address range that a device is
mapped into:
 This 2KB memory segment maps into the
reset location of the 8086/8088 (FFFF0H).

 NAND gate decoders are not often used.

Rather, the 3-to-8 Line Decoder (74LS138) is
more common.
 G2A, G2B, and G1 must be active.
 Each output of the decoder can be attached to an 2764
EPROM ( 8K X 8 ).
 1100 0000 0000 0000 0000
 1100 1111 1111 1111 1111
Find the address ranges for Y4, Y2 and Y7.
 Uses hexadecimal addresses to define
ranges of memory.
 The original processors developed by
Intel were unable to use more than 1 MB
of RAM.
 This 1 MB of memory divided into two
sections: the First 640 KB was reserved
for the O.S and applications ( designated
as conventional memory).
 The remaining 384 KB of RAM
(designated as upper memory) used for
video and ROM.