Computer Interfacing(CSE)

Lecture 2
Basic I/O Interface

Dr. Adel Agamy

[email protected]
Assistant Professor
Electrical Engineering Department
Faculty of Engineering
Aswan University
 Administration
• Instructor
Dr. Adel Agamy
• Teaching Assistant
Eng. Fatma Gamel
• References
[1] THE INTEL MICROPROCESSORS Architecture,
Programming, and Interfacing, by BARRY B. BREY
[2] Embedded System Interfacing by Marilyn Wolf
[3] Brain-Computer Interface Using Deep Learning Applications
M.G. Sumithra, Rajesh Kumar Dhanaraj, et all
 Chapter 11 Outlines
Introduction
• The basic methods of communications, both
serial and parallel, between humans or
machines and the microprocessor.
• The basic I/O interface and discuss decoding
for I/O devices.
• Details of parallel and serial interfacing, both
of which have a variety of applications.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 INTRO TO I/O INTERFACE
• I/O instructions (IN, INS, OUT, and OUTS)
• Isolated (direct or I/O mapped I/O) and
memory-mapped I/O, the basic input and
output interfaces, and handshaking.
• Knowledge of these topics makes it easier to
understand the connection and operation of
the programmable interface components
and I/O techniques.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The I/O Instructions
• One type of instruction transfers information
to an I/O device (OUT). reads from device
(IN).
• Instructions are also provided to transfer
strings of data between memory and I/O.
– INS and OUTS, found except the 8086/8088

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• Instructions that transfer data between an I/O
device and the microprocessor’s accumulator
(AL, AX, or EAX) are called IN and OUT.
• The I/O address is stored in register DX as a
16-bit address or in the byte (p8) immediately
following the opcode as an 8-bit address.
– Intel calls the 8-bit form (p8) a fixed address
because it is stored with the instruction, usually
in a ROM
• The 16-bit address is called a variable
address because it is stored in a DX, and
then used to address the I/O device.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• Other instructions that use DX to address
I/O are the INS and OUTS instructions.
• I/O ports are 8 bits in width.
– a 16-bit port is actually two consecutive 8-bit
ports being addressed
– a 32-bit I/O port is actually four 8-bit ports

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• When data are transferred using IN or OUT,
the I/O address, (port number or simply
port), appears on the address bus.
• External I/O interface decodes the port
number in the same manner as a memory
address.
– the 8-bit fixed port number (p8) appears on
address bus connections A7–A0 with bits
A15–A8 equal to 000000002
– connections above A15 are undefined for
I/O instruction

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• The 16-bit variable port number (DX)
appears on address connections A15–A0.
• The first 256 I/O port addresses (00H–FFH)
are accessed by both fixed and variable I/O
instructions.
– any I/O address from 0100H to FFFFH
is only accessed by the variable I/O address
• In a PC computer, all 16 address bus bits
are decoded with locations 0000H–03FFH.
– used for I/O inside the PC on the ISA
(industry standard architecture) bus

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• INS and OUTS instructions address an I/O
device using the DX register.
– but do not transfer data between accumulator
and I/O device as do the IN/OUT instructions
– Instead, they transfer data between memory
and the I/O device
• Pentium 4 and Core2 operating in the 64-bit
mode have the same I/O instructions.
• There are no 64-bit I/O instructions in the 64-
bit mode.
– most I/O is still 8 bits and likely will remain so
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 Isolated and Memory-Mapped I/O
• methods of interfacing I/O: isolated I/O and
memory-mapped I/O.
• In isolated I/O, the IN, INS, OUT, and OUTS
transfer data between the microprocessor’s
accumulator or memory and the I/O device.
• In memory-mapped I/O, any instruction that
references memory can accomplish the
transfer.
• The PC does not use memory-mapped I/O.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 Isolated I/O
• The most common I/O transfer technique
used in the Intel-based system is isolated I/O.
– isolated describes how I/O locations are isolated
from memory in a separate I/O address space
• Addresses for isolated I/O devices, called
ports, are separate from memory.
• Because the ports are separate, the user can
expand the memory to its full size without
using any of memory space for I/O devices.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• A disadvantage of isolated I/O is that data
transferred between I/O and microprocessor
must be accessed by the IN, INS, OUT, and
OUTS instructions.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 Memory-Mapped I/O
• Memory-mapped I/O does not use the IN, INS,
OUT, or OUTS instructions.
• It uses any instruction that transfers data
between the microprocessor and memory.
– treated as a memory location in memory map
• Advantage is any memory transfer instruction
can access the I/O device.
• Disadvantage is a portion of memory system
is used as the I/O map.
– reduces memory available to applications
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Personal Computer I/O Map
– the PC uses part of I/O map for dedicated
functions, as shown here
– I/O space between ports 0000H and 03FFH
is normally reserved for the system and ISA
bus
– ports at 0400H–FFFFH are generally
available for user applications, main-board
functions, and the PCI bus
– 80287 coprocessor uses 00F8H–00FFH, so
Intel reserves I/O ports 00F0H–00FFH

Figure 11–2 I/O map of a personal computer illustrating many of the fixed I/O areas.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Basic Input and Output Interfaces
• The basic input device is a set of three-state
buffers.
• The basic output device is a set of data
latches.
• The term IN refers to moving data from the
I/O device into the microprocessor and
• The term OUT refers to moving data out of
the microprocessor to the I/O device.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Figure 11–3 The basic input interface illustrating the connection of eight switches.
Note that the 74ALS244 is a three-state buffer that controls the application of the
switch data to the data bus.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Figure 11–4 The basic output interface connected to a set of LED displays.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Handshaking
• Many I/O devices accept or release
information slower than the microprocessor.
• A method of I/O control called handshaking
or polling, synchronizes the I/O device with
the microprocessor.
• An example is a parallel printer that prints a
few hundred characters per second (CPS).
• The processor can send data much faster.
– a way to slow the microprocessor down to match
speeds with the printer must be developed
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Handshaking
• Fig 11–5 illustrates typical input and output
connections found on a printer.
– data transfers via data connections (D7–D0)
• ASCII data are placed on D7–D0, and a pulse is then
applied to the STB connection.
– BUSY indicates the printer is busy
– STB is a clock pulse used to send data to printer
• The strobe signal sends or clocks the data into the
printer so that they can be printed.
– as the printer receives data, it places logic 1 on the
BUSY pin, indicating it is printing data

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Figure 11–5 The DB25 connector found on computers and the Centronics 36-pin
connector found on printers for the Centronics parallel printer interface.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Handshaking

• The software polls or tests the BUSY pin to

decide whether the printer is busy.
– If the printer is busy, the processor waits
– if not, the next ASCII character goes to the printer
• This process of interrogating the printer, or
any asynchronous device like a printer, is
called handshaking or polling.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
I/O PORT ADDRESS DECODING

• Very similar to memory address decoding,

especially for memory-mapped I/O devices.
• The difference between memory decoding
and isolated I/O decoding is the number of
address pins connected to the decoder.
• In the personal computer system, we always
decode all 16 bits of the I/O port address.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Decoding 8-Bit I/O Port Addresses
• Fixed I/O instruction uses an 8-bit I/O port
address that on A15–A0 as 0000H–00FFH.
– the PC never uses or decodes an 8-bit address
Decoding 16-Bit I/O Port Addresses
• PC systems typically use 16-bit I/O
addresses.
– 16-bit addresses rare in embedded systems
The difference between decoding an 8-bit and
a 16-bit I/O address is that eight additional
address lines (A15–A8) must be decoded
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
THE PROGRAMMABLE PERIPHERAL 82C55

• 82C55 programmable peripheral interface

(PPI) is a popular, low-cost interface
component found in many applications.
• The PPI has 24 pins for I/O, programmable in
groups of 12 pins and groups that operate in
three distinct modes of operation.
• 82C55 can interface any TTL-compatible
I/O device to the microprocessor.
• The 82C55 still finds application even in the
latest Core2-based computer system
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
THE PROGRAMMABLE PERIPHERAL 82C55

• 82C55 is used for interface to the keyboard

and parallel printer port in many PCs.
– found as a function within an interfacing chip set
– also controls the timer and reads data from the
keyboard interface
• The 8255 is programmed in either assembly
language or Visual C++ through drivers
available with the board experimentation.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Basic Description of the 82C55
• Fig 11–18 shows pin-outs of the 82C55 in
DIP(dual in-line package) and surface mount (flat pack)
format.
• The three I/O ports (labeled A, B, and C) are
programmed as groups.
– group A connections consist of port A (PA7–PA0)
and the upper half of port C (PC7–PC4)
– group B consists of port B (PB7–PB0) and the lower
half of port C (PC3–PC0)
• 82C55 is selected by its CS pin for programming and
reading/writing to a port.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The pin-out of the 82C55 peripheral interface adapter (PPI).

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• In the PC, a pair of 82C55s, or equivalents,
are decoded at I/O ports 60H–63H and also
at ports 378H–37BH.
• The 82C55 is a fairly simple device to
interface to the microprocessor and program.
• For 82C55 to be read or written, the CS input
must be logic 0 and the correct I/O address
must be applied to the A1 and A0 pins.
• Remaining port address pins are don’t cares.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Programming the 82C55
• 82C55 is programmed through two internal
command registers shown in Figure 11–20.
• Bit position 7 selects either command byte A
or command byte B.
– command byte A programs functions of group
A and B
– byte B sets (1) or resets (0) bits of port C only
if the 82C55 is programmed in mode 1 or 2
• Group B (port B and the lower part of port C)
are programmed as input or output pins.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Programming the 82C55
– group B operates in mode 0 or mode 1
– mode 0 is basic input/output mode that allows the
pins of group B to be programmed as simple input
and latched output connections
– Mode 1 operation is the strobed operation for group
B connections
– data are transferred through port B
– handshaking signals are provided by port C

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 The command byte of the command register in the 82C55

Sets or resets the bit indicated in the select

a bit field

Programs ports A, B and C

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• Group A (port A and the upper part of port C)
are programmed as input or output pins.
• Group A can operate in modes 0, 1, and 2.
– mode 2 operation is a bidirectional mode of
operation for port A
• If a 0 is placed in bit position 7 of the
command byte, command byte B is selected
• This allows any bit of port C to be set (1) or
reset (0), if the 82C55 is operated in either
mode 1 or 2. Otherwise, this byte is not used
for programming
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 0 Operation
• Mode 0 operation causes 82C55 to function:
– as a buffered input device
– as a latched output device
– ports A & B are programmed as (mode 0) simple
latched output ports
– port A provides segment data inputs, port B
provides a means of selecting one display position
at a time for multiplexing the displays
– the 82C55 is interfaced to an 8088 through a PLD
so it functions at I/O port numbers numbers
0700H–0703H.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 LCD Display Interfaced to the 82C55
• LCDs (liquid crystal displays) have replaced
LED displays in many applications.
– DMC-20481 is a 4-line by 20-characters-per-line
display that accepts ASCII code as input data
• It also accepts commands that initialize it and
control its application.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
 The Optrex DMC-20481 LCD display interfaced to the
82C55.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Stepper Motor Interfaced to the 82C55.

• Another device often interfaced to a computer

system is the stepper motor.
– a digital motor because it is moved in discrete
steps as it traverses through 360°
• An inexpensive stepper motor is geared to
move perhaps 15° per step
• A more costly, high-precision stepper motor
can be geared to 1° per step.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• In all cases, these steps are gained through
many magnetic poles and/or gearing.
• Figure shows a four-coil stepper motor that
uses an armature with a single pole.
– two coils are energized
• If less power is required, one coil may be
energized at a time, causing the motor to
step at 45°, 135°, 225°, and 315°.
• The motor is shown with the armature rotated
to four discrete places, called full stepping.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The stepper motor showing full-step operation: (a) 45° (b) 135° (c) 225° (d) 315°.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Key Matrix Interface
• Keyboards come in a variety of sizes, from
standard 101-key QWERTY keyboards to
special keyboards that contain 4 to 16 keys.
• a key matrix with 16 switches interfaced to
ports A and B of an 82C55.
– the switches are formed into a 4  4 matrix,
but any matrix could be used, such as a 2  8
• The keys are organized into four rows and
columns: (ROW0–ROW3) (COL0–COL3)

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 1 Strobed Input
• Causes port A and/or port B to function as
latching input devices.
– allows external data to be stored to the port
until the microprocessor is ready to retrieve it
• Port C is used in mode 1 operation—not for
data, but for control or handshaking signals.
– to help operate either or both port A and B as
strobed input ports

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Signal Definitions for Mode 1 Strobed Input

STB

• The strobe input loads data to the port latch,

which holds the information until it is input to
the microprocessor via the IN instruction.

IBF
• Input buffer full is an output indicating that
the input latch contains information.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
INTR
• Interrupt request is an output that requests
an interrupt. The INTR pin becomes a logic 1
when STB returns to a logic 1. Cleared when
data are input from the port by the processor.

INTE
• Interrupt enable signal is neither input nor
output; it is an internal bit programmed via
port PC4 (port A) or PC2 (port B) bit position.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
PC7, PC6
• The port C pins 7 and 6 are general-purpose
I/O pins that are available for any purpose.

Strobed Input Example

• An example of a strobed input device is a
keyboard.
• The keyboard encoder debounces the key
switches and provides a strobe signal
whenever a key is depressed.
– the data output contains ASCII-coded key code
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 1 Strobed Output
• Strobed output operation is similar to mode 0
output operation.
– except control signals are included to provide
handshaking
• When data are written to a strobed output port,
the output buffer full signal becomes logic 0
to indicate data are present in the port latch.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Signal Definitions for Mode 1 Strobed Output

OBF
• Output buffer full goes low whenever data
are output (OUT) to the port A or B latch. The
signal is set to logic 1 when the ACK pulse
returns from the external device.
ACK
The acknowledge signal causes the OBF
pin to return to logic 1. The ACK signal is a
response from an external device, indicating
that it has received data from the 82C55 port
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
INTR
• Interrupt request often interrupts the
processor when the external device receives
the data via the ACK signal. Qualified by the
internal INTE (interrupt enable) bit.
INTE
• Interrupt enable is neither input nor output;
it is an internal bit programmed to enable or
disable the INTR pin. INTE A is programmed
using PC6 bit. INTE B is programmed using
the PC2 bit.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
PC4, PC5
• Port C pins PC4 and PC5 are general-purpose
I/O pins. The bit set and reset command is
used to set or reset these two pins.
Strobed Output Example
The printer interface demonstrates how to
achieve strobed output synchronization between
the printer and the 82C55

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 2 Bidirectional Operation
• Mode 2 is allowed with group A only.
• Port A becomes bidirectional, allowing data
transmit/receive over the same eight wires.
– useful when interfacing two computers
• Also used for IEEE-488 parallel high-speed
GPIB (general- purpose instrumentation
bus) interface standard.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Signal Definitions for Bidirectional Mode 2

INTR
• Interrupt request is an output used to
interrupt the microprocessor for input
and output conditions.

OBF
• Output buffer full is an output indicating
the output buffer contains data for the
bidirectional bus.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
ACK
• Acknowledge is an input that enables the
three-state buffers so that data can appear
on port A. If ACK is logic 1, the output buffers
of port A are at their high-impedance state.

STB
• The strobe input loads the port A input latch
with external data from the bidirectional
port A bus.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
PC0, PC1, and PC2
• These pins are general-purpose I/O pins in
mode 2 controlled by the bit set and reset
command.
IBF
Input buffer full is an output used to signal that
the input buffer contains data for the external
bidirectional bus.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
INTE
• Interrupt enable are internal bits (INTE1 &
INTE2) that enable the INTR pin. The state
of the INTR pin is controlled through port C
bits PC6 (INTE1) and PC4 (INTE2).

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
82C55 Mode Summary
• Three modes of operation for the 82C55.
• Mode 0 provides simple I/O.
• Mode 1 provides strobed I/O.
• Mode 2 provides bidirectional I/O.
• These modes are selected through the
command register of the 82C55.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
A summary of the port connections for the 82C55 PIA.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey