Department of ECE

Course Code: Digital Circuit Design Credits

3-0-0: 3

2 3 2 - - - - - - - - 1 2 1
2 3 - - - - - - - - - 1 2 1
- 2 - - - - - - - - - 1 2 1
2 2 1 - - - - - 2 - - 1 2 1

Number Systems and Codes: Representation of unsigned and signed integers, Floating Point
representation of real numbers, Laws of Boolean Algebra, Theorems of Boolean Algebra,
Realization of functions using logic gates, Canonical forms of Boolean Functions,
Minimization of Functions using Karnaugh Maps.
Combinational circuit design: Design with basic logic gates, comparators, data selectors,
priority encoders, decoders, full adder, serial binary adder, parallel binary adders-ripple-carry
adder, carry-look ahead adder; Parallel prefix adders- Carry select Adder, Conditional sum
adder, Kogge-stone Adder, Brent-kung adder, Verilog models.
Sequential circuit design: Memory elements and their excitation functions SR, JK, T, and D
latches and flip-flops, master slave JK flip-flop, edge-triggered flip-flop, synchronous and
asynchronous counters, finite-state machine, sequence detector, minimization and
transformation of sequential machines, Registers, Verilog models
Testing of Combinational circuits: Fault models, structural testing: path sensitization Logic
families: TTL and CMOS Logic circuits, Transfer characteristics, fan-in, fan-out, noise margin,
rise time and fall time analysis, realization of Boolean equations using CMOS logic
Memory: Types of memories, MOS SRAM cells, DRAM, SDRAM, ALL DDRx, organization
of a SRAM, Organization of SDRAM, Periphery circuitry of Memory, Flash memory, SD card
Learning Resources:
Text Books:
1. William J. Dally and John W. Poulton, Digital Systems Engineering, Cambridge University
Press, 2008.
2. Schilling, Herbert Taub and Donald, Digital Integrated Electronics, Tata McGraw-Hill, 2008.
3. Jayaram Bhasker, Verilog Primer, 3rd edition, Prentice-Hall India, 1998.
4. Sameer Palnitkar, Verilog HDL: A guide to digital Design and Synthesis, 2nd edition, Pearson,
2003.

Scheme and Syllabi

 Department of ECE

Reference Books:
1. John F Wakerly, Digital Design Principles and Practices, 3rd Edition, Prentice Hall India, 2001.
2. Franklin P. Processor, David E. Winkel, The Art of Digital Design: An Introduction to Top-
Down Design, 2nd Edition, PTR Prentice Hall, 1987.
Other Suggested Readings:
1. NPTEL Courses
2. MIT Open Course Ware, etc.

Scheme and Syllabi

 National Institute of Technology, Warangal
Department of Electronics and Communication
Engineering
Course Handout
Date: 25-07-2024
Course No. : EC201 L T P:Credits::: 3 0 0 : 3 ESC
Course Title : Digital Circuit Design
Instructor : Dr. M. Satish
1. Course description:
The objective of the course is to make the students familiar with the logic gates, combinational
circuits, sequential circuits etc.
2. Course Outcomes:
At the end of the course the student will be able to:
CO-1 Design of combinational and sequential logic circuits and develop Verilog models
CO-2 Understand characteristics of the TTL/CMOS logic families and realize Boolean
equation using CMOS logic
CO-3 Understand fault detection techniques for digital logic circuits
CO-4 Understand SRAM/DRAM organization and periphery circuitry, operation of SRAM
cell, DRAM cell, DDR2/DDR4 and SD card
3. Text Books (TB)
1. William J. Dally and John W. Poulton, Digital Systems Engineering, Cambridge
University Press, 2008.
2. Schilling, Herbert Taub and Donald, Digital Integrated Electronics, Tata McGraw-
Hill, 2008.
3. Jayaram Bhasker, Verilog Primer, 3rd edition, Prentice-Hall India, 1998.
4. Sameer Palnitkar, Verilog HDL: A guide to digital Design and Synthesis, 2nd edition,
Pearson, 2003.
4. Reference Books:
1. John F Wakerly, Digital Design Principles and Practices, 3rd Edition, Prentice Hall
India, 2001.
2. Franklin P. Processor, David E. Winkel, The Art of Digital Design: An Introduction
to Top-Down Design, 2nd Edition, PTR Prentice Hall, 1987.
5. Course Plan
Lect. Ref. to
No. Exercises to be covered Text
Book
1-3 Number Systems and Codes: Representation of unsigned and signed integers, TB 1, 2
Floating Point representation of real numbers
Boolean Algebra: Laws of Boolean Algebra, Theorems of Boolean Algebra,
4-7 Realization of functions using logic gates, Canonical forms of Boolean Functions, TB 1, 2
Minimization of Functions using Karnaugh Maps

8-10 Combinational circuit design: Design with basic logic gates, comparators, data TB 1, 2
selectors, priority encoders, decoders
Adders: Full adder, serial binary adder, parallel binary adders-ripple-carry adder,
11-14 carry-look ahead adder; Parallel prefix adders- Carry select Adder, Conditional TB 1, 2,
sum adder, Kogge-stone Adder, Brent-kung adder, Verilog models. 4

Sequential circuit design: Memory elements and their excitation functions SR,
15-18 JK, T, and D latches and flip-flops, master slave JK flip-flop, edge-triggered flip- TB 1, 2
flop

1
 19-21 Synchronous and asynchronous counters, finite-state machine, sequence detector TB 1, 2

22-24 Minimization and transformation of sequential machines, Registers, Verilog TB 1, 2,

models 4
Testing of Combinational circuits: Fault models, structural testing: path
25-29 TB 1, 2
sensitization

30 Logic families: TTL and CMOS Logic circuits TB 1, 2

Transfer characteristics, fan-in, fan-out, noise margin, rise time and fall time
31-34 TB 1, 2
analysis

35-36 Realization of Boolean equations using CMOS logic TB 1, 2

37 Memory: Types of memories, MOS SRAM cells, DRAM, SDRAM, ALL DDRx TB 1, 2

38-39 Organization of a SRAM, Organization of SDRAM TB 1, 2

40-42 Periphery circuitry of Memory, Flash memory, SD card TB 1, 2

6. Contact Hours:
Day of Week Class Time
Tuesday 13:00 to 13:55
Thursday 10:00 to 10:55
Friday 8:00 to 8:55

7. Evaluation Scheme
Component Duration Weightage
Minor Test I 20 mins 10-15
Minor Test II 20 mins 10-15
Assignment - 10-15
Mid Sem Exam 2:00 hrs 20-30
End Sem Exam 2:30 hrs 40

8. Chamber consultation hours:

Monday to Wednesday 04:00 PM to 05:00 PM.
Thursday and Friday 02:00PM to 5:00PM.
Any other time with prior appointment.

9. Special Instructions:
1. Do not try to copy the sentences from the PPT and write in exam.
2. Do not copy/share the assignments given to you.