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Omar Khaled

سيفي

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18 views2 pages

Omar Khaled

سيفي

Uploaded by

aar79441
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Omar Khaled Elsaid Education

Undergraduate Ain Shams university, undergraduate "senior 1"


2020 – 2025 | Cairo, Egypt
[email protected] Electronics and Communication Engineering major
01096455679
Profile
Elshorouk city - Cairo - Egypt
Undergraduate senior 1, 2018 by law, uG2018, credit hours,
www.linkedin.com/in/omar-khaled-
specialized programs
90b01b219
Electronics & Communications engineering
Ain shams university Faculty of engineering
Cumulative GPA : 3.01
Courses
Digital IC Design Diploma, Certificates
Under supervision of Eng. Ali El-Temsah
07/2024 – 09/2024 Digital Design
using Verilog HDL and FPGA flow using Vivado.
Digital IC Verification,
Kareem Waseem diploma Digital Verification
using SystemVerilog and UVM

Skills
Programming Languages "HDL" : ASIC Flow
Verilog: Solid knowledge in Digital/RTL design
• including (Floorplanning, Pin Placement, Clock
•

basics. Tree Synthesis,Placement, Routing, Timing


SystemVerilog: Proficient in basic simulation
• Closure, Chip Finishing, Sign Off)
usage, code coverage, functional coverage, and Post-Layout Verification (Gate Level Simulation)
•

SystemVerilog assertions.
Design and Architecture:
Tools: Hardware Description Languages: Solid
•

Siemens EDA Simulation Tool : QuestaSim - Solid


• knowledge of both Verilog and SystemVerilog.
knowledge in using QuestaSim for simulation, FPGA Design Flow: Proficient in FPGA design flow
•

code coverage, functional coverage, and and architecture.


SystemVerilog assertions. Vivado Design Flow: Knowledgeable in Vivado
•

Knowledge of FPGA design flow and architecture


• design flow for FPGA development.
Knowledge of Vivado design flow ( Simulation,
•

Synthesis ) Verification Techniques:


Knowledge in clock domain crossing techniques.
•

Communication Protocols: Basic understanding formal Verification , FPGA-


•

Acquired knowledge in one of the most widely


• based prototyping, and emulators.
used communication protocols Experienced in the generation of Constrained
•

“SPI-Slave connected to dual-port RAM” Random Stimulus.


Acquired knowledge in one of the most widely
•

used communication protocols "UART" Verification Methodologies:


UVM: Demonstrated solid knowledge and
•

Object-Oriented Programming (OOP): experience in UVM-based verification


Basic understanding of Object-Oriented
• methodologies.
Programming principles. Assertion-Based Verification: Proficient in
•

assertion-based verification and functional


TCL Scripting Language coverage.
Testing Strategies: Solid understanding of testing
•

strategies, test planning, and testing automation.


Projects
“RTL to GDS Implementation of Low Power Configurable Multi Clock Digital 09/2024
System”, (on going)
RTL Design from Scratch of system blocks (ALU, Register File, Synchronous FIFO,
•

Integer Clock Divider, Clock Gating, Synchronizers, Main Controller, UART TX,
UART RX).
Integrate and verify functionality through self-checking testbench.
•

Constraining the system using synthesis TCL scripts.


•

Synthesize and optimize the design using design compiler tool.


•

Analyze Timing paths and fix setup and hold violations.


•

Verify Functionality equivalence using Formality tool


•

Physical implementation of the system passing through ASIC flow phases and
•

generate the GDS File.


Verify functionality post-layout considering the actual delays.
•

Communication Protocol Implementation :,


“SPI-Slave connected to dual-port RAM”
Successfully implemented and demonstrated expertise in one of the most utilized
communication protocols.

Class-Based SystemVerilog Testbench Development:


Engineered a robust SystemVerilog testbench for a FIFO and SPI-Slave connected
•

to Dual-port RAM.
Demonstrated proficiency in leveraging SystemVerilog features for effective
•

verification

FPGA Design :
Applied knowledge of FPGA design flow and architecture in real-world projects,
showcasing practical skills

UVM Environment for SPI-Slave and Dual-port RAM:


Spearheaded the development of a comprehensive top-level UVM environment.
•

Successfully integrated and verified the SPI-Slave connected to Dual-port RAM


•

using UVM methodologies.


Showcased adeptness in handling complex verification scenarios within a UVM
•

framework.

Worked on design by verilog :


Spartan6 - DSP48A1

Languages Military Status


Arabic Delayed
Native Speaker

English
Good working knowledge

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