Analog Integrated Circuits & Simulation

Laboratory
List of Experiments
Cycle - 1
1. Familiarization of Operational Amplier
2. Measurement of OP-AMP parameters
3. Wien Bridge Oscillator
4. Schmitt Trigger Circuit
5. Astable Multivibrator using OP-AMP
6. Waveform Generators using OP-AMP
7. Precision Rectiers
8. Active Second Order Filters
9. Active Notch Filter

Cycle - 2
1. Astable Multivibrator using Timer IC 555
2. Monostable Multivibrator using Timer IC 555
3. Series Voltage Regulator using LM723 IC
4. D/A Converter using R-2R Ladder network
5. SPICE Simulation of RC Phase shift Oscillator
6. SPICE Simulation of Waveform Generators using OP-AMP
7. SPICE Simulation of Active second order lters using Op-Amp (LPF,
HPF, BPF)
8. SPICE Simulation of D/A Converter using R-2R Ladder network
9. SPICE Simulation of Series Voltage Regulator using LM723 IC

1
Expt No. 1 Familiarization of Operational Ampliers

2
 Expt No. 2 Measurement of OP-AMP parameters
Aim:- To measure the following parameters of the OP-AMP 741C:

1. Input Oset Voltage (Vio )

2. Input Bias Current (IB )

3. Input Oset Current (Iio )

4. Slew Rate

5. CMRR

Circuit Diagrams:
Input Oset Voltage Measurement:

Rf

R1
− Vo

Figure 1: To measure input oset voltage

Procedure: To nd input oset voltage, setup the circuit as shown in gure 1 and
measure the output voltage (Vo ). The input oset voltage is given as

Vo R1
Vio = (1)
Rf + R1

where Rf = 100kΩ & R1 = 1kΩ. Typical value of the Vio =6 mV.

Input Bias Current & Oset Current Measurement:

0.01uF

− 1M
Vo
IB1
+ − Vo
0.01uF IB2
1M
+

Figure 2 (a). To measure current IB1 Figure 2 (b). To measure current IB2

3
 Procedure: To nd input oset current & input bias current, setup the circuit as shown
in gure 2 (a) 2 (b) and measure the output voltage (Vo ). Using the expression the following
expression IB1 & IB2 can be found.

Vo = IB1 R (2)

Vo = IB2 R (3)

From equation (2) & (3) IB1 & IB2 can be computed. The input bias current and input oset
current can be expressed as

IB1 + IB2
IB = (4)
2
Iio = |IB1 − IB2 (5)

The typical value of IB =500 nA and Iio = 200 nA for the OP-AMP µA 741C.

Slew Rate Measurement:

− Vo

Vin

Figure 2: To measure Slew Rate

Procedure: To nd slew rate, setup the circuit as shown in gure 3. Apply square wave
of 5Vpp, 1 KHz frequency. Vary the input frequency and observe the output. Increase the
input signal frequency until the output square wave changed to a triangular wave. Calculate
the slew rate by measuring the slope of the output waveforms.

dVo
Slew rate = |
dt max
=0.5V/µs typically.

CMRR Measurement:

Rf Rf

V2 R1 R1
− − Vco
Vo
R2 R2
+ +
V1
Rc Vci Rc

Figure 4 (b). To measure common mode

Figure 4 (a). To measure dierential mode
gain Ad gain Ac

4
 Procedure: To nd Common Mode Rejection Ratio (CMRR), setup the circuit as shown
in gure 4. Apply a dierence voltage (Vid ) of 100 mV at the input of circuit shown in gure 4
(a). Measure the output voltage (Vo d). The dierential mode voltage gain can be computed
from
Vod
Ad = (6)
Vid
To measure the common mode voltage gain Ac , apply a common mode voltage of 5Vpp , 1KHz
sine wave at the input of the circuit 4 (b). Measure the common mode output voltage (Voc ).
The common mode voltage gain Ac is given by

Voc
Ac = (7)
Vic
The CMRR is computed from the equation given below

 
Ad
CMRR = 20 log (8)
Ac

Typical value of the CMRR is 90 dB

5
 Expt No. 3 Wien Bridge Oscillator
Aim:- Design and setup a wien bridge oscillator of frequency 1 KHz using OP-AMP 741C:
Circuit Diagram:

Rf

R1
− Vo

R1 C1
C2 R2

Figure 3: 1. Wien bridge oscillator

Design:
Given f = 1 KHz, The frequency of oscillation is given by the equation,

1
f= √ Hz (9)
2π R1 R2 C1 C2
Let C1 = C2 =C & R1 = R2 =R; then the frequency of oscillation is given by,

1
f= Hz (10)
2πRC
Let C =0.1µF, R = 1.5 KΩ

The gain of the amplier is given by

Rf
A=1+ (11)
Ri
For Wien bridge oscillator, the gain of the amplier should be atleat 3;

Ri = 10KΩ, & Rf = 20KΩ ≈ 22KΩ (standard value)

6
 Expt No. 4 Schmitt Trigger Circuit
Aim:- Design and setup inverting, non-inverting & biased schmitt trigger circuits using
OP-AMP 741C for dierent values of LTP & UTP.

Circuit Diagram:

− Vo
R2
Vin
+ R1
+
Vo
Vin
R2 −
R1

Figure 4 (b). Non-Inverting schmitt

Figure 4 (a). Inverting schmitt trigger
trigger circuit
circuit

− Vo
Vin
+

R2
R1
VRef

Figure 4 (c). Biased schmitt trigger circuit

Design:

Inverting Schmitt trigger: Non-Inverting Schmitt trigger:

Let Vsat = 14V, VU T P = 3V & VLT P = -3V Let Vsat = 14V, VU T P = 3V & VLT P = -3V

R1 R1
VU T P = Vsat = 3V (12) VU T P = Vsat = 3V (13)
R1 + R2 R2

Let R1 = 10KΩ, then R2 = KΩ Let R1 = 10KΩ, then R2 = KΩ

Biased Schmitt trigger:

Let Vsat = 14V, VU T P = 4V & VLT P = 2V

R1 R2
VU T P = Vsat + VRef = 4V (14)
R1 + R2 R1 + R2
R1 R2
VLT P = − Vsat + VRef = 2V (15)
R1 + R2 R1 + R2

7
 Let VRef = 3V, solve the above two equations to nd R1 & R2 .
Procedure:
Setup the circuit as shown in gure shown above. Apply 1 KHz sinewave having ampli-
tude greater than the UTP from a function generator. Observe the output waveform in the
CRO. The transfer curve can be viewed on the CRO or DSO by setting the CRO in the XY
mode. Apply the input signal in the Channel 1 and observe the output using Channel 2.

Inverting Schmitt trigger: Non-Inverting Schmitt trigger:

Vin Vin

VUTP VUTP

t t
VLTP VLTP

Vo Vo
Vsat Vsat

t t
-Vsat -Vsat

Figure 4 (d). Output waveform Figure 4 (e). Output waveform

Vo Vo
Vsat Vsat

VLTP VUTP
Vin Vin

-Vsat -Vsat

Figure 4 (f ). Transfer curve Figure 4 (g). Transfer curve

8
Biased Schmitt trigger: Vo
Vsat

Vin
VUTP
VLTP

t
VLTP VUTP Vin

Vo
Vsat

t
-Vsat
-Vsat

Figure 4 (h). Output waveform Figure 4 (i). Transfer curve

9
 Expt No. 5 Astable Multivibrator using OP-AMP
Aim:- Design and setup an astable multivibrator of frequency 1 KHz using OP-AMP
µA741C with the following spaecications:

1. Duty ratio = 50%

2. Duty ratio = 10%

Circuit diagram:

R +VCC

4 8
RA
− 7 Reset Vcc
Vo Dis
RB 6 Threshold Out 3
C
+ NE555 Vo
2 Trigger
Gnd Ctrl
R1 C 1 5
R2 0.01uF

Figure 5 (b). Astable Multivibrator circuit

Figure 5 (a). Astable Multivibrator circuit
with duty ratio = 10%
with duty ratio = 50%

Design:

50% Duty ratio: 10% Duty ratio:

R2 R2
β= = 0.5 β= = 0.5
R1 + R2 R1 + R2
R1 = 10KΩ; & R2 = 10KΩ R1 = 10KΩ; & R2 = 10KΩ
1+β 1+β
T = T1 + T2 = 2RC ln T1 = R3 C ln = 0.1ms
1−β 1−β
Let C = 0.1µF ; R = KΩ; 1+β
T2 = R4 C ln = 0.9ms
1−β
Let C = 0.1µF ; R3 = KΩ; R4 = KΩ;

10
 Typical output waveforms:

50% Duty ratio: 10% Duty ratio:

Vo Vo
+Vsat +Vsat
+βVsat +βVsat
VC VC
t t
-βVsat -βVsat
-Vsat -Vsat

Figure 5 (c). output waveform with duty Figure 5 (d). output waveform with duty
ratio = 50% ratio = 10%

11
 Expt No. 6 Waveform Generators using OP-AMP
Aim 1:- Design and setup an triangular waveform generator of frequency 1 KHz using
OP-AMP µA741C.

Aim 2:- Design and setup a saw-tooth waveform generator of frequency 1 KHz using
OP-AMP µA741C.

Circuit diagram:

R2 R2
C C
R1 R1
+ +
R3 R3
− Vo − Vo
− −
+ +
+V -V
R4
Figure 6 (a). Triangular waveform
generator Figure 6 (b). Saw-tooth waveform
generator

Design:

Trianglular waveform generator:

The peak to peak output of triangular wave is given by the equation,

R1
VTP P = 2 Vsat
R2
The frequency of oscillation f is given by the equation,

R2
f=
4R1 R3 C
Given, VTP P = 5V; f = 1 KHz;

Let C = 0.1µF, Vsat = 13 V, R2 = 1 KΩ, Then R1 = ; R3 = ;

Saw-tooth waveform generator:

The Trianglular waveform generator circuit design is modied to get the saw-tooth wave-
form. The potentiometer R4 = 10K is used additionally for the saw-tooth waveform generator
circuit.

12
 Typical output waveforms:

Triangular waveform: Saw-tooth Waveform::

Comparator output
Vsat Comparator output
Vsat

0
t
0
t

-Vsat
-Vsat
Vo
Integrator output Vo
Integrator output

0
t
0
t

Figure 6 (c). output waveform of the

comparator Figure 6 (d). Output waveform

13
 Expt No. 7 Precision Rectiers
Aim 1:- Design and setup a precision halfwave rectier using OP-AMP µA741C. Also
plot its output waveform & transfer curve.

Aim 2:- Design and setup a precision fullwave rectier using OP-AMP µA741C. Also
plot its output waveform & transfer curve.

Circuit diagram:

+
Vin −
− Vin A2
D + D2
R1 R2
Vo
RL
Vo
−
A1
Figure 7 (a). Precision halfwave rectier
+ D1
RL

Figure 7 (b). Precision fullwave rectier

Procedure:

Precision Halfwave Rectier:

Assemble the circuit as shown in Figure 7(a). Apply a 500mV, 1 KHz sine waveform
from a signal source. Observe the output waveform across the load the resistor RL (10KΩ).

To plot the transfer curve, set the DSO in the X-Y mode. Apply the input signal to the
channel-1 (X-input) and apply the output to the channel-2 (Y-input). Observe the transfer
curve on DSO.

Precision Fullwave Rectier:

Assemble the circuit as shown in Figure 7(b). Apply a 500mV, 1 KHz sine waveform from
a signal source. Observe the output waveform across the load the resistor RL (10KΩ).Assume
the Resistors R1 = R2 = 10KΩ and use the diodes D1 & D2 as 1N4001.

To plot the transfer curve, set the DSO in the X-Y mode. Apply the input signal to the
channel-1 (X-input) and apply the output to the channel-2 (Y-input). Observe the transfer
curve on DSO.

14
 Typical Waveforms:

Output waveforms:
Vin Vin

0 0
t t

Vo Vo

0 0
t t

Figure 7 (c). Precision halfwave rectier Figure 7 (d). Precision fullwave rectier
output output

Transfer Curves:

Vo Vo

0 0
Vin Vin

Figure 7 (e). Precision halfwave rectier Figure 7 (f ). Precision fullwave rectier

transfer curve transfer curve

15
 Expt No. 8 Active Second order Filters
Aim 1:- Design and setup a second order butterworth low-pass lter for an upper cut-o
frequency of 1 KHz. Plot the frequency response and nd the upper cut-o frequency.

Aim 2:- Design and setup a second order butterworth high-pass lter for a lower cut-o
frequency of 1 KHz. Plot the frequency response and nd the lower cut-o frequency.

Aim 3:- Design and setup a second order narrow band-pass lter for a center frequency
of 1KHz, Quality factor of 3 and gain AF = 10. Plot the frequency response and nd the
lower cut-o frequency, upper cut-o frequency, bandwidth and Q-factor.

Circuit diagram:

RF RF

Ri Ri
− Vo − Vo
R2 R1 741C C2 C1 741C
+ +

Vs C2 C1 Vs R2 R1

Figure 8 (a). Butterworth second order Figure 8 (b). Butterworth second order
LPF HPF

C2

R3

R1 C1
− Vo
741C
+
Vin R2
RL

Figure 8 (c). Narrow Band-pass Filter

Design of active Low-Pass Filter:

The upper cut-o frequency of the low pass lter is given by

1
fH = √ Hz
2π R1 R2 C1 C2
Let R1 = R2 = R & C1 = C2 = C;

16
 The above equation for upper cut-o frequency is simplied to

1
fH = Hz
2πRC
Let C = 0.1 µF, nd the R value for a fH = 1 KHz. For second order butterworth lter,
the voltage gain must be 1.586. The voltage gain AF is given by

RF
AF = 1 + = 1.586
Ri
∴ RF /Ri = 0.586

Let Ri = 10KΩ, ∴ RF = 5.86 KΩ ≈ 6.2 KΩ (standard value).

Design of active High-Pass Filter:

The lower cut-o frequency of the high-pass lter is given by

1
fL = √ Hz
2π R1 R2 C1 C2
Let R1 = R2 = R & C1 = C2 = C;

The above equation for lower cut-o frequency is simplied to

1
fL = Hz
2πRC
Let C = 0.1 µF, nd the R value for a fL = 1 KHz. For second order butterworth lter,
the voltage gain must be 1.586. The voltage gain AF is given by

RF
AF = 1 + = 1.586
Ri
∴ RF /Ri = 0.586

Let Ri = 10KΩ, ∴ RF = 5.86 KΩ ≈ 6.2 KΩ (standard value).

Design of Narrow Band-Pass Filter:

The center frequency frequency of the band-pass lter is given as fc = 1KHz, Q = 3,

AF =10. To simplify the calculations, assume C1 = C2 = C = 0.01µF (Refer Figure 8 (c)).
The value of R1 , R2 , & R3 is calculated as per the following equations:

Q 3
R1 = = = 4.77KΩ ≈ 4.7KΩ
2πfc CAF 2π(1000)(0.01 × 10−6 )(10)
Q 3
R2 = = = 5.97KΩ ≈ 6.2KΩ
2
2πfc C(2Q − AF ) 2π(1000)(0.01 × 10−6 )(2 × 32 − 10)
Q 3
R3 = = = 95.5KΩ ≈ 100KΩ
πfc C π(1000)(0.01 × 10−6 )
∴ R1 = 4.7 KΩ, R2 = 6.2 KΩ, R3 = 100 KΩ & C = 0.01µF

Result: The second order active low-paas lter, high-pass lter and band-pass lter are
designed and plotted their frequency responses.

17
1. Low-Pass Filter:
The upper cut-o frequency fH =
Pass band gain AF =

2. High-Pass Filter:
The lower cut-o frequency fL =
Pass band gain AF =

3. Band-Pass Filter:
The lower cut-o frequency fL =
The upper cut-o frequency fH =
The bandwidth BW =fH − fL =
Q factor =
The gain at the center frequency AF =

18
 Expt No. 9 Notch Filter
Aim:- Design and setup a second order Notch lter for a notch frequency of 1.6 KHz.
Plot the frequency response and nd the notch frequency.

Circuit diagram:

R R − Vo
741C
+

C C
Vin RL 10K
2C R/2

Figure 9. Twin-T Notch Filter

Design of Notch Filter:

The notch-out frequency is given by

1
fN = Hz (16)
2πRC
Given fN = 1.6 KHz, let C = 0.01µF, compute the R ?

R = 995 Ω≈ 1kΩ

Result: Plotted the frequency response of the notch lter.

The measured notch frequency fN = Hz

The attenuation at the notch-out frequency = dB

19
Experiment Cycle - II

20
 Expt No. 10 Astable Multivibrator using Timer IC 555
Aim:- Design and setup an astable multivibrator using timer IC 555 of frequency 1 KHz
and (i) duty ratio 80% & (ii) duty ratio 50%.

Circuit diagram:

Figure 10.1 Internal diagram of 555 in Astable mode.

+VCC +VCC

4 8 4 8
RA RA
7 Reset Vcc 7 Reset Vcc
Dis Dis
RB 6 Threshold Out 3 RB 6 Threshold Out 3
Vo D Vo
NE555 NE555
2 Trigger 2 Trigger
Gnd Ctrl Gnd Ctrl
C 1 5 C 1 5
0.01uF 0.01uF

Figure 10.2 Astable multivibrator duty Figure 10.3 Astable multivibrator duty
ratio >50% ratio = 50%

Design:

The output frequency is f = 1KHz. Assume Vcc = 10V.

1
Total time period T = = 1ms
f

21
 Duty ratio 80% Duty ratio 50%
The equation to ON time period T1 is given For 50% duty ratio, ON time period (T1 ) =
by OFF time period (T2 ) and is given by the
equation (Ref. Figure 10.3)
T1 = 0.693 (RA + RB ) C = 0.8×T = 0.8ms
The equation to OFF time period T2 is
given by T1 = T2 = 0.693 RA C = 0.5 × T = 0.5 ms
T2 = 0.693 RB C = 0.2 × T = 0.2 ms
Let C = 0.1µ F; ∴ RB = Let C = 0.1µ F; ∴ RA = RB =
Sub. in equation for T1 and nd RA .

Waveforms:

Vo Vo
T T

0 0
t T1 T2 t
T1 T2
VC VC
2/3VCC 2/3VCC

1/3VCC 1/3VCC

0 0
t t
Figure 10.4 Astable multivibrator duty Figure 10.5 Astable multivibrator duty
ratio = 80% ratio = 50%

Result: Astable multivibrator using timer IC 555 is designed and plotted the output
and capacitor waveforms.

At 80% duty ratio:

Observed output Frequency f = ...Hz

duty ratio = ...

At 50% duty ratio:

Observed output Frequency f = ...Hz

duty ratio = ...

22
 Expt No. 11 Monostable Multivibrator using Timer IC
555
Aim:- Design and setup an Monostable multivibrator using timer IC 555 for a pulsewidth
of 1 ms.

Circuit diagram:

+VCC Vtrigger

4 8
VCC
R
7 Reset Vcc
R1 D Dis
6 Threshold Out 3
0
Vo Vo t
NE555
2 Trigger T T
VCC
Vi C1 Gnd Ctrl
C 1 5
0.01uF 0
t
VC
Figure 11.1 Monostable multivibrator 2/3VCC

0
t

Figure 11.2 Monostable multivibrator

waveforms

Design:

The ON time period (T) of the pulse in a monostable multivibrator is given by the
equation;

T = 1.1 R × C

Given T =1 ms; let C = 0.1 µF; R = 9.09 KΩ ≈ 10KΩ.

For preventing false triggering at the positive edge, a dierentiator circuit is connected
at the trigger input of the timer IC. A diode D (1N4001) is connected as shown in gure to
remove the positive spikes from the dierentiator output (R1 C1 ).

The pulse width for the monostable output is designed for 1 ms.
The trigger pulse can
1
be applied at the trigger input of the timer IC for a frequency of 100 Hz (Tp = ).
100Hz

For better dierentiation,

Tp 10ms
R1 C1 < = = 1ms
10 10
Let C1 = 0.1 µF; ∴ R1 = 10 kΩ

23
 Result: Monostable multivibrator circuit using timer IC 555 has been de-
signed and output waveforms plotted.

The observed pulsewidth of the output waveform =... ms

24
 Expt No. 12 Series Voltage Regulator using LM 723 IC
Aim 1:- Design a series voltage regulator of 5V/1A using LM723 IC. Plot the load and
line regulation characteristics. Also nd the percentage of load regulation & percentage line
regulation.

Aim 2:- Implement a simple current limit protection to the above design and plot the
load and line regulation characteristics.

Aim 3:- Implement a foldback limiting protection to the 5V/1A series voltage regulator
and plot the load and line regulation characteristics.

Aim 4:- Design a series voltage regulator of 12V/1A using LM723 IC. Plot the load and
line regulation characteristics. Also nd the percentage of load regulation & percentage line
regulation.

Circuit diagram:

Figure 12.1 Internal diagram of the regulator IC LM 723

T1 VO
A
+ 12 11
− Vdc
V +
VC VO 10
6 C 2
Vref L
R3 RL
3
R1 LM723 CS
5
NI 4
0.1uF INV
R2 V- Comp
7 13 100 pF
Figure 12.2 LM723 Pin Diagram

Figure 12.3 Low Voltage Regulator using

25
 LM723

T1 Rsc VO T1 Rsc VO
A A
+ 12 11 + 12 11
− Vdc − Vdc
V+ VC VO 10 V+ VC VO 10 R3
6 C 2 6 C 2
Vref L RL Vref L RL
3 3 R4
R1 LM723 CS R1 LM723
5 R3 5 CS
NI 4 NI 4
0.1uF INV 0.1uF INV
R2 V- Comp R2 V- Comp
7 13 100 pF 7 13 100 pF

Figure 12.4 Low Voltage Regulator with Figure 12.5 Low Voltage Regulator with
simple current limit protection foldback current limit protection

VO T1 Rsc VO
T1
A A
+ 12 11 + 12 11
− Vdc − Vdc
V +
VC VO 10 V+ VC VO 10
6 6 C 2
Vref CL 2 Vref L
RL
R2 RL CS 3 R2
C 3
S R3 LM723
R3 LM723 4
4 5 INV
5 INV NI
NI R1
R1 V- Comp
V- Comp 7 13 100 pF
7 13 100 pF

Figure 12.7 High Voltage Regulator with

Figure 12.6 High Voltage Regulator using simple current limit protection
LM723 IC

Design:

Low Voltage Regulator:

Given that Vo = 5V, ILmax =1 A, An external series pass transistor T1 is used for
boosting the load current to above 150 mA. An unregulated voltage of 12V is applied at the
input (VC ).

A positive low-voltage regulator (2 V to 7 V) using LM723 IC is as shown in Figure 12.3.

The voltage at the non-inverting terminal of the error amplier is obtained using a voltage
divider circuit (R1 &R2 ). The voltage at the non-inverting terminal VN I is given by,

R2
VN I = Vref
R1 + R2
The error amplier is congured as a voltage follower circuit with an internal series pass
transitor and an external series pass transistor (T1 ).

26
 ∴ The output voltage of the regulator (Vo ) is approximately same as (VN I ).

R2
VN I = Vo =
Vref
R1 + R2
The 723 IC provides a constant reference voltage of Vref =7.15V. Let R1 = 10KΩ, R2
can be estimated using the above equation for Vo .

Simple current protection:

A simple current limit protection can be implemented using the internal protection tran-
sistor. An external protection resistor Rsc is connected between the base and emitter of the
internal protection transistor (between CL & CS ) to implement the simple current limit pro-
tection. When a short circuit occurs at the regulator output, the voltage accros the Rsc will
be greater than 0.6V. This turns on the internal protection transistor and there by divierting
the base current of the series pass transistor through the internal protection transistor. This
prevents further increase of load current through the series pass transistor and protects the
regulator.
Let Isc be the maximum safe load current through the regulator, then Rsc can be esti-
mated as per the following equation.

0.6V 0.6V
Rsc = = = 0.5Ω
Isc 1.2A
The power ratings of the resistor Rsc is calculated as shown below:

2
PRsc = Isc × Rsc = 1.22 × 0.5Ω = 0.72W ≈ 1W (standard)

∴ Rsc = 0.5Ω/1W.

Foldback limiting protection:

Foldback limiting is another form of overcurrent protection where both the output cur-
rent and the output voltage reduces with short-circuit at the load. The load regulation
characteristics with foldback limiting is shown in gure 12.8. The resistances Rsc , R3 , R4 &
the internal current limit transistor Q2 is used for the foldback limit protection. The gure
12.5 describe the foldback limit in a low-voltage regulator using 723 IC. The VBE2 of the
internal current limit transistor Q2 can be expressed as per the following equation.

VBE2 = VRsc − VR3

The voltage VR3 across R3 will increase or decrese if the load voltage increases or de-
creases. When the load current increases to its maximum permissible value, VRsc becomes
large enough to make VBE2 approximately 0.7V. i.e., VBE2 ≈ 0.7 V = VRsc − VR3 . At this
point current limiting occurs similar to simple current limit protection. If the load resistor
is made smaller, the load voltage will drop and VR3 will also drops. Since VBE2 remains
essentially a constant at 0.7 V, a smaller load current must ow to produce the smaller drop
across VRsc . Further decreases in load resistance produce further drops in load voltage and
a further reduction in load current, as foldback limiting occurs.

27
 Let R3 = 1kΩ; R4 = 9kΩ, and output voltage Vo = 5V. For a maximum load current
of ILmax = 1 A, the short-circuit protection resistor Rsc can be obtained as follows:

The voltage across the R3 is given by

   
R3 1kΩ
VR3 = Vo = × 5V = 0.5V
R3 + R4 10kΩ

From the equation to VBE2 = 0.7V = VRsc - VR3

VRsc = 0.7 V + 0.5V = 1.2 V

VRsc
∴ Rsc =
ILmax
= 1.2 Ω

The power ratings of the resistor Rsc is calculated as shown below:

PRsc = IL2 max × Rsc = 1.02 × 1.2Ω = 1.2W ≈ 2W (standard)

∴ Rsc = 1.2Ω/2W.

High Voltage Regulator:

Given Vo = 12V; ILmax = 1 A; Let the unregulated input voltage to the regulator is
Vdc =20V;

The basic high voltage regulator with output voltage greater than 7 V is shown in Figure
12.6. In the high voltage mode, the error amplier inside the 723 regulator is congured as
non-inverting amplier with a voltage gain given by,

 
R2
Vo = Vref 1 +
R1

Let R1 = 10kΩ; R2 can be computed from the above equation.

Short-circuit protection:
The high voltage regulator with simple short circuit protection is shown in Figure 12.7.

Let Isc be the maximum safe load current through the regulator, then Rsc can be esti-
mated as per the following equation.

0.6V 0.6V
Rsc = = = 0.5Ω
Isc 1.2A
The power ratings of the resistor Rsc is calculated as shown below:

2
PRsc = Isc × Rsc = 1.22 × 0.5Ω = 0.72W ≈ 1W (standard)

∴ Rsc = 0.5Ω/1W.

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 Waveforms:

Vo Vo
VNL
VFL

0 IFL IL mA 0 Vin
Figure 12.8 Load regulation Figure 12.9 Line regulation
characteristics characteristics

Vo Vo Normal regulator operation

VNL VNL

foldback-limiting region
0 ILmax IL mA 0 ILmax IL mA
Figure 12.10 Load regulation Figure 12.11 Load regulation
characteristics with simple current characteristics with foldback current
limiting limiting
Result: Designed a low voltage and high voltage regulator using LM723 IC.
Plotted the load and line regulation characteristics.

Observed output voltage of the low-voltage regulator = ...

% of load regulation for the low-voltage regulator =...

% of line regulation for the low-voltage regulator =...

Observed output voltage of the high-voltage regulator = ...

% of load regulation for the high-voltage regulator =...

% of line regulation for the high-voltage regulator =...

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 Expt No. 13 Digital to Analog Converter using
OP-AMP 741C
Aim :-Design a R-2R ladder type 4-bit Digital to Analog Converter using
OP-AMP 741C IC.

Circuit diagram:

2R R R R RF

+15V
2R 2R 2R 2R
− Vo
1 B0 1 B1 1 B2 1 B3 741C
+
5V 0 0 0 0
RL
-15V

Figure 13.1 R-2R Ladder type DAC circuit

Design:

The output voltage equation to a 4-bit R-2R ladder type DAC is given by,

 
B3 B2 B1 B0
Vo = −RF + + +
2R 4R 8R 16R
where each of the binary inputs B3 , B2 , B1 , B0 may be either high (+5V) or low (0V).

Let R=10kΩ and RF = 2R = 20kΩ and RL = 10kΩ.

Observation:

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 Decimal Eqvt. of Input (V) Output Voltage (V)
binary inputs B3 B2 B1 B0 Calculated Measured
0 0 0 0 0 0
1 0 0 0 5 -0.625
2 0 0 5 0 -1.25
3 0 0 5 5 -1.875
4 0 5 0 0 -2.50
5 0 5 0 5 -3.125
6 0 5 5 0 -3.750
7 0 5 5 5 -4.375
8 5 0 0 0 -5
- - - - - -
14 5 5 5 0 -8.875
15 5 5 5 5 -9.375

Results:
Designed an R-2R ladder type DAC using OP-AMP 741C and veried the
results.

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