ECE 5234 EMI Noise Reduction and Filter Design

Project 1

Due date: Oct 20th, 2024 (Sunday)

A Boost dc/dc converter and the parameters are shown in Fig. 1. MOSFET BSC060N10NS3 is used for T1 and T2.
The gate of T2 is short-circuited to make T2 always turned off and work as a diode. A continuous PWM signal with
25% duty cycle and frequency of 100 kHz is used to drive T1.

Fig. 1 DC-DC boost converter

Q1(20points): Please use the LTSPICE to set up a boost converter shown above. Please use the model to simulate the
ideal boost converter and show the following waveforms in one figure. From top to bottom: PWM signal voltage, Vds
of T1, inductor current iL , and output voltage Vout. (switch on /off voltage Vg could be set as 5V/0V, a gate resistor of
(e.g. 5Ω in this case) is needed for Spice model, simulation time step of 5ns or smaller is required).

Note: please use the waveforms in the steady state and show the waveforms in about 5 switching cycles.

Please show PWM signal Vg and Vds of T1 in the turn-off transient of T1. Note: please include the waveforms within
0.5 us after the falling edge of PWM signal Vg.

Q2(30 points): A dc busbar is designed for the boost converter, as shown in Fig. 2(a). There are 6 terminals on the
busbar. There are three layers in the busbar: DC-, AC and DC+ & Vgate & Vsource (Vgate & Vsource are connected to switch
T1’s gate resistor and source). Each net of DC-, AC takes up one layer, and nets DC+ & Vgate & Vsource (shown in red
with copper materials) together take the same one layer as show in Fig. 2(b). The three copper layers are assembled
with the FR4 material (green material). The gate signal current flowing direction is shown with black arrow.

The parasitic parameters of the busbar include parasitic inductance, parasitic capacitance, and parasitic resistance. Fig.
3(a) shows the parasitic resistances and inductances of the busbar. R dc+, Rdc-, and Rac are the parasitic resistances of
copper layers (from one terminal to the other terminal). L dc+, Ldc-, and Lac are the parasitic self-inductances of copper
layers (from one terminal to the other terminal). Mdc+_ac, Mdc-_ac, and Mdc+_dc- are the three mutual inductances between
the three copper layers. Fig. (b) shows the parasitic capacitance between the three copper layers.

The parasitic parameters of gate signal traces (for switch T1) include parasitic inductance, parasitic capacitance, and
parasitic resistance. Fig. 4(a) shows the parasitic resistances and inductances of the gate signal traces. Rgate and Rsource
are the parasitic resistances of copper layers (from one terminal to the other terminal). L gate and Lsource are the parasitic
self-inductances of copper layers (from one terminal to the other terminal). M gate-ac and Msource-ac are the mutual
inductances between gate signal traces layers and AC layer (mutual inductances between gate signal traces layers and
DC layers could be neglected for simplification). Fig. 4(b) shows the parasitic capacitance between the gate signal
traces and AC layer. The current flow direction (black arrows) for the gate signal is provided for Q3D simulation.

The Q3D model of the dc busbar + gate signal traces is attached. Please use Q3D to simulate the parasitic resistance,
inductance, parasitic capacitance of the busbar mentioned above.

Note1: All the parasitics are extracted at the frequency of 100 MHz.

Note2: Please show the screenshot of the Tables of parasitic resistance, inductance, parasitic capacitance, e.g. Fig. 4.

Fig. 2 DC Bus with gate signal traces for T1 (a) 3D view (b)cross section view

Fig. 3 Parasitics of the busbar (a) Parasitic resistance and inductances (b) Parasitic capacitance.

Fig. 4 Fig. 2 Parasitics of the gate signal traces and busbar (a) Parasitic resistance and inductances (b) Parasitic
capacitance.
Q3(40 points): A LTSPICE component model of the busbar can be generated with the parasitic parameters obtained
in Q2. Please export the parasitic resistance, inductance, parasitic capacitance (100 MHz) of the busbar + gate signal
traces into a LTSPICE model (see the instructions and use the parasitic parameters @ 100 MHz) and use it for the
simulation of boost converter in LTSPICE. Please show the following waveforms in one figure. From top to bottom:
PWM signal voltage (measured at left side of Rg in Fig. 5), Vds of T1, inductor current iL , and output voltage Vout.

The connections between the busbar and the boost converter are shown in Fig. 5.

Fig. 5 Boost converter with dc busbar + gate signal traces.

Note1: The instructions of Q3D and LTSPICE are attached.

Note2: please use the waveforms in the steady state and show the waveforms in about 5 switching cycles.

Please show PWM signal Vg and Vds of T1 in the turn-on/off transient of T1. Note: please include the waveforms
within 0.5 us after the rising/falling edge of PWM signal Vg. Compare the waveforms with designed busbar & gate
signals traces and the waveforms in the ideal boost converter. Measure the peak voltage of Vg and Vds and the
oscillation frequency.

Q4(10 points): Please discuss why the oscillation happens in the turn-off transient if the busbar is used and the possible
factors influencing the frequency and amplitude of the oscillation. And discuss what is causing the gate drive signal
oscillations & impacts.

Hint: Pay attention to the parasitic capacitance and inductance obtained in the Q3D simulation.

Pay attention to gate drive signals difference between the source PWM signal (from gate driver), PWM signals
measured at gate resistor Rg’s terminals .

Based on the simulations, do you have any suggestion for the dc busbar/gate signal traces design for boost
converter?
Note:

Please put your name and your PID (also student ID number)

All homework is due at 11:00pm on their due dates. Later ones will not be accepted unless

prior arrangements have been made with the instructor. Homework can be submitted in class or

uploaded into scholar.

Homework may be handwritten. However, it should be neat and legible. Be sure to staple

your pages together in the order of the problems as they appear. Work that cannot be

easily read (in the opinion of the instructor or the GTA) will receive no credit.

Students may discuss general approaches to solving homework problems. The actual solutions

to be turned in for grading should be the original work of the individuals.