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06 - Branch Prediction Logic Notes Upload

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sujeet.p
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- Branch Hazards

- Delayed Branch
- Branch Prediction
Pipelining
Data Dependency
• Flow dependency
• Anti-dependency
• Output dependency
• I/O dependency
Control Hazards(Branch Hazards)
• All the instructions who change the program
counter leads to the control hazard
• Branch Condition
• Interrupt
Control hazards:

The instruction fetch unit of the CPU is responsible for


providing a stream of instructions to the execution unit.

The instructions fetched by the fetch unit are in consecutive


memory locations and they are executed.
Control hazards:

However the problem arises when one of the instructions is


a branching instruction to some other memory location.

Thus all the instruction fetched in the pipeline from


consecutive memory locations are invalid now and need to
removed(also called flushing of the pipeline).

This induces a stall till new instructions are again fetched


from the memory address specified in the branch instruction.
Control hazards:

Thus the time lost as a result of this is called a branch


penalty.

Often dedicated hardware is incorporated in the fetch unit to


identify branch instructions and compute branch addresses
as soon as possible and reducing the resulting delay as a
result.
Branch Hazards
in the Pipelined Processor
Branch Hazards
• Branch dependences can result in branch hazards
(aka control hazards) when they are too close to
be handled correctly in the pipeline.

CSE 1419 - Topic


Conditional Branch Instructions
Delayed Branch and Branch Prediction

Delayed branch and branch prediction are two


different ways of mitigating the effects of a long
execution pipeline.

Without them, the pipeline needs to stall whenever a


conditional branch is taken, because the instruction
fetch mechanism can't know which instruction should
be executed next after the branch instruction until the
computations on which it depends are completed.
Dependences
• Data dependence: one instruction is dependent on
another instruction to provide its operands.
• Control dependence (Branch dependences): One
instructions determines whether another gets executed
or not.
• Control dependences are particularly critical with
conditional branches.
add $5, $3, $2

data dependences sub $6, $5, $2

beq $6, $7, somewhere


control dependence
and $9, $3, $1
CSE 141
13- Topic
What is delayed branching?
• When branches are processed by a pipeline
simply, after each taken branch, at least one cycle
remains unutilized.

• Instruction slots following branches are known as


branch delay slots.
Delayed Branch
What is delayed branching?
• Delayed branch A conditional branch instruction
found in some RISC architectures that
include pipelining.

• The effect is to execute one or more instructions


following the conditional branch before the
branch is taken.

• Throughput might Decreases.


Delayed Branch
Delayed Branch
• Delayed branch simply means that some
number of instructions that appear after the
branch in the instruction stream will be
executed regardless of which way the branch
ultimately goes.
Delayed Branch
• In many cases, a compiler can put
instructions in those slots that don't actually
depend on the branch itself, but if it can't, it
must fill them with NOPs, which kills the
performance anyway.

• This approach keeps the hardware simple,


but puts a burden on the compiler technology.
Branch Prediction
What Does Branch Prediction
Mean?
• Branch predication speeds up the processing
of branch instructions with CPUs using
pipelining.

• The technique involves only executing certain


instructions if certain predicates are true.

• Branch prediction is typically implemented in


hardware using a branch predictor.
Branch Prediction
Branch prediction is a more hardware-oriented
approach, in which the instruction fetcher simply
"guesses" which way the branch will go.

CPUs initially executed instructions one by one


as they came in, but the introduction of
pipelining meant that branching instructions
could slow the processor down significantly as
the processor has to wait for the conditional
jump to be executed.
Branch Prediction
• Branch prediction breaks instructions down
into predicates, similar to predicate logic.

• A CPU using branch prediction only executes


statements if a predicate is true. One
example is using conditional logic.

• Since unnecessary code is not executed, the


processor can work much more efficiently.
Branch prediction is implemented in CPU
logic with a branch predictor.
Branch Prediction
Various systems have different ways of
improving the accuracy of the guess.

Sometimes the compiler puts a clue into the


instruction stream, and sometimes the hardware
keeps track of which way each branch has gone
in the past.
Branch Prediction
Branch Prediction
Branch Prediction
Branch Prediction
Techniques to handle Control
Hazards
• Branch Predictions
• Predicts whether there is any branching
• Static Branch Predictor(Either yes or no)
• Dynamic Branch Predictor
• Delayed Predictions
Dynamic Branch Predictor

• Dynamic Branch Predictor


• Change the predictions based on previous instructions
• 1 bit dynamic branch predictor(Taken/Not Taken)
• 2 bit dynamic predictor
1 bit dynamic branch predictor
Delayed Prediction
• Delay slot
• I1,I2,I3,(I4->I1),I5,I6…
• Here I4 is branched instruction and I1 need to be
executed next.
• But I5 and I6 are already fetched. I5 and I6 are Delay
slot instructions.
• So wait for time to execute I5 and I6 ,this time is called
delay time.

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