Model Question Bank

VLSI Design
EC-3011

Note: This question bank is under development and frequently updated. So, you are advised to
check it periodically.

Module-1: VLSI Design Methodology and design style

Short Answer Type Question:

1. When an IC designer chooses to go for a full custom IC design methodology for his
design, mention two reasons.
2. Mention Importance of Behavioral simulation and synthesis in VLSI design
3. When a functionally equivalent off the shelf component is not available in the market
which design methodology a IC designer can choose when time to market is a concern,
mention the reason for choosing it.
4. When a functionally equivalent off the shelf component is not available in the market as
well as there are no existing cell libraries available. which design methodology a IC
designer can choose when time to market is not a concern, mention the reason for
choosing it.

Descriptive type:
1. Draw a neat labeled diagram of Gajski’s Y-chart and explain how the VLSI chip design is
perceived.
2. It is desired to design a Video Processing IC with enhanced features and the constraints
for this design are: low power, High Performance, small area. State and explain the VLSI
Design style that to be used keeping in mind the above constraints.
3. A large-scale fast prototyping system has been produced by using FPGA.
(a) Discuss the pros and cons of such prototyping systems for proof of design
concepts and verification in view of effort and speed performance of the design.
(b) How would you compare the hardware prototyping method with the computer
simulation model?

Module-2: VLSI Fabrication

Short Answer type Question:

1. Highlight differences between dry and wet oxidation techniques.

2. Difference between positive and negative photoresist
3. Why is Silicon preferred over Germanium?
Descriptive type:

1. Discuss the process of Lithography, emphasizing the importance of Mask and photoresist.
2. With the help of neat diagrams explain the steps followed to fabricate a PMOS device on
a N-type substrate.
3. Write a brief note on ion implantation technique. What are the advantages of ion
implantation over diffusion technique?

Module-3: Two terminal MOS structure and its analysis

Short Answer type questions:

1. Define flat band condition and flat band voltage of MOSFET.
2. Why is negative body bias (VSB) not applied for NMOS transistors?
3. Mention the approximation made in Gradual channel approximation technique.
4. Draw a graph indicating variation in threshold voltage with body bias for n-channel MOS
transistors.
5. Why is channel length modulation effect prominent in short channel MOSFETs?
6. How the output resistance of a MOS transistor is affected by channel length modulation?
7. Describe the relationship between mask channel length LM, and electrical channel length
L. Are they identical? If not, express the relation between L and LM.

Descriptive type:

1. An enhancement-type nMOS transistor has the following parameters:

Vt0=0.8V
Ƴ=0.2 V1/2
λ=0.05 V-1
|2φF |= 0.58 V
μn.Cox= 30 μA/V2
(a) When the transistor is biased with VG= 2.8 V, VD= 5 V, Vs =1 V,
and VB =1 V, the drain current is ID = 0.24 mA. Determine W/L.
(b) Calculate ID for VG= 4 V, VD= 4 V, Vs= 2 V, and VB= 1V

2. The following parameters are used for a NMOS transistor. Substrate doping ND = 1015
cm-3, polysilicon gate doping density ND = 1020 cm-3, gate
oxide thickness tox = 650 A0, and oxide-interface charge density NOX=2 x 1010 cm-2. Use
 εsi = 11.7ε0 and εox = 3.97ε0 for the dielectric coefficients of silicon and silicon-dioxide,
respectively.
Calculate the threshold voltage when (a) Body is 0.2 V positive compared to Source (b)
Body is 0.2 V negative compared to Source.

3. The reported experimental data of one n- MOSFET is listed in the table below. Determine
the device parameter VTO, γ, κ=µ.Cox.(W/L) and λ. Assume |2Φf|=0.7 Volt. [6]

VDS(V) VGS(V) VBS(V) ID

(µA)
5 2 0 10
5 5 0 400
5 5 -3 280
8 5 0 480

4. With the help of Gradual channel approximation derive the expression of drain current of
an NMOS transistor in saturation region considering the effect of channel length
modulation.

5. Discuss the components of threshold voltage. and derive the expression of Threshold
voltage of a MOSFET for non-zero substrate bias.

6. Consider the following p-channel MOSFET process: Substrate doping ND = 1016 cm-3,
polysilicon gate doping density ND = 1020 cm-3, gate oxide thickness tox = 650 A0, and
oxide-interface charge density Nox = 2 x 1010 cm-2. Use εsi = 11.7ε0 and εox = 397ε0 for the
dielectric coefficients of silicon and silicon-dioxide, respectively. Calculate the threshold
voltage VTH, (a) for VSB = 0V and (b)for VSB = 0.2V.

7. Compare full scaling and voltage scaling in terms of drive current, power dissipation,
power density and gate capacitance. Which type of scaling is preferred for low power and
which one is preferred for high speed applications? Justify your answers.
8. The following parameters are given for an nMOS process.
● tox=500Å
● Substrate doping NA=1016 cm-3
● Polysilicon gate doping ND=1020cm-3
● Oxide interface charge density Nox=2x1010cm-2
(a) Calculate VT for unimplanted transistors.
(b) What type and what doping concentration of impurities must be implanted to achieve a
threshold voltage VT=+2V and VT=-2V?
 9. An enhancement nMOS has the following parameters.
µn=340cm2/Vs, tox=210Å, |2Φf|=0.74V, polysilicon gate doping =ND=1020cm-3,
Neglect the effect of bulk charge and oxide interface charge densities. Calculate VGS if
VD=3.3V, VS=0.4V, VB=0V, 𝞬=0.1V-1/2, (W/L)=2 and ID=2mA. Assuming the transistor operates
in a linear region.

Module-4: MOS Inverter

Short Answer Type Question:

1. Define noise margin of inverter.
2. What are the drawbacks of resistive load inverters?
3. Plot VTC curve of resistive load inverter for different values of KnRL
4. What are the advantages of active MOS load inverters over resistive load inverters?
5. Compare CMOS inverter and NMOS inverter in terms of power and speed.
6. Identify the operating region of NMOS and PMOS in a CMOS inverter if Vin=Vdd/2 is
applied. Assume Vdd=5V.
7. State the condition required for one CMOS inverter to be symmetrical.
8. At which condition, one NMOS and PMOS will conduct the same amount of current for
the same magnitude of terminal voltages?

Descriptive type:
1. Compare resistive load , saturated enhancement load, linear enhancement load and
depletion MOSFET load inverter in terms of area requirement, power consumption and
noise margin.
2. Discuss the operation of resistive load inverters and plot the VTC curve and highlight
different critical voltages (VOH, VOL, VIL, VIH). How can the sharpness of the VTC curve
be increased?
3. With a suitable sketch, describe the operation of the CMOS inverter. Also highlight
different operating regions in the voltage transfer characteristics curve.
4. What do you mean by symmetrical CMOS inverter? Establish the necessary conditions
required for symmetry.
5. Design one CMOS inverter by determining the ratio of width of the NMOS and PMOS
transistor (Wn/Wp) to achieve a switching threshold voltage of 1.9V. The power supply
of the inverter is 3.3V and other parameters related to NMOS and PMOS are:
μnCox=30μA/V2, VT0,n=0.7V and μpCox=10μA/V2, VT0,p=-0.6V. Assume channel
length L=500 nm for both transistors.
Hint: Expression for switching threshold voltage of inverter is given by
 From the above expression, find KR=Kn/Kp= μnCox(W/L)n / μpCox (W/L)p. Since
channel length (L), μnCox and μpCox value is given, (Wn/Wp) can be derived.

6. Discuss CMOS inverter by drawing its VTC and derive the expression for its switching
power dissipation and switching threshold voltage for a symmetric inverter for . If
VT0n=|VT0p|=1.0V, VDD=5V, find the switching threshold voltage. Given μnCox=30μA/V2,
and μpCox=10μA/V2.

7. If for a CMOS inverter, μnCox=30μA/V2, and μpCox=10μA/V2, VT0n=|VT0p| =0.6 V,

VDD=3.3V, evaluate the VIL and VIH

Module-5: Transient operation of CMOS Inverter and Delay, Power estimation

Short Answer type questions

1. Define rise and fall time in CMOS inverter

2. What is the purpose of using a super buffer?
3. What do you mean by short circuit power dissipation in CMOS circuits?
4.

Descriptive /Numerical type:

1. One CMOS inverter having following parameters: μnCox=10μA/V2, (W/L)n=10,

VT0,n=0.6V and μpCox=10μA/V2, (W/L)p=4, VT0,p=-0.7V. The inverter has a supply
voltage (VDD) of 5V and drives a load capacitor of 1pF. Estimate the high-to-low(tPHL)
and low-to-high(tPLH) propagation delay (50% delay time) using the current averaging
method. As a designer, if you want to reduce the low-to-high(tPLH) delay of the same
inverter then what will be your design strategy?
Hint:
2. Design one CMOS inverter by determining the size of the NMOS transistor (W/L) so that
high to low propagation delay (50% delay)should be limited to 2ns. The inverter drives
one load capacitor of value 2pF with a supply voltage of 3.3 Volt. Other design
parameters are: μnCox=20μA/V2, VT0,n=0.6V and μpCox=10μA/V2, VT0,p=-0.5V. Use
the average current method.

3. Why is the low power feature of CMOS logic circuits less prominent in high speed
operation?
4. What is a super buffer and why is it used? Derive the optimum scaling factor in the super
buffer to drive a large capacitive load with minimum delay.

5. Discuss different types of power dissipation that occur in CMOS circuits. Which
component is prominent during switching operation?
Hint: Power dissipation components in CMOS circuits: (1) Dynamic or switching power
dissipation, (2) short circuit power dissipation (3) Leakage power dissipation.
Dynamic power dissipation dominates during switching. It originates from the periodic
charging and discharging of parasitic load capacitors.

6. One CMOS inverter driving equivalent load capacitance of 1pF at supply voltage of 3.3V.
If the average value of current flowing through NMOS and PMOS transistors are 1.5mA
and 0.8mA respectively then find the 50% delay tPHL and tPLH of the inverter. Symbols
have their usual meaning.

Hint: tPHL=Cload.ΔVout/Iavg(H-L). During High-to low transition NMOS is ON, So,

Iavg(H-L)=1.5mA. And ΔVout=VOH-V50%=3.3-1.65=1.65V, Cload=1pF. Using these data, tPHL
can be derived.

Similar calculation for tPLH, PMOS is responsible for LOW to HIGH transition.

tPLH=Cload.(V50%-VOL)/Iavg(L-H), where VOL=0 for CMOS inverter and V50%=Vdd/2.

7. For CMOS inverters with following data evaluate tPLH and tPHL using average current
method.

Kn=60uA/V2, kp=20uA/V2, Vdd=5V, (W/L)n=(W/L)p.VT0n=0.7V, VT0p=-0.65V.

Cloud=1pF.

Hint: Same as above (see Q1)

8. One CMOS inverter has the following parameters. Find the VIL and VIH and noise margin
of the inverter if the value of Vout is 3.1V and 0.21V respectively at these unit slope
points. Parameters: VDD=3.3V, VT0n=0.55V, VT0p=-0.65V, kn=170uA/V2, kp=70uA/V2.

Hint:
 When Vin=VIL, dVout/dVin=-1 (unit slope point), at this point Vout=3.1V, KR=Kn/Kp,
all other parameters given. So VIL can be derived from the above equation.

Similarly,

At Vin=VIH, Vout=0.21V (given), find out VIH. After getting VIL and VIH find noise
margin using:

NMH=VOH-VIH=VDD-VIH

NML=VIL-VOL=VIL-0

10. Consider a CMOS inverter with following parameters. The output load capacitance is
2pF. Calculate the propagation delay tpLH using the average current method.

NMOS: VT0n=0.7V, kn=50uA/V2, PMOS: VT0p=-0.9V, kp=20uA/V2, VDD=5V.

11. Consider switching delays for 1pF in a 10KΩ resistive load inverter circuit where,
μnCox=60uA/V2 , W/L=10, VT0=1V.

Find tPHL (50% high to low delay) by using the average current method. Assume the input
signal is an ideal rectangular pulse switching between 0V and 5V. Supply voltage (VDD) of
the inverter is 5V.

Hint:

The VOL value of resistive load inverter is given by

Putting all values, the calculated VOL value is 0.48V.

𝑉𝑂𝐻+𝑉𝑂𝐿 5+0.48
𝑉50% = 2
= 2
=2.74V
Note that, the relation between MOSFET current ID, resistor current IR and discharging
current of capacitor ic is related as (IR+ic=ID) (Applying KCL at output node this equation can
be obtained).

Case-1: When Vin=5V, Vout=VOH=5V, NMOS is in saturation,

⎡ 2⎤
𝐼𝐷𝑛 = µ𝐶𝑜𝑥 (𝑊/𝐿)⎢(𝑉𝑖𝑛 − 𝑉𝑡, 𝑛) ⎥=2mA
⎣ ⎦

Since VDD=5V, Vout=5V, current flowing through the resistor is 0. So, current flowing
through a capacitor is the same as current flowing through MOSFET.

Case-2:

When Vin=5V and Vout=V50%=2.74V,

⎡ 2
𝑉𝑜𝑢𝑡 ⎤
𝐼𝐷𝑛 = µ𝐶𝑜𝑥 (𝑊/𝐿)⎢(𝑉𝑖𝑛 − 𝑉𝑡, 𝑛)𝑉𝑜𝑢𝑡 − ⎥=1.8mA
⎢ 2 ⎥
⎣ ⎦

Current flowing through resistor IR=(5-2.74)/10K=0.226mA

So, current flowing through capacitor (discharging current) = 1.8-0.226=1.57mA

Average value of capacitor current flowing during high to low transition is (2+1.57)/2
=1.78mA

High to low delay

𝐶𝑙𝑜𝑎𝑑(𝑉𝑂𝐻−𝑉50%) −12
10 (5−2.74)
τ𝑃𝐻𝐿 = 𝐼𝑎𝑣𝑔,𝐻𝐿
= −3 = 1. 27𝑛𝑠𝑒𝑐
1.78𝑥10
 Module-6: CMOS Logic design

Short answer type questions

1. Why is nmos a suitable choice for pull down network in CMOS logic?
Ans: NMOS can easily pass logic-0 and can't pass logic-1 correctly. Purpose of the pull
down network is to discharge the load capacitor to GND i.e. to pass logic-0. Hence
NMOS is a suitable choice.
2. Why is pmos a suitable choice for a pull up network in CMOS logic?
Ans:PMOS can easily pass logic-1 and can't pass logic-0 correctly. Purpose of the pull up
network is to charge the load capacitor to VDD i.e. to pass logic-1. Hence PMOS is a
suitable choice.

3. Implement the boolean function F=(AB+CDE)’ using CMOS logic

4. State difference between Lambda and micron rule related to layout design.
5. Draw a stick diagram of two input CMOS NOR gates.
6.

Descriptive type
1. Implement the Boolean function f=(AB.(CD+E))’ using CMOS logic. Find one inverter
equivalent circuit (considering simultaneous switching of all inputs) of the above
mentioned logic. Assume (W/L)p=15 and (W/L)n=10
2. Implement the Boolean function f=(AB.(CD+E))’ using CMOS logic. Find any one Euler
path and use it to sketch a stick diagram of the logic.
3. What is latch up in CMOS circuits? Briefly explain the latch-up phenomenon and state
the possible measures to prevent latchup.
4. The layout for a logic function is given below. Draw the transistor level diagram and find
its function.

Module-7: High performance CMOS logic

Descriptive type
1. Discuss operation of CMOS precharge-evaluate logic (dynamic CMOS) circuit. State any
two drawbacks of this type of logic circuit. How can those drawbacks be overcomed?
2. With a neat sketch explaining the operation of NP-Domino (NORA) logic circuit. What is
the unique feature of this type of logic?
3. Implement the following logic:
A) Two input NAND gate using Dynamic CMOS logic
B) Two input XOR gate using NMOS pass transistor logic
C) 2x1 Multiplexer using CMOS transmission gate
D) Two input XOR gate using static CMOS logic with min no of transistors
E) f=(AB+CDE)’ using two stage Domino logic

4. Find out the voltages Vx, Vy, Vz and V0 of the following NMOS pass transistor logic
circuit. Threshold voltage of each NMOS transistor is 0.5V. Ignore the body bias effect.

Hint: 1st transistor can pass upto 5-Vth=5-0.5V=4.5V. Hence Vx=4.5V

2nd transistor can pass upto 4.5V, so Vy=4.5V, similarly Vz=4.5V, V0=4.5V

5. Find out the voltages Vx, Vy, Vz and V0 of the following NMOS pass transistor logic circuit.
Threshold voltage of each NMOS transistor is 0.5V. Ignore the body bias effect

Hint: 1st transistor can pass upto 5-Vth=5-0.5V=4.5V. Hence Vx=4.5V

2nd transistor can pass upto3-0.5=2.5V, so Vy=2.5V, similarly 3rd transistor can pass upto
4-0.5=3.5V, hence it can easily pass 2.5V, so Vz=2.5V. Similarly, last transistor can pass max
1-0.5=0.5V. Hence Vo=0.5V

6. Find out the voltages V01, V02, V03 of the following NMOS pass transistor logic circuit.
Threshold voltage of each NMOS transistor is 0.5V. Ignore the body bias effect. Assume
Vdd=5V.
Hint: V01=Vdd-Vth=4.5V, V02=min(Vdd,V01-vth)=4V.
V03=min(Vdd/2, V02-Vth)=2.5V.

7. Consider a conventional NP-Domino as shown in figure with all pre-charge and evaluate
devices. Assume all pull-down/pull-up single NMOS/PMOS devices so that each domino stage
consists of a dynamic inverter followed by a static inverter. Assume that the pre-charge time,
evaluation time and propagation delay of inverters are all T/2. Also assume that transistors are
ideal. State any problem occurs when input makes a 0 to 1 transition? What about a 1 to 0
transition? If any problem occurs, fix it by inserting an inverter.

8. Complement on relative merits and demerits of static and dynamic logic circuit. Implement the
following logic function using Dynamic and NORA Logic.

𝑍 = ((𝐴 + 𝐵 + 𝐶)(𝐷 + 𝐸))'

9. Explain the cascade problem in dynamic logic circuit implementation with a suitable diagram.

10.Discuss the issue of charge sharing in Domino CMOS logic and techniques used to alleviate
the issue.

11.With the help of relevant diagrams explain how pipelining is implemented in NORA logic.

Short Answer Type Questions

1.Why in pass transistor logic, the cascading of logic gates are avoided.

Ans: To avoid multiple threshold voltage drops and as a result magnitude of output voltage
decreases.

2.Mention the techniques to resolve charge sharing issue in dynamic CMOS logic

3. “In Dynamic CMOS logic direct cascading of logics are not allowed” - Cite the reason

Ans: Direct cascading of logic gates may result in incorrect output. During the beginning of
evaluation phase, node o/p=logic-1 and this makes NMOS ON and 2nd stage load capacitor may
discharge to logic-0.

4. Mention advantages of NORA CMOS logic over Domino CMOS logic.

Ans: Pipelined architecture supported.

5. What are the advantages of Dynamic CMOS technology over Static CMOS

Ans: Faster operation due to low parasitic capacitance i.e. due to low transistor count. Less area
requirement.