Adders, Subtractor, Multiplexer, Demultiplexer,

MUX Realization of switching functions,

Encoder, Decoder, Parity bit generator, Code-
converters, Basic PLD’s-ROM, PROM, PLA, PAL
Realizations.
Introduction:
• Logic circuits for digital systems may be
Combinational or Sequential.
• The output of a combinational circuit depends on
its present inputs only.
• Combinational circuits perform a specific
information processing operation fully specified
logically by a set of Boolean functions.
• A combinational circuit consists of input variables,
logic gates and output variables.
• It is a circuit having different logic gates inbuilt or
integrated in a circuit.
• The logic gates accepts signals from the inputs and
generate signals to the output.
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• This process transforms binary information from
the given input data to the required output data.
• Both input and output data are represented by
signals i.e., they exist in two possible values, one
representing logic-1 and the other logic-0.
• The output of the combinational circuit depends on
combination of input variables. It does not use any
memory i.e., the output depends on its present
inputs only.

Block diagram of a combinational circuit

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• For n- input variables, there are 𝟐𝐧 possible
combinations of binary input values.
• For each possible combination, there is one and
only one possible output combination.
• A combinational circuit can be described by m
Boolean functions one for each output variable.
• Each output function is expressed in terms of the
n-input variables.

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Design Procedure:

1) Observe the problem definition.

2) The number of available input variables and
required output variables is determined.
3) The input and output variables are assigned letter
symbols.
4) The truth table that defines the required
relationship between inputs and outputs is
derived.
5) The simplified Boolean function for each output is
obtained.
6) The logic diagram is drawn.
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Ex: Design a combinational circuit with 2-inputs
which produce output as logic 0 when any one input
is 1.
Sol: 2 inputs → 1 output
2 inputs → 4 input combinations
B
A B Y
A
0 0 1
1
0 1 0
1 0 0
1 1 0

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 Half-Adder
• Half-Adder is a combinational logic circuit designed
to add two single bit numbers.
• It contains 2 binary inputs and 2 binary outputs.
(Sum and carry bits)

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• The sum is the Ex-OR of A and B.
• The carry is the AND of A and B.

Logic diagram of Half-Adder

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 Logic diagram of Half-Adder using AOI logic

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Half-Adder using 2-input NAND gates:

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Half-Adder using 2-input NOR gates:

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 Full Adder
• A full adder is a combinational circuit that adds two
bits and a carry and outputs a sum bit and a carry
bit.
• The full adder adds the bits A and B and carry from
the previous column called the Carry-in 𝑪𝒊𝒏 , outputs
the sum bit S and the carry bit called the carry-out
𝑪𝒐𝒖𝒕 .
• The variable S gives the value of least significant
bit of the sum.
• The variable 𝑪𝒐𝒖𝒕 gives the output carry.

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 Logic diagram of Full-Adder using two Half-Adders

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Full-Adder using AOI logic:

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 Block diagram of a Full-Adder using two half-adders

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Full-Adder using 2-input NAND gates:

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Full-Adder using 2-input NOR gates:

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 Half-Subtractor
• The Half-subtractor is a combinational circuit that
subtracts one bit from the other and produces the
difference.
• It also has an output to specify if a 1 has been
borrowed.
• It has 2 inputs A and B and 2 outputs Difference (d)
and borrow (b).
• ‘b’ is the output signal generated that informs the
next stage that a 1 has been borrowed.
• It is used to subtract the LSB of the subtrahend
from the LSB of the minuend when one binary
number is subtracted from the other.

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• For A>=B → b is 0
• For A=0, B=1 → b is 1
• The d output is the result of arithmetic operation
2b+A-B

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• Output:

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Half-Subtractor using 2-input NAND gates:

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Half-Subtractor using 2-input NOR gates:

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 Full-Subtractor

• A full subtractor is a combinational circuit with 3

inputs (A,B, 𝐛𝐢 ) and two outputs difference(d) and
borrow (b).
• The 1s and 0s for the output variables are
determined from the subtraction of A - B - 𝐛𝐢 .

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Full-Subtractor using 2-input NAND gates:

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Full-Subtractor using 2-input NOR gates:

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 Binary Parallel Adder
• A binary parallel adder is a digital circuit that adds
two binary numbers in parallel form and produces
the arithmetic sum of those numbers in parallel
form.
• It consists of a full adder connected in a chain,
with the output carry from each full adder
connected to the input carry of the next full adder
in the chain.
• An n-bit parallel adder requires n full adders.
• The parallel adder in which the carry-out of each
full adder is the carry-in to the next most
significant adder is called a Ripple Carry Adder.
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 Logic diagram of a 4-bit binary parallel adder

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 Binary Parallel Subtractor

• The subtraction A-B can be done by taking 2’s

complement of B and adding it to A.
• The 2’s complement can be obtained by taking the
1’s complement and adding 1 to the least
significant pair of bits.
• The 1’s complement can be implemented with
inverters .

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 Logic diagram of a 4-bit binary parallel subtractor

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 Binary Adder-Subtractor
• The addition and subtraction operations are combined
into one circuit with one common binary adder.
• This is done by including an X-OR gate with each Full
Adder(FA).
• The mode M controls the operation.
• When M=0 → Adder → , 𝑪𝒊𝒏 =0, the circuit
performs A+B+ 𝑪𝒊𝒏 = A + B.
• When M=1 → Subtractor → , 𝑪𝒊𝒏 = 1, the circuit
performs
A + (1’s complement of B) + 𝑪𝒊𝒏 = A + (1’s complement of
B) + 1= A + (2’s complement of B) = A – B.
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 Logic diagram of a 4-bit binary parallel adder-subtractor

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 Multiplexers (Data Selectors)
• Multiplexing means Sharing.
• There are two types of multiplexing- Time
multiplexing and Frequency multiplexing.
• For example, when several peripheral devices
share a single transmission line or bus to
communicate with a computer, at any given time,
one and only one device is using the line.
• Each device in succession is allocated a brief time
to send or receive data. This is Time multiplexing.

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• In Frequency multiplexing, several devices share a
common line by transmitting at different
frequencies.
• A Multiplexer (MUX) or Data Selector is a logic
circuit that accepts several data inputs and allows
only one of them at a time to get through to the
output.
• The routing of the desired data input to output is
controlled by SELECT inputs/ADDRESS inputs.

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• Normally, there are 𝟐𝐧 input
lines and ‘n’ select lines
whose bit combinations
determine which input is
selected.
• The MUX acts like a
digitally controlled multi-
position switch.
• MUX selects 1-out of- N
input data sources and
transmits the selected data
to a single output channel.
This is called Multiplexing.

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Basic 2-input Multiplexer:

• 2 * 1 MUX → 1 Select input, 2 data inputs, 1 output

2 : 1 MUX

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4-input Multiplexer:

• 4 * 1 MUX → 2 Select inputs, 4 data inputs, 1 output

4 : 1 MUX

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 • The 2-4-8-16 input MUX are readily available in TTL
and CMOS logic families.
• These basic ICs can be contained for multiplexing
a larger number of inputs.
• Some packages contain more than one Mux.
Ex: 74157 quad 2:1 MUX (Four 2:1 Mux having the
same data select inputs) and 74153 dual 4:1 MUX.
• Most multiplexers have Enable inputs to facilitate
Cascading.
• Multiplexers may have an Enable input to control
the operation of the unit.

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• When Enable input is in Inactive state → Outputs
are Disabled.

• When Enable inputs are in Active state → the

circuit acts as a normal Multiplexer.

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8-input Multiplexer:

8 * 1 MUX → 3 Select inputs, 8 data inputs, 1 output

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8:1 MUX using two 4:1 MUX and one 2:1 MUX

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16- Input MUX using two 8-input MUX:

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• When S3 = 0, the left MUX is enabled and S2 , S1
inputs determine which of its data inputs will
appear at its output and pass through the OR gate
to final output X.
• When S3=1, the right MUX is enabled.
• This arrangement is also called Multiplexer Tree.

Applications of Multiplexers:
• Data Selection, Data Routing, Operation
Sequencing, Parallel-to-Serial conversion,
Waveform generation and logic function generation.

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Ex: Realize 16:1 MUX using 8:1 MUX

a) Using two 8:1 MUX

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b) Using two 8:1 MUX and one 2:1 MUX

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Ex: Realize 16:1 MUX using 4:1 MUX

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32-input Multiplexer:

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32:1 MUX using 8:1 MUX

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 MUX as a Logic Function Generator
• A multiplexer can be used in place of logic gates to
implement a logic expression.
• It can generate any Boolean algebraic function of a set
of input variables.
• MUX can be viewed as a function generator, because
we can easily set or change the logic function it
implements.
• One advantage of using a MUX in place of logic gates
is that, a single integrated circuit can perform a
function that might otherwise requires numerous ICs if
gates are used.
• It is very easy to change the logic function
implemented if and when redesign of a system
becomes necessary.
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• The first step in the design of a function generator
using a MUX is to construct a truth table for the
function to be implemented.
• Then, connect logic 1 to each data input of the MUX
corresponding to each combination of input
variables, for which the truth table shows the
function to be equal to 1.
• Logic 0 is connected to the remaining data inputs.
• The variables themselves are connected to data
select inputs of the multiplexer.

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Ex: Use a multiplexer to implement the logic
function
Sol:

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Ex: Implement the following function using 8:1 MUX

Sol:

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Ex: Use a 4:1 MUX to implement the logic function

Sol:

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Ex: Implement the following function with a MUX.
Choose a and b as Select inputs.

Sol:

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Ex: Use a multiplexer having three data select inputs to
implement the logic for the function given below.
Also, realize the same using 16:1 MUX.

Sol:

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Ex: Implement the function 𝐅 𝐚, 𝐛, 𝐜 = 𝐚𝐛 + 𝐛𝐜 ҧ using a 4:1
MUX.
Sol: 𝐅 𝐚, 𝐛, 𝐜 = 𝐚𝐛 + 𝐛𝐜
ҧ = 𝐚𝐛𝐜 + 𝐚𝐛𝐜ҧ + 𝐚𝐛𝐜 ҧ = m (1,5,6,7)
ҧ + 𝐚ത 𝐛𝐜

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Ex: Implement the following function using an 8:1
MUX.
Sol:

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Ex: Implement the following Boolean function using an
8:1 MUX considering D as input and A,B,C are select
lines.
ഥ + 𝐁𝐃 + 𝐁
𝐅 𝐀, 𝐁, 𝐂, 𝐃 = 𝐀𝐁 ഥ 𝐂𝐃
ഥ

Sol: 𝐅 𝐀, 𝐁, 𝐂, 𝐃 = 𝐀𝐁
ഥ + 𝐁𝐃 + 𝐁
ഥ 𝐂𝐃
ഥ

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 De-Multiplexers (Data Distributors)
• A de-multiplexer programs the
reverse operation of a MUX
i.e., it takes a single input and
distributes it over several
outputs.
• It is called a ‘Distributor’,
since it transmits the same
data to different destinations.
• A demultiplexer is a 1-to-N (or
𝟐𝐧 ) device.

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1-line to 4-line DEMUX:

The input data line goes to all

of the AND gates.
The two select lines S0 and S1
enable only one gate at a
time and the data appearing
on the input line will pass
through the selected gate to
the associated output line.

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 1-line to 8-line DEMUX:

• The single input data line D is

connected to all eight AND
gates.
• The three select lines S0, S1, S2
enable only one gate at a time
and the data appearing on the
input line will pass through the
selected gate to the associated
output line.
• For example, with
only the AND gate O0 will be
enabled and the data D will
appear at output O0.
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 Encoders
• An encoder is a device whose inputs are decimal
digits and/or alphabetic characters and whose
outputs are the coded representation of those
inputs. i.e., An encoder is a device which converts
familiar numbers or symbols into Coded format.
• An encoder has a number of input lines, only one of
which is activated at a given time and produces an
N-bit output code depending on which input is
activated.
• Here, the inputs are Active HIGH, which means
they are normally LOW.

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4*2 line Encoder (Nibble to Binary):

• Q 1 = D3 + D2 Q0= D1 +D3
• D0 is not present in the expressions. D0 is a Don’t care.

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 D3 Q1
Q1 = D3 + D2
D2

Q0
Q0= D1 +D3
D1

Logic Diagram of 4 * 2 Encoder

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8*3 line Encoder (Octal to Binary Encoder):
It accepts 8 input lines and 3-bit output code.

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 D0 is not present in the expressions.
D0 is a Don’t care.

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10*4 line Encoder (Decimal to BCD encoder):
• This type of encoder has 10 inputs- one for each
decimal digit, and 4 outputs corresponding to the
BCD code.

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There is no explicit input for decimal 0. The BCD output is
0000 when the decimal inputs (1 to 9) are all 0.
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16*4 line Encoder (Hexa-Decimal to Binary encoder):

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 Priority Encoders
• A Priority encoder is a logic circuit that responds to
just one input in accordance with some priority
system, among all those that may be simultaneously
HIGH.
• The most common priority system is based on the
relative magnitudes of the inputs; whichever decimal
input is the largest, is the one that is encoded.
• In some practical applications, priority encoders may
have several inputs that are routinely HIGH and the
same time, and the principal function of the encoder
in those cases is to select the input with the highest
priority. This function is called the Arbitration.

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• A common example is found in computer systems,
where there are numerous input devices and
several of which may attempt to supply data to the
computer at the same time.
• A priority encoder is used to enable that input
device which has the highest priority among those
competing for access to the computer at the same
time.

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4- Input Priority Encoder:

• In addition to the outputs A and B, the circuit has a

third output designated by “V”.
• This “V” is a Valid bit indicator that is set to 1 when
one or more inputs are equal to 1.
• If all the inputs are 0, there is no valid input and
V=0.
• When V=0, the other two inputs are not inspected
and are specified as Don’t Care conditions.
• Higher the subscript number, higher the priority of
the input.

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• Here, input D3 has the highest
priority. So, regardless of the
values of other inputs, when
this input is 1, the output for
AB is 11(binary 3).
• D2 has the next priority level.
The output is 10 if D2=1
provided that D3=0 regardless
of the values of other two
lower priority inputs.
• The output for D1 is generated
only if higher priority inputs are
0, and so on down the priority
levels.
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 • The condition of output V is an OR function
of all the input variables.

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• Although the table has only 5 rows, when each
in a row is first replaced by 0 and then by 1, the
possible input combinations will be 16.
• The min terms for the two functions A and B are
derived from the truth table as:

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25-03-2023 K.Hema Lalitha,Asst.Prof,GVPCE(A) 93
Decimal to BCD Priority Encoder:

• It produces a BCD output

corresponding to the highest
order decimal digit appearing
on the inputs and ignores all
others.
• The inputs and outputs are
Active LOW.
• If any decimal input is active, it
is encoded provided all higher
value inputs are inactive
regardless of the states of all
lower value inputs.
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 𝐀𝟏 = 𝐃𝟐 𝐃𝟒 𝐃𝟓 𝐃𝟖 𝐃𝟗 + 𝐃𝟑 𝐃𝟒 𝐃𝟓 𝐃𝟖 𝐃𝟗 + 𝐃𝟔 𝐃𝟖 𝐃𝟗 + 𝐃𝟕 𝐃𝟖 𝐃𝟗

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• A2 will be HIGH if:

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Octal to Binary Priority Encoder:

• The Octal- to- Binary

Priority Encoder can be
designed using 74148
IC.
• It has Active LOW inputs
and Active LOW outputs.
• The Enable input and
the Gray outputs which
are also Active LOW are
used to cascade circuits
to handle more inputs.

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Ex: Design a Hexa-Decimal to Binary encoder using
74148 encoders and 74157 multiplexer.
Sol:

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 Decoders
• A Decoder is a logic circuit that converts an N-bit
binary input code into M output lines such that only
one output line is activated for each one of the
possible combinations of inputs.
• Decoder identifies or recognizes or detects a
particular code.
• For N inputs (each input can be either 0 or 1), there
are 𝟐𝐍 possible input combinations or codes.
• For each of these input combinations, only one of
the M outputs will be Active, all the other outputs
remain Inactive.

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 General Block Diagram of a Decoder

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3 line to 8 line Decoder:

• It is also called Binary to Octal

Decoder because it takes 3- bit
binary input code and activates
one of the 8 (octal) outputs
corresponding to that code.
• It is also referred as 1-of-8
decoder because only one of the
eight outputs is activated at one
time.
• For Active HIGH outputs, all AND
gates are used.
• For Active LOW outputs, all NAND
gates are used.
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Enable Inputs

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 Enable

3 * 8 Decoder with Enable input

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BCD-to-Decimal Decoder (7442):

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2 line to 4 line Decoder:

• Some decoders are constructed using NAND gates.

• This circuit operates with complemented outputs
and complemented enable input.
• The decoder is enabled when E=0.The inputs are
Active HIGH and outputs are Active LOW.
• At any given time, only one output can be equal to
0, all other outputs are equal to 1.
• The output whose value is equal to 0 represents
the min term selected by the inputs A and B.
• The circuit is disabled when E=1, regardless of the
values of two other inputs.
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• In general, a decoder
may operate with
complemented or
uncomplemented
outputs.
• The Enable input will be
activated with either 1
or 0 signal.

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• Active LOW enable bit
Active HIGH inputs
Active LOW outputs

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4-to-16 decoder from two 3-to-8 decoders:

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4-to-16 decoder using 2-to-4 decoders:

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Applications of Decoders:

• Decoders are used whenever an output or group of

outputs is to be activated only on the occurrence
of a specific combination of input levels.
• These decoders are used as timing or sequencing
signals to turn on or off at specific times.
• Decoders are widely used in memory systems of
computers, where they respond to the address
code input from the central processor to activate
the memory storage location specified by the
address code.

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Combinational Logic Implementation (Full Adder using
a Decoder and OR gates):

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BCD-to-Seven Segment Decoder:
• This type of decoder accepts the BCD
code and provides outputs to energize
seven segment display devices in
order to produce a decimal read out.
• Each segment is made up of a
material that emits light when current
is passed through it.
• The most commonly used materials
include LEDs, Incandescent filaments
and LCDs.
• The LEDs generally provide greater
illumination levels but require more
power than that by LCDs.

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• In common Anode type, a
low voltage applied to an
LED cathode allows current
to flow through the diode,
which causes it to emit
light.
• In common Cathode type, a
High voltage applied to LED
anode causes the current to
flow and produces the
resulting light emission.
Common Cathode type is
generally used.
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 A3 A2 A1 A0

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