User Experiences with the Portable Stimulus Standard

Tom Fitzpatrick, PSWG Vice Chair

Prabhat Gupta, AMD
Mike Chin, Intel
The Biggest Change

2 © 2023 Accellera Systems Initiative, Inc.

Introducing Behavioral Coverage (WIP)
 Given a stream of action executions, find out
whether a given temporal scenario (query) occurs idle
Cov1
in this stream
write
 The cover statement specifies the interesting addr = 0x2000 read
addr = 0x1000
scenario
send
 A monitor encapsulates behaviors to be covered
wait
- A monitor may be implicit (in a cover statement) or explicit read
addr = 0x2000

action write { rand bit [32] addr; }

action read { rand bit [32] addr; } Cov2
monitor read_after_write { write w; read r; activity { w; r; }} wait write
cover Cov1 { read_after_write wr; activity { wr with r.addr == w.addr; }}
idle write
cover Cov2 { write w1, w2; read r; activity { w1; r overlaps (w2) ;} send read

3 © 2023 Accellera Systems Initiative, Inc.

Behavioral Coverage Tracking
 Action traversal (e.g., do A with x == 5): A
- Match nearest action execution matching imposed constraints
 Concatenation: concat { m1; m2 } m1 m2
- Match first m2 after m1
- Match m1 from the current point; from every match point of m1 match m2

 Eventually: eventually m
m
- Some time in the future
- Match m from everywhere, starting from the current point

 Sequence: sequence { m1; m2 } or { m1; m2 }

- Match m2 after m1, not necessarily immediately
- Match m1 from the current point; starting from the match of m1 match m2 from every point
- Equivalent to concat { m1; eventually m2 }

 Overlaps: {m1 overlaps m2} m1

- Match m1 if m2 executes at any point while m1 is executing m2
 Select: select { m1; m2 }
m1
- Match either m1 or m2
4 © 2023 Accellera Systems Initiative, Inc.
m2
Solve/Runtime Messaging
 New addition to the Core Library
- Solve time solve function void print_foo(my_struct s) {
print("The context of the struct is:\n");
- format print("value = %d\nname = '%s'\n", s.value, s.name);
- print }
solve function string get_foo_context_string(my_struct s) {
return format("value = %d\nname = '%s'\n", s.value, s.name);
}

- Runtime exec body {

y = my_func();
- message message(FULL, "The values of the variables x and y are: ");
message(LOW, "%d, %d", x, y);
}

- Either package io_pkg { // may change to std_pkg or…

- error/fatal function void error(string format, type... args);
function void fatal( int status, string format, type... args);
}
returned to calling
environment

5 © 2023 Accellera Systems Initiative, Inc.

Solve/Runtime Messaging
 Solve-Time File I/O
- Via file handles package io_pkg {
typedef chandle file_handle_t;
static const file_handle_t nullhandle = /* implementation-specific */;
enum file_option_e {TRUNCATE, APPEND, READ};
function file_handle_t file_open(string filename, file_option_e opt = TRUNCATE);
function void file_close(file_handle_t file_handle);
function bool file_exists(string filename);
function void file_write(file_handle_t file_handle, string format, type... args);
function string file_read(file_handle_t file_handle, int size = -1);

- Single Functions function void file_write_lines(string filename, list<string> lines,

file_option_e opt = TRUNCATE);
function list<string> file_read_lines(string filename);}

6 © 2023 Accellera Systems Initiative, Inc.

List randomization
 Lists can now be
declared rand struct S {
rand list<bit[8]> lst;
- Randomized when its exec pre_solve { // Initialize the list
container is randomized repeat (100) {
lst.push_back(0);
- Just like other rand fields }
}
 The size is considered a constraint {lst.size() in [4..100]; // Error: illegal constraint on size
state variable foreach (lst[i]) {
lst[i] == i+lst.size(); // OK: size is a state variable in foreach
- size cannot be constrained }
directly }
}

7 © 2023 Accellera Systems Initiative, Inc.

Procedural randomization statement
 Allowed in solve exec blocks
will be randomized as
 Subset allowed in struct S1 { v1.f1.a, [0..14]
rand bit[8] a, b;
target exec }
v1.f1.b
- No struct randomization
struct S2 { random
 Also supports rand S1 f1;
S1 f2; non-random
- urandom constraint f1.a < f2.a;
active constraint
}
- urandom_range f1.a < 100
action A {
exec post_solve {
S2 v1;
bit[4] v2; will be randomized
v1.f2.a = 100; inline constraint
randomize v1, v2 with {v1.f1.a < v2;} f1.a < 15
}
} randomize two variables

8 © 2023 Accellera Systems Initiative, Inc.

Dist randomization constraint
 Similar to SystemVerilog
- := assigns a specific weight struct S {
- :/ distributes weight across a list rand bit[32] x;
bit y;
 Subject to other constraints
constraint dist x in [100..102 := 1, 200 := 2, 300 := 5];
- dist only biases values in the legal
100:1, 101:1, 102:1, 200:2, 300:5
range

constraint dist x in [100..102 :/ 1, 200 := 2, 300 := 5];

100:1/3
101:1/3, 200:2, 300:5
102:1/3

constraint dist x in [100..102 := 1, 200 := 2, 300 := 5];

constraint (y==1) -> x > 300; Constraint causes dist
} to be ignored

9 © 2023 Accellera Systems Initiative, Inc.

Labels as action handles
 Labels as action handles
- Create handle for anonymous action traversal
action mem2mem_chain {
- Can be referenced from above activity {
do mem_c::load_buff;
repeat (10) {
select {
xfer: do dma_c::mem2mem_xfer;
cpy: do cpu_c::memcpy;
}
}
}
}

action my_test {
activity {
do mem2mem_chain with { xfer.size > 10; };
}
}
dma_c::mem2mem_xfer

10 © 2023 Accellera Systems Initiative, Inc.

Inference Issue
state config_s {
rand mode_e mode;
}

action configX {
output config_s out_cfg;
constraint out_cfg == X; bringup
} bringup

action B {
input config_s cfg;
constraint cfg.mode == X; A
}
configX A
action my_stress_seq {
activity {
do bringup; configX
do A; mode X
do B; mode X Stress is not achieved
} B should start immediately because relevant
}
after A completes – it’s a B B
critical aspect of the intent behavior is spaced
In reality B may
start long after apart or diluted
A completes

11 © 2023 Accellera Systems Initiative, Inc.

Inference For “Atomic” Block
Inferred action is
scheduled prior to
the atomic block
bringup
The atomic activity block guarantees
that the invocation of each action configX bringup
does not wait for any action other than
its predecessor in the sequence configX mode X
mode X
action my_stress_seq {
Atomic block
activity { doesn’t start
do bringup; A A until all its
do A; {
atomic dependencies
dodo
B;A; are met
} do B;
} }
Any dependency of B B
}
} B is a dependency
of the entire block

12 © 2023 Accellera Systems Initiative, Inc.

Concise read-modify-write
 Added a way to read-modify-write
struct CR : packed_s<> {
in a single operation bit en;
pure component reg_c < type R, bit[11] pad;
reg_access ACC = READWRITE, bit[4] mode;
bit[16] coeff;
int SZ = (8*sizeof_s<R>::nbytes)> { }
function R read();
component dut_c {
function void write(R r); dut_regs_c regs;

function bit[SZ] read_val(); action cfg_a {

rand bit[4] mode;
rand bit[16] coeff;
function void write_val(bit[SZ] r); exec body {
comp.regs.cr.write_masked(
function void write_masked(R mask, R val); {.mode=~0, .coeff=~0}, {.mode=mode, .coeff=coeff});
function void write_val_masked(bit[SZ] mask,
bit[SZ] val); comp.regs.cr.write_val_masked(0xFFFFF000,
(coeff << 16) | (mode << 12));
function void write_field(string name,
bit[SZ] val); comp.regs.cr.write_fields({“mode”, “coeff”},
function void write_fields(list<string> names, {mode, coeff});
list<bit[SZ]> vals); }
} }
}

13 © 2023 Accellera Systems Initiative, Inc.

Additional New Features
 Static functions in components
- Function declaration associated with the component type (not instance)
- Called via the “::” scope operator

 Tag/Addr_value
 Enum base type
 Floating Point computation and storage types

14 © 2023 Accellera Systems Initiative, Inc.

AI Engine Subsystem Verification With PSS

Prabhat Gupta - AMD

Agenda
 Introduction
 PSS initial approach – tackle portability
 First-class PSS model
 Constraints
 PSS Methodology
 Conclusion

16 © 2023 Accellera Systems Initiative, Inc.

Introduction
 Verification of a grid of general-purpose AI Engines
- AI Engine information is available at
https://www.xilinx.com/products/technology/ai-engine.html AIE array

 Example use cases of AI Engine array Compute Compute Compute Compute

- Auto framing and eye gaze correction with Microsoft Teams Compute Compute Compute Compute

- Low power background blur, audio noise reduction, etc. Compute Compute Compute Compute

 Highly configurable network fabric Mem Mem Mem Mem

 Compute, Memory, and Shim engines Shim Shim Shim Shim

 Connected to SoC with a high-speed on-chip data network

and pervasive control network Control Processor
 Grid of engines and highly configurable network makes Subsystem
creating functional, performance, and post-silicon validation
tests very challenging

17 © 2023 Accellera Systems Initiative, Inc.

Circuit-switched DMA
 More than one channel going east-west or north-south
 Multi-hop acyclic paths for DMAs
 Adjacent columns can be isolated as a group
 DMAs can’t cross the isolation boundary

18 © 2023 Accellera Systems Initiative, Inc.

AI sub-system

 AI Array with embedded control

processor AIE array
Registers

 AI array can be subdivided for isolated

parallel work from different NOC
applications
 Host processor sends work to NOC

embedded processor Address

Embedded SoC
Translation
Processor Comm

 Embedded processor sends compute

kernels to AIE array

19 © 2023 Accellera Systems Initiative, Inc.

Testbench environments
AIE array
 IP only NOC
UVC
- AIE array UVM/C++ environment

 Subsystem PSS
- AIE array with an embedded processor running C code
with UVM/C++ environment Registers AIE array
 Full SoC
NOC
- X86 processors, AIE subsystem, and rest of chip
- C code running on x86 and embedded processor NOC

Address
 Post-silicon bring-up and validation Translation
Embedded
Processor
SoC
Comm
- C code running on the main and embedded processor

X86 cores

20 © 2023 Accellera Systems Initiative, Inc.

Verification Challenges
 AIE Array
- Many possible paths through the AI engine array
- Compute array can be configured into different partitions, which impacts routing
- Need to exercise many combinations to verify routing/arbitration throughput/latency
- Legal pseudo-random paths for routing
- Challenging to account for possible parallel DMAs without a lot of procedural code in a complex test
- Lots of boilerplate code for new tests
 Subsystem
- Need to verify new interfaces
- Most tests in UVM, take advantage of randomization/coverage with the embedded processor in bypass
- A lot of boilerplate code for each test
- Some bare-metal content for the embedded processor, but it’s a huge barrier, not usually done
 SoC
- Need bare-metal test content, but only have UVM content
- Must develop multi-core tests to exercise key cases  multicore is always a challenge
- Synchronization across AIE and other IP are challenging

21 © 2023 Accellera Systems Initiative, Inc.

 The value – portability

PSS FIRST STEPS

22 © 2023 Accellera Systems Initiative, Inc.

An AIE Test
 Power up and bring the AIE array out of the reset with the UVM testbench
 Boot AIE array
- Initialization sequence in PSS

 Configure AIE array isolation with PSS

- Adjacent columns isolated to work on different applications
- Find a valid random isolation setup, that could be user-supplied, and do isolation programming

 Configure acyclic circuit-switched DMA circuits with PSS

- Find N random valid circuits across all isolation units, program the circuits

 Generate traffic
- Run M parallel DMAs and check the results
- Select valid routes from the last step

 Repeat with new isolation setup

23 © 2023 Accellera Systems Initiative, Inc.

PSS first steps for AIE project
 UVM to PSS – started at IP level
- Mostly procedural code converted from UVM to PSS AIE array
- Fixed column isolation setup and DMA circuits
NOC
UVC
- PSS address spaces and registers

 Portability to the embedded control processor (CP) PSS

- Address space adapted to CP address map and TLBs

 Value Registers AIE array

- NOC randomization
- New tests running on the control processor NOC

- Test available for post-silicon bring up NOC

Address Embedded
Translation SoC
Processor Comm

24 © 2023 Accellera Systems Initiative, Inc.

 How does the PSS portability work?

PSS MODEL INTEGRATION

25 © 2023 Accellera Systems Initiative, Inc.

AIE IP PSS Integration
component pss_top {
transparent_addr_space_c<aie_mem_trait_s> mem;
transparent_addr_space_c<mem_trait_s> sysmem;

exec init_down { AIE array

// Add PSS executors to map to UVCs
// May have some tool-specific setup for integration
// Call to add_executor
...

// Memory setup UVC

repeat(col: COMPUTE_TILE_COLS) {
repeat (row: COMPUTE_TILE_ROWS) {
PSS tool-specific
transparent_addr_region_s<aie_mem_trait_s> tile_region;
integration
usually calling
aie_tile_region.size = COMPUTE_MEM_SIZE;
UVM sequence
aie_tile_region.addr = compute_tile_base(row, col);

aie_tile_region.trait.mem_block = COMPUTE_TILE;
aie_tile_region.trait.row = row + COMPUTE_TILE_START_ROW;
aie_tile_region.trait.col = col;
exec body {
(void)mem.add_region(tile_region); comp.regs.SOME_REG.write_val(0xdeadc0de);
}; …
}; write32(mem_handle, 0x12345678);
}
transparent_addr_region_s<mem_trait_s> sysmem_region;
(void)sysmem.add_region(sysmem_region);
...
26 © 2023 Accellera Systems Initiative, Inc.
AIE Subsystem PSS integration
component pss_top {
exec body {
transparent_addr_space_c<aie_mem_trait_s> mem;
comp.regs.SOME_REG.write_val(0xdeadc0de);
transparent_addr_space_c<mem_trait_s> sysmem;
…
write32(mem_handle, 0x12345678);
exec init_down {
}
// Add PSS executors to map to Embedded Processor
// May have some tool-specific setup for integration
// Call to add_executor exec body {
... *(volatile uint32_t*) SOME_REG_ptr = 0xdeadc0de;
*(volatile uint32_t*) mem_handle_ptr = 0x12345678;
// Memory setup }
repeat(col: COMPUTE_TILE_COLS) {
repeat (row: COMPUTE_TILE_ROWS) {
transparent_addr_region_s<mem_trait_s> tile_region;

aie_tile_region.size = COMPUTE_MEM_SIZE;
aie_tile_region.addr = TLB(compute_tile_base(row, col));
Registers AIE array
aie_tile_region.trait.mem_block = COMPUTE_TILE;
aie_tile_region.trait.row = row + COMPUTE_TILE_START_ROW;
NOC
aie_tile_region.trait.col = col;

(void)mem.add_region(tile_region);
}; NOC

};
transparent_addr_region_s<mem_trait_s> sysmem_region; Address
Embedded SoC
(void)sysmem.add_region(sysmem_region); Translation
Processor Comm
...
}
}
27 © 2023 Accellera Systems Initiative, Inc.
SoC PSS integration
 Multiple executors
- One embedded processor and a few x86 processors
Registers AIE array
 Two test compilation units
- Tool-specific setup to generate test code for x86 and embedded control NOC
processor

 PSS action synchronization across executors

NOC

Address Embedded
- Tool-specific implementation, usually memory-based mailboxes Translation Processor
SoC
Comm

 PSS Memory setup

- Shared system memory
- Local AIE memories
X86 cores

28 © 2023 Accellera Systems Initiative, Inc.

 How it should be

FIRST-CLASS PSS MODEL

29 © 2023 Accellera Systems Initiative, Inc.

Desired PSS model capabilities/example tests
PSS model capabilities Example tests
Setup random isolation groups N parallel DMAs with random circuits in a
Setup multiple acyclic circuits in an isolation random isolation setup
group
N parallel DMAs with random circuits in an
Multiple parallel DMAs with data checks
Enable inference for simple test writer isolation setup with all columns as one group
interface Maximum parallel DMAs to system memory
A simple PSS Test API that allows random Validate every point-to-point path in the AIE
and directed tests grid
action aie_dma_one_group { action aie_dma {
activity {
activity {
do setup_isolation with { parallel {
out_iso_state.num_iso_groups == 1; replicate (N) { do aie_c::dma; }
} };
};
parallel { };
replicate (N) { do aie_c::dma; }
};
};
};

30 © 2023 Accellera Systems Initiative, Inc.

PSS model
PSS TOP
AI Subsystem

AIE array

Memory
Test action Compute Compute Compute Compute

dma_compute2compute Compute Compute Compute Compute

Resource
pool dma_compute2mem
Compute Compute Compute Compute
Buffer dma_compute2shim
pool Mem Mem Mem Mem
dma_mem2compute
Stream
dma_mem2mem Shim Shim Shim Shim
pool

dma_mem2Shim
exec_init
dma_shim2compute Control Processor
…
Subsystem

31 © 2023 Accellera Systems Initiative, Inc.

PSS model
component aie_tile <int NO_DMA,int NO_BD>
{ Abstract base actions in separate files. Allows project-specific
pool [NO_DMA] dma_chan_s chan_pool;
action implementation while keeping high-level tests the same
action configure_isolation {}

action configure_switch {} component mem_tile <

int MEM_SIZE, component Translation,
action stream_to_mem {} int NO_DMA, int NO_BD>
: aie_tile<NO_DMA, NO_BD>
action mem_to_stream {} {
} Translation translation;
}

component compute_tile <

component tile_addr_translation_c { int MEM_SIZE, component Translation,
int NO_DMA, int NO_BD>
target function bit[64] translate( : aie_tile<NO_DMA, NO_BD>
addr_handle_t hndl, {
bit[64] base_address) Translation translation;
{ }
bit[64] addr;
...
return (addr); component shim_tile< int NO_DMA, int NO_BD >
} : aie_tile<NO_DMA, NO_BD>
} {}

32 © 2023 Accellera Systems Initiative, Inc.

Test composition
Test Solved scenario
action sysmem2computedma {
activity {
sysmem2computetile_dma_parallel with {
in_circuits_state.num_isolation_groups == 1;
}; setup_isolation write_ipu_data
};
};

setup_circuits

aie_profile_state_s aie_circuit_state_s
num_isolation_groups 1

mem2stream stream2mem

sysmem2computetile_dma_p
check_dma
Flow Object
Data flow

Test action
Control flow
Inferred action

33 © 2023 Accellera Systems Initiative, Inc.

Test API design process
dma_compute2compute
 State object to store current circuit state
action dma_compute2compute_parallel {
- Max size circuits array in state object
input circuit_state_s circuits_in;
- Most rules about circuits encapsulated in state object output circuit_state_s circuits_out;

 First try // constraint rules to create output circuit state

// from the input circuit state
- Action input current circuit state and output updated // ...

circuit state with new circuits rand array<circuit_node_s, MAX_CIRCUITS> src;

rand array<circuit_node_s, MAX_CIRCUITS> dst;
 Problem rand int in [1..MAX_CIRCUITS] parallel_count;
- Huge constraint space for doing two DMAs in series activity {
parallel {
- Sparse solution space with constraints on input and replicate(i: parallel_count) {
output state objects do compute_tile::mem_to_stream with {node == src[i];}
do compute_tile::stream_to_mem with {node == dst[i];}
}
action two_dma { }
}
activity {
}
do dma_compute2compute_parallel;
do dma_compute2compute_parallel;
}
}
34 © 2023 Accellera Systems Initiative, Inc.
Test API design process
dma_compute2compute
 State object to store current circuit state
- Max circuits array action dma_compute2compute_parallel {

 Preferred solution input circuit_state_s circuits_in; // Only INPUT

- Constraints for isolation and circuits in the state object rand array<circuit_node_s, MAX_CIRCUITS> src;
rand array<circuit_node_s, MAX_CIRCUITS> dst;
- DMA actions have an input state object but no output
rand int in [1..MAX_CIRCUITS] parallel_count;
state
activity {
 Tip parallel {
replicate(i: parallel_count) {
- A generic DMA action, that inputs the current state do compute_tile::mem_to_stream with {node == src[i];}
manipulates it, and then outputs it, is not always a good do compute_tile::stream_to_mem with {node == dst[i];}
}
solution for high-level test space modeling with PSS }
- This generic action is very procedural that unnecessarily }
}
adds to constraint-solving complexity
- Be cognizant of PSS global constraint-solving semantics

35 © 2023 Accellera Systems Initiative, Inc.

Test API – building block actions
Test API design

• Constraint space and usability concerns affect the Test API design most
• Quick iterations on API design is highly desirable

Three levels of test API – building block actions

• Level 1
• Fully encapsulated sub-IP or IP model with registers, initialization, and programming sequences
• E.g., compute, mem, and shim tile PSS components with mem_to_stream and stream_to_mem
actions
• Not directly used to create tests
• Level 2
• Main test writers' interface
• For example, sysmem2computetile_dma_parallel action from AIE component
• Level 3
• Simplified high-level test interface used by the architect, SoC DV, and post-silicon
• DMA action to do DMA from a given tile to another tile

36 © 2023 Accellera Systems Initiative, Inc.

 They are powerful and dangerous

CONSTRAINTS

37 © 2023 Accellera Systems Initiative, Inc.

Constraint efficiency
 Constraints are the backbone of the PSS model
- Allows for action inference, flow object binding inference, describe state and resource rules

 PSS models formulate a global constraint-solving problem

- Local randomization in PSS 2.1 should contain the constraint-solving problem for data-only randomization

 Efficient constraints are extremely important for PSS models

 TIPS
- Only expose important attributes of test space as rand for test space exploration
- E.g., random DMA channel allocation is important as a model attribute but not so much the data for DMA
- Explicitly restrict the domain of a random attribute
- E.g., DMA channel number shouldn’t be ‘rand int’ but ‘rand int in [0..MAX_DMA-1]’

38 © 2023 Accellera Systems Initiative, Inc.

Constraint efficiency – example problem
 Group adjacent columns as an isolation group
Col 0 Col 1 Col 2 Col 3
 Problem – create random legal isolation groups
 Isolation group examples
- One group - [Col 0, Col 1, Col 2, Col 3]
- Four groups - [Col 0], [Col 1], [Col 2], [Col 3]
- Two groups - [Col 0, Col 1], [Col 2, Col3]
- Two groups - [Col 0, Col 1, Col 2], [Col3]
- Two groups - [Col 0], [Col 1, Col 2, Col3]
- Three groups – [Col 0], [Col 1, Col 2], [Col 3]
- Three groups – [Col 0, Col 1], [Col 2], [Col 3]
- Three groups – [Col 0], [Col 1], [Col 2, Col 3]

39 © 2023 Accellera Systems Initiative, Inc.

Constraint search space
 Get N good mango baskets from M baskets action eat_good_mangoes {

- Which basket is bad is not important rand array<int in [1..MAX_MANGO], MAX_BASKET> baskets;

 Constraint solver needs to find values of rand array<bool, MAX_BASKET> good_baskets;

all rand attributes that satisfy the rand int in [0..MAX_BASKETS] num_good_baskets;
}
constraints
 The possibility space of the cross of rand Size of constraint space = MAX_MANGO *
attributes domain size is the constraint MAX_BASKET *
space MAX_BASKET * 2
MAX_BASKET

action eat_good_mangoes {

rand array<int in [1..MAX_MANGO], MAX_BASKET> baskets;

// Reduced constraint space

// index from 0 to no_good_baskets-1 are good in the baskets array
rand int in [0..MAX_BASKETS] num_good_baskets;
}

40 © 2023 Accellera Systems Initiative, Inc.

Constraint efficiency – a complex solution
action setup_isolation {
constraint foreach (g:isolation_profile[i]) {
// This array is one isolation profile that would use all columns if(i < no_of_groups) {
rand array<array<int in [-1..NO_OF_COL-1], NO_OF_COL>,NO_OF_COL> isolation_profile; foreach (g[j]) {
rand array<int in [-1..NO_OF_COL-1], NO_OF_COL*NO_OF_COL> col_index; if(j < group_sizes[i]) {
g[j] == columns[col_index[i*NO_OF_COL + j]]; 2D array of valid groups
}
rand int in [1..NO_OF_COL] no_of_groups;
else {
rand array<int in [0..NO_OF_COL], NO_OF_COL> group_sizes; g[j] == -1; [0, 1, 2, 3]
}
rand int in [0..NO_OF_COL-1] columns[NO_OF_COL]; }
constraint unique {columns};
}
}
0 1 2 3
constraint group_sizes.sum() == NO_OF_COL;

constraint foreach (group_sizes[i]) {

constraint foreach (g:isolation_profile[i]) {
if(i >= no_of_groups) {
-1 -1 -1 -1
if(i >= no_of_groups) {
-1 -1 -1 -1
foreach (g[j]) {
group_sizes[i] == 0; g[j] == -1;
} else { }

}
group_sizes[i] >= 1;
}
} -1 -1 -1 -1
}
exec post_solve {
constraint col_index[0] == 0;
printf("################ Isolation profile ##################\n");
constraint foreach (g:isolation_profile[i]) { printf("No of isolated col groups: %d\n", no_of_groups);
if(group_sizes[i] > 0) { foreach (g:isolation_profile[i]) {
if(i < no_of_groups) { if(group_sizes[i] > 0) {
foreach (g[j]) { outf("(");
if(j < group_sizes[i]) {
if(i ==0 && j == 0) { foreach (g[j]) {
col_index[0] == 0; if(j < group_sizes[i]) {
} outf("%d,",g[j]);
else { }
col_index[i*NO_OF_COL + j] == col_index[i*NO_OF_COL + j - 1] + 1; }
} }
} }
else { }
col_index[i*NO_OF_COL + j] == col_index[i*NO_OF_COL + j - 1]; };
}
}
}
}
}
41 © 2023 Accellera Systems Initiative, Inc.
Constraint efficiency:
a simple efficient solution
// Stores the last column of an isolation group
rand array <int in [0..MAX_ISOLATION_GROUPS-1], MAX_ISOLATION_GROUPS> last_elem_of_group;

// Used for forcing DMAs into isolations so they aren't empty if we want
rand int in [1..MAX_ISOLATION_GROUPS] num_nonempty_groups;

// Ensure groups are continuous and don't skip over each other
constraint foreach(gb:last_elem_of_group[i]) {
Compact representation
of the solution
if(i < MAX_ISOLATION_GROUPS-1) { // Only look at valid isolation groups
if( i < num_nonempty_groups-1) { // Only look at non-empty groups

// last column of a group must be less than last column of the next group
last_elem_of_group[i] < last_elem_of_group[i+1];
}
else { One group of all columns Last element of group
// group everything that is not valid
last_elem_of_group[i] == last_elem_of_group[i+1]; [0, 1, 2, 3] 3 X X X
}
}
}
// Last element of the last isolation group must be the last column
constraint last_elem_of_group[MAX_ISOLATION_GROUPS-1] == MAX_ISOLATION_GROUPS-1;

42 © 2023 Accellera Systems Initiative, Inc.

Constraint space comparison
2D array of valid groups Last element of group 2D array of valid groups Last element of group

[0, 1, 2, 3] [0, 1], [2, 3]

0 1 2 3 3 X X X 0 1 -1 -1 1 3 X X
-1 -1 -1 -1 2 3 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1

[0], [1], [2], [3] [0], [1, 2], [3]

0 -1 -1 -1 0 -1 -1 -1
0 1 2 3 0 2 3 X
1 -1 -1 -1 1 2 -1 -1
2 -1 -1 -1 3 -1 -1 -1
3 -1 -1 -1 -1 -1 -1 -1

The symmetry of the solution space presents a bigger search space for constraint solver

43 © 2023 Accellera Systems Initiative, Inc.

Constraint - conclusion
 Design symmetry-free solution space when possible
- Only one possible representation of the solution in the constraint model

 Minimize action inference for test writer interface actions

- If a compound action always causes inference of another action, add that action explicitly

 Use explicit binds where possible

- Usually, a constraint solver is used for the possible binding of inputs and output
- Explicit binding reduce constraint complexity

 Avoid chaining of complex constraints from input to output

- For example, avoid, constraining all output flow object fields except a few equal to input flow object fields

 Design PSS model to only expose important random attributes to the next integration level
- A poorly designed constraint model could easily overwhelm current and future constraint solvers
- Only allow free random attributes at system-level that are important for system-level tests

44 © 2023 Accellera Systems Initiative, Inc.

 A language can only do so much

PSS METHODOLOGY

45 © 2023 Accellera Systems Initiative, Inc.

PSS methodology - call to action
 Create industry-wide PSS methodology library like UVM
- Common types to facilitate smooth multi-IP and third-party integration
- Support virtualization and address translation to work across IPs including third part IPs

 Create high-level open action libraries for the standard protocols that work across vendors
- PCIe, CXL, UCIe, etc.

 Create a forum for community-maintained design patterns

- For example, Power state transitions with interleaved traffic

 Publish best practice guidelines

- Constraint modeling
- Code structuring

 Improve PSS action export methodology for use in the production firmware

46 © 2023 Accellera Systems Initiative, Inc.

PSS deployment strategies
 Start small and provide immediate value
- Refactor initial design to create a first-class PSS model

 Starting a PSS project at any integration level is good

- SoC with processors
- It’s difficult to create random, multi-IP tests manually in C for the processors
- Use PSS for random, multi-engine functional, stress, and power tests
- Sub-system UVM and/or SystemC
- New tests can be created quickly. Reduced boilerplate for tests
- Scenario randomization as compared to data randomization
- Focus on describing system rules and encapsulated functionality then use PSS automation to create new tests
- IP
- PSS allows better reasoning of resource modeling and config space for an IP (see DVCON US 2022 presentation)
- PSS-based portable programming sequences help your friends at SoC and post-silicon (if they are friends)

47 © 2023 Accellera Systems Initiative, Inc.

Conclusion
 Reduced test development costs with portability
- IP programming sequence can be used in post-silicon bring-up, validation, and manufacturing tests
- PSS enables the rapid creation of complex tests that identify functional, power, performance, and firmware bugs in
heterogeneous multi-processor systems through randomized, multi-IP testing
 PSS improves communication among Architecture, Firmware, DV, and Post-silicon teams
through formal high-level language, leading to fewer bugs
- Describe and share SoC configuration, Inter-IP initialization, and power sequencing at high-level
- The PSS language allows for effective communication through its semantics and constructs, serving as an
executable specification
 Better post-silicon bring-up and validation
- Generate a range of tests, from simple to complex, in thousands, for effective bring-up, validation, and optimization
- Collect generation-time and runtime reports to demonstrate and analyze coverage
 Creating new tests is fun with PSS
- Reduced friction for creating new tests, especially multi-IP tests
- Understanding every detail of SoC is not required with PSS partial scenario specification
- Improved productivity is personally satisfying for engineers

48 © 2023 Accellera Systems Initiative, Inc.

Q&A
Approaches and Challenges to Scalable Modeling
DVCon 2023
Mike Chin, Principal Engineer, Intel Corporation
([email protected])
Motivation/Need for Portable Stimulus
 Lower ramp up cost for new validation engineers
- Simplify content creation
- Hide complexity - realization layer
- Drive efficient productivity!

 Grow expertise from “user” to “power user”

- User – verification engineer
- Power users – model developers, backend developers, debuggers

 “Correct by construction” validation content

- Drive accurate modeling to ensure test content correctness through implicit actions

Portable Stimulus has the promise to accelerate verification

through ease of creation and accuracy of verification content!

51 © 2023 Accellera Systems Initiative, Inc.

Challenges to Scalable Modeling
- Premise
- Pace of innovation, complexity of design Platform Configuration/
continues to increase Attached Devices
- Verification resources (at best!) remain
constant
- How do we effectively validate across the Testbench/ Feature
continuum? Realization Enhancements/
Layer Changes

How do we comprehend this problem?

What methodologies can we use to IP -> Model Use Cases
maximize development ROI? Subsystem -> (Focused -> Random -> AI)
SoC

52 © 2023 Accellera Systems Initiative, Inc.

 1 package dvcon2023 {

Our Modeling Problem 2

3
enum fsm_state { On, Off, Ready };
state state_t {
4 fsm_state cacheState;

Simple state machine IP

5 };
6

 States:  Actions:
7 component BasicIP {
8 pool state_t fsmState;

 On  PowerUp 9 action PowerUp {

10 output state_t outState; constraint outState == On;
 Ready  PowerDown 11 };

 Off  Initialize 12 action PowerDown {

13 input state_t inState; constraint inState == Ready;

 Read 14 output state_t outState; constraint outState == Off;

15 };
- Support 2 independent FSM instances 16 action Initialize {
17 input state_t inState; constraint inState == On;
18 output state_t outState; constraint outState == Ready;

How do we create scalability in our model? 19 };

How do we deal with the same model 20 action Read {

executing on different platforms? 21 input state_t inState; constraint inState == Ready;

Enhancements for a new project? 23 output state_t outState; constraint outState == Ready;
24 };
25 };
Base Model + Extend vs. Override
26 };
53 © 2023 Accellera Systems Initiative, Inc.
Extend vs. Override in modeling logic

“Base” model How do we build reusability

- Reusable, core modeling logic and scalability into our
consisting of: models?
- Actions - Use SW best practices!
- Buffers, Streams, States
- Extend models
- Resources, pools
- Support new capabilities through “extend”
- Scalable models address different language syntax
execution platforms, model - Override settings
configurations, and use cases - Constrain model settings to reflect
- A scalable realization layer is challenging to project/configuration values
implement

54 © 2023 Accellera Systems Initiative, Inc.

Extend
 Use to support capabilities not present in
the base model 1 package dvcon2023 {

- Optional features/New enhancements 2 extend enum fsm_state [ Busy ];

3 extend component BasicIP {
- Platform-specific configuration support 4 action Write {

- SoC/Subsystem integration 5 input state_t inState; constraint inState == Ready;

6 output state_t outState; constraint outState == Busy;
 Support for new logic capabilities 7 };

- Actions 8 action PollCompletion {

9 input state_t inState; constraint inState == Busy;
- Enum/struct members 10 output state_t outState; constraint outState == Ready;

- Resources 11 };
12 };
13 };

55 © 2023 Accellera Systems Initiative, Inc.

Override
// Platform 1 (Post-si)
1 package dvcon2023 {
2 extend component BasicIP {
3 function IPPowerDown();
 Configurable parameters in the base model 4 };

that are overridden per project/configuration 5 extend action BasicIP::PowerDown {

6 exec body { comp.IPPowerDown(); }
- Number of subdevice instances 7 };
- Agent count 8 };

- Target types
// Platform 2 (Pre-si testbench)

 Additional constraints to specify component 1 package dvcon2023 {

variable value ranges or specific values 2 extend component BasicIP {

3 function SidebandShutOffClocks();
- Base models must be written to be configurable! 4 function SidebandVerifyControllerPowerState();
5 action PreSiPowerDown : PowerDown {
6 exec body {
7 comp.SidebandShutOffClocks();
8 super;
9 comp.SidebandVerifyControllerPowerState();
10 }
11 };
12 };
13 };

56 © 2023 Accellera Systems Initiative, Inc.

Challenges to Extend vs. Override

Realization Layers Base vs. Extend vs. Override

- Scalable support for all permutations: - Extend/Override are useful
- Model scope (IP -> Subsystem -> SoC) mechanisms for expanding model
- Platforms support
- Devices - When do we make the decision to put
- Traffic generators something back into the base model?
- Use cases (focused tests, randomization,
AI)
- Extend/Override mechanisms need to
be carefully managed!

57 © 2023 Accellera Systems Initiative, Inc.

Challenges to Scalable Modeling
Modeling capabilities Scalable Subsystem/SoC
- Dynamic hardware problems still pose support
challenges to scalable modeling - Intuitive model composition with
- Dynamic bandwidth calculation/throttling multiple IP models
- Reconfigurable transport layer modeling - Layered support for subsystem/SoC
features
Vendor/use case specialization
- Working in 2 languages is Input collateral for model
cumbersome configuration
- Language support for vendor tool - Leveraging non-PSS config files
capabilities
- Convert to PSS is the only option
- Randomization tools
- AI workflows/tools
58 © 2023 Accellera Systems Initiative, Inc.
Summary - Challenges to Scalable Modeling
 Premise
- Pace of innovation, complexity of design Platform Configuration/
continues to increase Attached Devices

- Verification resources (at best!) remain constant

Testbench/ Feature
Realization Enhancements/
Layer Changes

Modularity modeling approaches supported by

PSS drive efficient reusability and scalability IP -> Model Use Cases
across a wide variety of verification challenges! Subsystem -> (Focused -> Random -> AI)
SoC

59 © 2023 Accellera Systems Initiative, Inc.

Q&A
Panel Discussion