R20

Code No: R20A0506

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Regular Examinations, February 2022
Computer Organization
(CSE, CSE-AI&ML, CSE-CS, CSE-DS)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 Explain different functional units of a digital computer with neat sketch. Recall the [14M]
usage of Signed number representations
OR
2 Recall the Multiplication algorithms used in Computer Arithmetic. Convert the [14M]
following binary number into decimal & octal number:
i) (00010.110)2 ii) (000.10110)2
SECTION-II
3 List and explain the steps involved in the execution of a complete instruction [14M]
cycle. List the basic symbols used in register transfer Language
OR
4 Classify different Types of Instructions used in Computer Organization with an [14M]
example.
SECTION-III
5 Explain direct and immediate addressing Modes. Differentiate CISC and RISC [14M]
processors
OR
6 Illustrate the micro-programmed control unit(MCU) with a neat diagram and how [14M]
instructions will be processed in MCU?
SECTION-IV
7 Draw a neat block diagram of memory hierarchy in a computer system. Compare [14M]
the parameters size, speed and cost per bit in the hierarchy.
OR
8 Explain the following mapping techniques used for cache mapping [14M]
i) Associative mapping ii)Direct mapping iii) set-associative mapping cache
SECTION-V
9 Write a short notes on Peripheral devices .With a neat sketch explain the working [14M]
principle of DMA
OR
10 Discuss with neat diagrams, How Hazards improved in Pipelining. [14M]
**********

Page 1 of 1
 R20
Code No: R20A0506
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Regular Examinations, February 2022
Computer Organization
(CSE, CSE-AI&ML, CSE-CS, CSE-DS)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 Explain different functional units of a digital computer with neat sketch. Recall the [14M]
usage of Signed number representations
OR
2 Recall the Multiplication algorithms used in Computer Arithmetic. Convert the [14M]
following binary number into decimal & octal number:
i) (00010.110)2 ii) (000.10110)2
SECTION-II
3 List and explain the steps involved in the execution of a complete instruction [14M]
cycle. List the basic symbols used in register transfer Language
OR
4 Classify different Types of Instructions used in Computer Organization with an [14M]
example.
SECTION-III
5 Explain direct and immediate addressing Modes. Differentiate CISC and RISC [14M]
processors
OR
6 Illustrate the micro-programmed control unit(MCU) with a neat diagram and how [14M]
instructions will be processed in MCU?
SECTION-IV
7 Draw a neat block diagram of memory hierarchy in a computer system. Compare [14M]
the parameters size, speed and cost per bit in the hierarchy.
OR
8 Explain the following mapping techniques used for cache mapping [14M]
i) Associative mapping ii)Direct mapping iii) set-associative mapping cache
SECTION-V
9 Write a short notes on Peripheral devices .With a neat sketch explain the working [14M]
principle of DMA
OR
10 Discuss with neat diagrams, How Hazards improved in Pipelining. [14M]
**********

Page 1 of 1
 R18
Code No: R18A0505
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, July/August 2021
Computer Organization
(CSE)
Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions
All Questions carries equal marks.
***
1 a). Explain the bus structure in detail with neat diagram. [7M]

b). What are the functions of ALU. [7M]

2 Differentiate between fixed point and floating point representation. [14M]

3 Explain various types of computer registers with block diagrams. [14M]

4 Explain various instruction formats and write various instruction formats for [14M]
X=(A+B)*(C+D).

a). Explain the different Addressing modes with numerical example. [7M]
5
b). Discuss CISC and RISC processors. [7M]

6 Illustrate the binary division process through a numerical example. [14M]

7 Explain briefly about memory hierarchy. [14M]

8 With the help of a block diagram. Explain DMA transfer in detail. [14M]

**********

Page 1 of 1
 R18
Code No: R18A0505
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Regular/Supplementary Examinations, February 2021
Computer Organization
(CSE)
Roll No

Time: 2 hours 30 min Max. Marks: 70

Answer Any Five Questions
All Questions carries equal marks.
****
1 a). Explain about data representation. [7M]

b). With a neat sketch, explain in detail about the functional units of computers. [7M]

2 What is bus? Draw the figure to show how functional units are interconnected [14M]

using a bus and explain it.

3 What is Instruction Cycle? Briefly explain with state diagram. [14M]

4 What is the difference between a direct and an indirect address instruction? And [14M]

Explain about various addressing modes.

5 Explain clearly three types of CPU organizations. [14M]

6 Draw and explain a flowchart of multiplication algorithm. [14M]

7 Explain the following Auxiliary memory devices: [14M]

i. Magnetic disks

ii. Magnetic tape.

8 Describe in detail about input-output-processor (IOP) organization. [14M]

**********

Page 1 of 1
Code No: R18A0505
R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Regular Examinations, November 2019
Computer Organization
(CSE)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 a) Explain the basic operational concepts of a computer with the help of a suitable [8M]
diagram
b) Explain how the performance of a computer is measured [6M]
OR
2 a) Use 8 bits to represent -9 in Signed magnitude, Signed 1’s Complement, and [6M]
Signed 2’s Complement representations .
b) Define a parity bit. Draw the diagrams of 3-bit odd parity generator and checker [8M]
circuits and explain
SECTION-II
3 a) Draw and explain the construction of bus system using Three State buffers [8M]
b) List all the logic microoperations that are performed on the contents of registers [6M]
OR
4 a) List and explain the purpose of different registers for the basic computer [6M]
b) Explain Interrupt Cycle with the help of a flowchart [8M]
SECTION-III
5 a) Compare the hard wired control unit and micro programmed control unit [8M]
b) Explain about typical Data Transfer Instructions [6M]
OR
6 a) Explain the following addressing modes with an example [6M]
i) Register Indirect Addressing mode ii) Relative Addressing mode
b) Discuss about RISC and CISC Characteristics [8M]
SECTION-IV
7 (a) Differentiate Static and Dynamic RAMs [6M]
(b) Explain Direct mapping technique used for cache mapping [4M]
(c) What is page fault? List various page replacement algorithms [4M]
OR
8 (a) Explain ROM and RAM with respect to their block diagrams [7M]
(b) Explain how read and write operations are performed in Associative memory [7M]
SECTION-V
9 (a) Describe in detail about IOP organization [8M]
(b) Explain the method of DMA transfer. [6M]
OR
10 Define cache memory? Explain various mapping techniques in cache memory. [14M]

**********

Page 1 of 1
 R18
Code No: R18A0505
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, October 2020
Computer Organization
(CSE)
Roll No

Time: 2 hours Max. Marks: 70

Answer Any Four Questions
All Questions carries equal marks.
***
1 a) Draw the diagram of a Single bus structure and explain.

b) Explain about Multiprocessors and Multicomputer.

2 a) Draw the circuit diagram of 4-bit adder-subtractor circuit and explain its
Operation.
b) Explain division algorithms with suitable example.

3 a) Draw and explain 4 bit binary incrementer circuit.

b) Explain the Hardware implementation for generating basic logic micro
operations.
4 a) Explain Instruction Cycle with the help of a flowchart.
b) List and explain all the register reference instructions.

5 a) Explain the operation of a Micro programmed control unit using a diagram.

b) Explain the following

i) Micro operation ii) Microinstruction iii) Micro program.

6 a) Draw the block diagram of an 8-bit ALU with a 4-bit status register and
explain the purpose of each bit in the status register.
b) Explain about typical Data Manipulation Instructions.

7 (a) Define Hit Ratio.

(b) Explain Write-through and Write-back methods of cache updation.
(c) Implement FIFO algorithm for the following page trace with the frame size 4.
0 1 3 6 2 4 5 2 5 0 3 1 2 5 4 1 0.

8 (a) What is meant by instruction pipeline? Explain four segment Instruction

Pipeline. Give its timing diagram.
(b) Discuss briefly the protocols of universal serial bus.
**********

Page 1 of 1
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, October 2020
Computer Organization
(CSE & IT)
Roll No

Time: 2 hours Max. Marks: 70

Answer Any Four Questions
All Questions carries equal marks.
***
1 a) Represent the following decimal values as signed 7 bit number using sign
magnitude, signed 1’s complement and signed 2’s complement formats:
i)+43 ii) -10 iii)51 iv)-27
b) Explain the different registers that are available in the processor of a
digital computer and the connection between the processor and the
memory.
2 a) What are the basic functional units present in the computer and explain
each of them?
b) Design a 4 bit Arithmetic Circuit which can perform addition,
subtraction, increment and decrement operations.
3 a) Draw the flow chart for interrupt cycle and write in brief about modified
fetch phase.
b) Define the following:
i. Microoperation
ii. Microinstruction
iii. Microprogram
iv. Microcode
4 a) What is instruction cycle? Explain various steps involved in the
instruction cycle.
b) Write the circuit of Microprogram sequencer for control memory, explain
in brief.
5 a) Explain the Stack Organization with example.
b) With a neat diagram explain floating point addition/subtraction unit.
6 a) Discuss the differences between RISC and CISC.
b) Write Booth multiplier recoding table. Perform booth multiplication on
the following numbers -13(multiplicand), +11 (multiplier).
7 a) Draw the block diagram of a DMA controller and explain its functioning.
b) List the applications of Vector processing. Write in brief about vector
operations.
8 a) List and explain different types of cache memory mapping techniques.
b) How address mapped using pages in virtual memory? Explain.
**********
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, July/August 2021
Computer Organization
(CSE & IT)
Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions
All Questions carries equal marks.
***
1 a) What is the purpose of addressing modes? Explain various addressing mode [7M]
techniques.
b) Design and explain 4-bit adder-subtractor and 4-bit arithmetic circuit to perform [7M]
addition and subtraction using full adders.

2 a) a) Explain the complete design of simple system to implement RTL code using [7M]
direct connections, bus and tri-state buffers.
b) Design the bus system for 4 registers and explain the working of it? [7M]

3 a) Explain the organizations of micro programmed control unit with neat sketch. [7M]
b) What is address sequencing? Explain the conditional branching and mapping of [7M]
instruction in it.

4 a) Explain micro sequencer organization with a neat sketch. [7M]

b) Discuss the following:
Computer configuration for micro program, Symbolic micro program and [7M]
binary micro program.

5 a) What are the different data transfer and data manipulation instructions and [7M]
explain with example.
b) Design 4 bit Adder and Subtractor circuit and explain its operations. [7M]

6 a) Write the Division algorithm and explain with an example. [7M]

b) Differentiate CISC and RISC microprocessors? Explain the architecture of [7M]
CISC and RISC microprocessors

7 a) Explain instruction execution in a 4 stage pipeline with flowchart. [7M]

b) What are the different major hazards in pipelined execution [7M]

8 a) Draw a neat block diagram of memory hierarchy in a computer system. [7M]

Compare the parameters size, speed and cost per bit in the hierarchy.
b) Explain ROM and RAM with respect to their block diagrams [7M]

**********

Page 1 of 1
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, Dec-21/Jan-22
Computer Organization
(CSE & IT)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 Describe the functional blocks of a computer. Explain the RTL interpretation of [14M]
instructions.
OR
2 Illustrate the various addressing modes of the CPU. Brief on fixed and floating [14M]
point representation of relevant data.
SECTION-II
3 Describe the phases in Instruction cycle. [14M]
OR
4 Illustrate with a neat architecture about design of control unit [14M]
SECTION-III
5 Explain in detail about CISC and RISC machines [14M]
OR
6 Demonstrate with example the working of shift & add and booths multiplier. [14M]
SECTION-IV
7 Briefly describe the modes of data transfer in detail. [14M]
OR
8 List various parallel processing challenges. Draw the block diagram of 5 stage [14M]
pipeline system.
SECTION-V
9 Explain briefly about Associate-mapped and set-associate mapped cache memory [14M]
OR
10 Describe about the segmented page mapping and page replacement in detail [14M]
**********

Page 1 of 1
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, February 2021
Computer Organization
(CSE & IT)
Roll No

Time: 2 hours 30 min Max. Marks: 70

Answer Any Five Questions
All Questions carries equal marks.
***
1 a) Explain various number systems and number representations used in system. [7M]
[7M]
b) Dividend A=01110 Divisor B=10001. Explain flowchart for divide operation.
2 a) Convert the (256)10 into following codes [7M]
[7M]
i) Binary Coded Decimal (BCD) ii) Excess 3 codes
iii) Gray code iv) Reflected Code
b) Explain addition and subtraction algorithms for data represented in signed
magnitude and signed 2’s compliment.
3 a) What are the different phases a basic computer instruction cycle consists? Explain [7M]
[7M]
instruction cycle with flowchart.
b) a) Explain the design of control unit. How to decode the micro operation fields? Explain
the process.
4 a) Write the format of the micro instruction and micro operations for the control memory. [7M]
[7M]
b) With neat sketch explain the design of control unit of basic computer.
5 a) What are the different types of addressing modes and explain with examples [7M]
[7M]
b) Write the multiplication algorithm and explain with an example
6 a) Draw the circuit for 4-Bit BCD Adder and explain its operations. [7M]
[7M]
b) Explain the STACK Organization
7 a) Differentiate parallel processing and pipeline processing and explain them. [7M]
[7M]
b) Explain arithmetic pipeline with example
8 a) What is virtual memory? With the help of neat sketch explain the method of [7M]
[7M]
virtual to physical address translation.
b) Explain the READ and WRITE operations in Associative Memory
**********

Page 1 of 1
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, May 2019
Computer Organization
(CSE & IT)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
*****
SECTION-I
1(a) Explain in brief the evolution of computer generations. [7M]
(b) Differentiate between: (i) Input unit and Output unit (ii) Third generation & [7M]
Fourth generation computers
OR
2(a) Explain the various input output modes of data transfer. [7M]
(b) Define micro operation? Explain arithmetic micro operations. [7M]
SECTION-II
3(a) Explain about the address sequencing in control memory. Draw the diagram to [7M]
show selection of address that is to be loaded into the Control address register.
(b) Describe briefly about the register organization for floating point operations. [7M]
OR
4(a) Differentiate between Hard-wired controlled and Microprogrammed controlled [7M]
microinstructions.
(b) Explain how to construct a common bus for four registers of n bits each using [7M]
three state buffers.
SECTION-III
5(a) Explain Booth’s multiplication algorithm with an example. [7M]
(b) Explain the following addressing modes with examples: [7M]
(i) Immediate mode (ii) Relative mode (iii) Auto increment
OR
6(a) Discuss the Arithmetic operations on floating point numbers. [7M]
(b) With the help of suitable diagram, explain a circuit that can be used to perform either [7M]
addition or subtraction of binary numbers.
SECTION-IV
7 Write in detail about modes of I/O transfer. [14M]
OR
8 Explain in detail about Asynchronous data transfer. [14M]
SECTION-V
9(a) Consider a memory consisting of 64K words of 8 bits each. Give the organization [7M]
to implement this memory using 16K X 1 static memory chips.
(b) Construct an associative memory page table with number of words equal to the [7M]
number of blocks in the main memory.
OR
10(a) Write a short note on virtual memory. [7M]
(b) Write short notes on a)magnetic Disks B) Magnetic tapes, [7M]
**********

Page 1 of 1
 R17
Code No: R17A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester Supplementary Examinations, November 2019
Computer Organization
(CSE & IT)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 a) What are the different performance measures used to represent a computer [7M]
system performance?
b) Discuss about Error Detection codes. [7M]
OR
2 a) Explain Arithmetic, logic and shift micro-operations with examples. [10M]
b) Describe single bus organization of a computer system. [4M]
SECTION-II
3 a) Explain role of different computer registers with respect to instruction [7M]
Fetch cycle and execution. Give example.
b) With the diagram explain the basic organization of micro programmed [7M]
control unit.
OR
4 a) List the basic computer registers with their bit size, register name and [7M]
functionality.
b) Write the differences between Hardwired Control and micro programmed [7M]
control.
SECTION-III
5 a) Explain basic instruction types. Give an example for each type. [7M]
b) Explain addition and subtraction algorithm in computer arithmetic [7M]
OR
6 a) What is Addressing mode? Explain following addressing modes: [7M]
i) Direct addressing mode
ii) Indexed addressing mode
iii) Auto increment addressing mode
iv) Auto decrement addressing mode
v) Indirect addressing mode
b) Explain stack organization with block diagram. [7M]
SECTION-IV
7 a) Describe the different modes of transfer. [7M]
b) What are the different stages of Instruction pipeline? Explain. [7M]
OR
8 a) Differentiate the Asynchronous and synchronous data transfers. [7M]
b) What are the conflicts raised in pipelining? Suggest solutions to overcome [7M]
these conflicts.
Page 1 of 2
 SECTION-V
9 a) What is cache memory? State different mapping techniques in detail [10M]
b) What is page fault? What does page fault signifies when occurred. Explain [4M]
page replacement algorithms.
OR
10 a) Explain the memory hierarchy with a neat diagram. [7M]
b) Define hit rate and miss penalty. Calculate the total access time if miss rate [7M]
is 0.12 miss penalty is 0.015ms and cache access time is 10microseconds.
**********

Page 2 of 2
Code No: R15A0510
R15
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech II Semester Supplementary Examinations, December 2019
Computer Organization
(CSE)
Roll No

Time: 3 hours Max. Marks: 75

Note: This question paper contains two parts A and B
Part A is compulsory which carriers 25 marks and Answer all questions.
Part B Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE Questions,
Choosing ONE Question from each SECTION and each Question carries 10 marks.
***
PART-A (25 Marks)
1). a Define a Parity bit. [2M]
b Define a microoperation. Give examples [3M]
c What are the different phases in an instruction cycle [2M]
d What are the advantages and disadvantages of Hardwired Control Unit [3M]
e Define cache memory. [2M]
f Define an interrupt. What are the different types of interrupts [3M]
g Define a Peripheral. Give Examples [2M]
h What are the different conflicts in instruction pipelining [3M]
i Define locality of reference [2M]
j Draw the memory hierarchy diagram [3M]
PART-B (50 MARKS)
SECTION-I
2 (a) What are the different functional units of a computer and explain [6M]
(b) Differentiate between multi processors and multi computers. [4M]
OR
3 (a) List at least 8 logic microoperations [4M]
(b) Draw the circuit diagram of 4-bit adder-subtractor circuit and explain its [6M]
operation
SECTION-II
4 (a) List the various types of registers used in a basic computer and explain [4M]
(b) Explain the different instruction formats of a basic computer [6M]
OR
5 (a) What are the address sequencing capabilities in a control memory [4M]
(b) Draw the Microinstruction format and explain each field [6M]
SECTION-III
6 Define effective address? And Explain various addressing modes in detail [10M]
with numerical examples.
OR
7 (a) Write the three address instruction formats to evaluate X=(A+B)*(C+D) [4M]
(b) Explain the Stack organization in a system [6M]
Page 1 of 2
 SECTION-IV
8 (a) What is the need of I/O interface module. Differentiate isolated IO and [5M]
memory mapped I/O?
(b) Explain the concept of asynchronous data transfer. [5M]
OR
9 What is meant by instruction pipeline? Explain four segment Instruction Pipeline. [10M]
Give its timing diagram
SECTION-V
10 (a) Write short note on Magnetic Disks [3M]
(b) What is virtual memory? With the help of neat sketch explain the method [7M]
of virtual to physical address translation.
OR
11 (a) Explain how read and write operations are performed in Associative [5M]
memory
(b) Explain Direct mapping technique used for cache mapping [5M]
******

Page 2 of 2
 R15
Code No: R15A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech II Semester Supplementary Examinations, February 2021
Computer Organization
(CSE)
Roll No

Time: 2 hours 30 min Max. Marks: 75

Answer Any Five Questions
All Questions carries equal marks.
***
1 Evaluate the following arithmetic statement using zero, one, two and three address [15M]
instructions. Use the conventional symbols and instructions.
X = (A+B) * (C+D).
2 Draw a flowchart for adding and subtracting two fixed point binary numbers where [15M]
Negative numbers are signed 1’s complement presentation.
3 With a neat Block Diagram explain about Input – Output and Interrupts [15M]
4 Differentiate between hardwired control and micro programmed control. [15M]
Is it possible to have a hardwired control associated with a control memory,
Justify your answer
5 a) Illustrate the different types of addressing modes with examples. [7M]
[8M]
b) Represent the following conditional control statement by two register transfer
statements with control functions: If(P=1) then(R1←R2) else if (Q=1) then
(R1←R3).
6 Show the step-by-step multiplication process using Booth algorithm [15M]
when the following binary numbers are multiplied.
(+33) × (-12).
7 Reproduce instruction pipeline with clear examples. [15M]
8 Compare interrupt driven data transfer scheme and DMA. Using block diagram [15M]
explain interrupt driven transfer scheme.
******

Page 1 of 1
 R15
Code No: R15A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech II Semester Supplementary Examinations, June 2022
Computer Organization
(CSE)
Roll No

Time: 3 hours Max. Marks: 75

Answer Any Five Questions
All Questions carries equal marks
***
1 List and explain the functional units of a computer. [15M]

2 List the registers for the basic computer and give their functionality in program [15M]
execution.

3 Write a detailed note on instruction cycle. [15M]

4 Describe the micro programmed control organization and compare its advantages [15M]
over hardwired control.

5 Explain Computer Arithmetic in detail. [15M]

6 Compare and Contrast CISC and RISC. [15M]

7 Analyze the parallel processing architecture and its uses. [15M]

8 Explain cache memory and cache coherence? [15M]

******

Page 1 of 1
 R15
Code No: R15A0510
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II B.Tech I Semester supplementary Examinations, May 2019
Computer Organization
(IT)
Roll No

Time: 3 hours Max. Marks: 75

Note: This question paper contains two parts A and B
Part A is compulsory which carriers 25 marks and Answer all questions.
Part B Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE Questions,
Choosing ONE Question from each SECTION and each Question carries 10 marks.
****
PART-A (25 Marks)
1). a What is 2’s compliment ? give examples. [2M]
b What is Register Transfer ? give example. [3M]
c What is Instruction cycle. [2M]
d Explain the different timing diagrams associated with buses. [3M]
e Write the advantages of RISC over CISC. [2M]
f What is Addressing mode ? List any 4 addressing modes. [3M]
g What is meant by pipelining and the advantage of pipelining. [2M]
h What are the functions of typical I/O interface. [3M]
i What is the function of TLB. [2M]
j Why does DMA have priority over the CPU when both requests a memory [3M]
transfer.
PART-B (50 MARKS)
SECTION-I
2 a) What are the design goals of Computer Architecture. [5M]
b) Explain about Floating-point representation. [5M]
OR
3 Distinguish between error detection and error correction. Explain with an example [10M]
how Hamming code is used for error detection.
SECTION-II
4 a) Show how a 9-bit micro operation field instruction can be divided into [5M]
subfield to specify 46 micro-operation. How many micro-operations can be
specified in one micro instruction.
b) What is control field encoding ? Explain the role and advantages of micro [5M]
programming.
OR
5 a) Give the micro operations needed to execute the instruction LDA. [5M]
b) Write about Hardwired control [5M]
SECTION-III
6 Explain in detail the principle of carry-look-ahead adder, Show how 16-bit CLA’s [10M]
can be constructed from 4-bit adders.

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 OR
7 a) Distinguish between circular shift and arithmetic shift with example [5M]
b) Explain the three basic types of Data manipulation instructions [5M]

SECTION-IV
8 a) Explain the daisy chain mechanism of data transfer. [5M]
b) Explain briefly the purpose of an IO processor in data transfer between a [5M]
peripheral device and CPU
OR
9 a) Explain pipeline chaining and vector loops in a vector processor. [5M]
b) Describe the implementation of multiply instruction use narrative and [5M]
flowchart.
SECTION-V
10 a) Describe the concept of cache memory and explain the methods of writing [5M]
into cache.
b) Explain the Memory Hierarchy. [5M]
OR
11 A Digital computer has a memory unit of 64 K x 16 and a cache memory of 1 K [10M]
words. The cache uses direct mapping with a block size of four words. How many
bits are there in the tag, index, block an word fields of the address format? How
many blocks can the cache accommodate ?
******

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