6 CMOS Static Logic
6 CMOS Static Logic
A•B
A
A+B
A B
Dual PUN and PDN
A B F
0 0 1
A B
0 1 1
1 0 1
A•B
1 1 0
A
A
B
CMOS NOR
A B F
B
0 0 1
A 0 1 0
1 0 0
A+B
1 1 0
A B
A
B
Complex CMOS Gate
B
A
C
D
OUT = !(D + A • (B + C))
A
D
B C
Standard Cell Layout Methodology
Routing
channel
VDD
signals
GND
X PUN
A
j C
B C
X i VDD
X = !(C • (A + B))
C
i B j A
A B
PDN
A GND
B
C
Two Stick Layouts of !(C· (A + B))
A C B A B C
VDD VDD
X X
GND GND
X i VDD
B j A
GND A B C
For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
Logic Graph: Example 2
X PUN
A C
B D D C
X VDD
X = !((A+B)•(C+D))
C D
B A
A B PDN
A GND
B
C
D
Sticks Diagram
A B D C
VDD
GND
A A
A⊕B A⊕B
B B
A ⊕ B = A•!B+!A•B
A A
B B
A⊕B A⊕B
A ⊕ B = A•B+!A•!B
How many transistors in each?
Can you create the stick transistor
layout for the lower left circuit?
Static CMOS Full Adder Circuit
!Cout = !Cin & (!A | !B) | (!A & !B) !Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)
B
A B B A B Cin
A
A Cin
!Cout !Sum
Cin
A Cin
A
A B B A B Cin
B
Cout = Cin & (A | B) | (A & B) Sum = !Cout & (A | B | Cin) | (A & B & Cin)