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CPU Organization in Computer Architecture for BCA course

BACHELOR OF COMPUTER APPLICATIONS (Guru Gobind Singh Indraprastha

University)

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CPU Organization
1.Introduction

The CPU is made up of 3 major parts:

1. Register set
2.Control unit (CU)
3. Arithmetic and logic unit(ALU)
Register set stores intermediate values used during the execution of the program.
ALU executes the microperations. CU generates the control signal related to
micro operation. CU controls the transfer of information among the registers
and selects which operation to be performed by ALU.

Computer Architecture can be defined as computer structure and behaviour as

seen by the programmer that uses machine language instructions. This includes
instruction formats, addressing modes, instruction set and the general
organization of CPU registers.

The design of CPU involves choosing hardware for implementing the machine
instructions. Assembly language Programmer must be aware of the register set,
memory structure, the type of data supported by the instructions, and the
function that each instruction performs.

Q) Explain about General Register Organization (OR) What is microprogrammed

control?
Intermediate values like pointers, counters, return addresses, temporary results
and partial products during multiplication are stored in registers rather than in
main memory. Accessing intermediate values is faster when they are kept in
registers. The registers communicate with each other for direct data transfers,
while performing microoperations. Hence it is most efficient if we connect them
through a common bus system. A bus organization of seven CPU registers is as
shown below

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The above diagram consists of 7 registers which are connected to 2 multiplexers (MUX)
to form Bus A and Bus B. The select lines (SELA and SELB ) are used to select the
registers to input data to ALU through Bus A and Bus B.

The ALU performs arithmetic and logical microoperations and generates output. One
copy of the output is stored in the register .

The combined value of SELA( 3bits), SELB( 3bits), SELD( 3bits), OPR (5 bits) (i.e,
3+3+3+5= 14 bits ) is called control word.SELA and SELB selects input registers,
SELD selects the output register.

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Example of micro operation

The following statements demonstrate the sequence of steps that are used to perform
microoperation.
For Example to perform the operation R1 ¬ R2 + R3 , the sequence of steps will be
1MUX A selector (SELA): Here BUS A ¬R2
●
2MUX B selector (SELB): Here BUS B ¬R3

3ALU operation selector (OPR): Here 00010 is fed through OPR to perform addition
by ALU.

4 Decoder destination selector (SELD): Selects the register that must store the output.
This is decided by the SELD input given to 3x8 decoder .Here Output generated after
the execution of micro operation is loaded into R1 .

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Microoperation Symbolic Designation Control Word

SEL SELB SELD OPR

A
R1← R2 - R3 R2 R3 R1 SUB 01 011 001 00101
0

R6 ← R6 + 1 R6 — R6 INCA 110 000 110 00001

R7 ← R1 R1 — R7 TSFA 00 000 111 00000

1

A memory unit that stores control word is known as control memory. By reading
consecutive control words, we can generate desired sequence of micro operations. This
type of generating control words is known as Micro programmed control.

Q)Explain about stack organization ? (or) What is stack and how stacks are organized
in system architecture.
Ans:

Stack: set of memory location in which data values are accessed using Last In First
Out Technique (LIFO) is called Stack. Stacks are
1.Very useful feature for nested subroutines, nested interrupt services.
2.Also efficient for arithmetic expression evaluation
3.Stack Pointer (SP) register holds the address of memory location containing top most
data item.
4.Only PUSH and POP operations are applicable

Stacks can exist as a standalone unit (Register Stack) or can be implemented as

part of main memory (Memory Stack)

i) Register Stack organization: Stack can be organized as a collection of finite number

of memory words or registers. Below figure shows the organization of a 64-word

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register stack.

A. Conclusion

Here DR is a data register used to store the data popped from top of stack. DR register
also holds the data to be pushed onto the stack.
Stack Pointer (SP) register holds the address of memory location containing top most
data item.
FULL and EMPTY are one bit registers or Flags. FULL is set to 1 when the stack is
full and EMPTY is set to 1 when the stack is empty. The first item stored in the stack
is at address 1. The last item is stored at address 0. If SP reaches 0, the stack is full, so
FULL is set to 1

In 64-word stack, the SP contains 6 bits because 2 = 64 .The first item stored in the
6

stack is at address 1. The last item is stored at address 0. When SP=63 and SP← �� +
1 , the result is 0 as 111111+1=1000000 in binary. But SP =0 as SP can hold 6 least
significant bits(LSB). Also when SP=0 and �� ← �� − 1 then 000000-1=111111
therefore, SP=63.

ii) Memory Stack Organization

A portion of main memory is used as stack and processor register as SP. Below figure
shows portion of main memory divided into 3 segments -program, data and stack

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segments. The initial value of SP is 4001 and the stack grows with decreasing

addresses.
Thus the first item stored in the stack
is at address 4000, the second item is
stored at address 3999, and the last
address that can be used for the
stack is 3000.

A new item is inserted with push operation as follows

-PUSH operation:
SP ←SP - 1
M[SP] ←DR
An data item is deleted using
pop operations as follows
POP operation:
DR ← M[SP]
SP← SP + 1

Most computers do not provide hardware to check stack overflow (full stack) or
underflow (empty stack). Limit checking must be done in software using 2 processor
registers. One register to hold upper limit (i.e, 3000 in this case) and another to hold
lower limit.
Stack Organization is good for evaluating arithmetic expressions. Common
arithmetic expressions are written in infix notation.

Evaluation of Arithmetic Expressions: Any arithmetic expression can be expressed in

parenthesis-free Polish notation. The reverse Polish notation is very suitable for stack.
In reverse polish notation operands are declared first and then the operators.

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Multiplication and division are performed before addition and subtraction. The
following diagram represents evaluation of arithmetic expression using stack.

The above expression is evaluated from left to right. The operands are pushed onto the
stack and the arithmetic operations are performed on the top 2 elements of the stack,
the result is again pushed back onto stack.
Ans: Consider the expression (A + B) * [C * (D + E) + F]
 we must first perform the arithmetic inside the parentheses (A + B) and (D + E).
So, AB+DE+
 Next we must calculate the expression inside the square brackets.
 The multiplication of C * (D + E) must be done prior to the addition of F since
multiplication has precedence over addition. So, AB+DE+C*F+
 The last operation is the multiplication of the two terms between the parentheses
and brackets
 The converted expression is A B + D E + C * F + *
 The expression can be converted to reverse Polish notation, without the use of
parentheses, by taking into consideration the operation hierarchy.
Q)What are the common fields found in an instruction?

Ans: The bits of the instruction are divided into groups called fields. The most common
fields found in instruction formats are:
1.operation code field (op-code field) that specifies the operation to be performed.
2.An address field that has a memory address or a processor register depending on
mode field.
3.A addressing mode field that specifies determines how the address field is to be
interpreted (to get effective address or the operand)
Q)Explain about the most common processor organizations. (or) What are 1-address ,
2- address, 3- address and zero-address instructions. (or) Explain about various types of
instruction formats.
Ans:
Most common fields in instruction are op-code field, address field and addressing
mode field. The number of address fields in the instruction format depends on the
internal organization of CPU. Most computers fall into one of the 3 types of CPU
organizations. They are
1.Single register (Accumulator) organization
2.General register organization

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3.Stack organization
1.Single register (Accumulator) organization: Accumulator is the only general purpose
register.
Example : ADD X /* AC <-- AC + M[X] */ One address instruction
here AC is the accumulator and M[X] is the memory word located at address X.
Since the instruction has one address field, ADD X is a one –address instruction
2. General register organization employs two or three address fields in their instruction
format. Each address field may specify a processor register or a memory word. Any of
the registers can be used as the source or destination for computer operations.
ADD R1, R2, R3 /* R1 ← R2 + R3 */
ADD R1, R2, R3 is three address instructions as it has 3 register address fields R1,R2
and R3. First address field R1 is the destination and remaining address fields(R2 and
R3) are sources.
Q) Convert the expression from infix to postfix or reverse polish notation

Ans: Consider the expression (A + B) * [C * (D + E) + F]

 we must first perform the arithmetic inside the parentheses (A + B) and (D

+ E). So, AB+DE+

 Next we must calculate the expression inside the square brackets.

 The multiplication of C * (D + E) must be done prior to the addition of F

since multiplication has precedence over addition. So,AB+DE+C*F+
 The last operation is the multiplication of the two terms between the
parentheses and brackets
 The converted expression is AB+ DE+ C*F+ *
 The expression can be converted to reverse Polish notation, without the
use of parentheses, by taking into consideration the operation hierarchy.
Q) What are the common fields found in aninstruction?
Ans: The bits of the instruction are divided into groups called fields. The most common
fields found in instruction formats are:
1. operation code field (op-code field) that specifies the operation to be
performed.
2. An address field that has a memory address or a processor register
depending on modefield.
3. A addressing mode field that specifies determines how the address field is
to be interpreted (to get effective address or the operand)
Q)Explain about the most common processor organizations. (or) What are 1-address
, 2- address, 3address and zero-address instructions? (or) Explain about various
types of instruction formats.
Ans: Most common fields in instruction are op-code field, address field and
addressing mode field. The number of address fields in the instruction format

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depends on the internal organization of the CPU. Most computers fall into one of
the 3 types of CPU organizations. They are
1. Single register (Accumulator) organization
2. General register organization
3. Stack organization

1. Single register (Accumulator) organization: Accumulator is the only general

purpose register.

Example : ADD X /* AC AC + M[X] */ One addressinstruction

here AC is the accumulator and M[X] is the memory word located at address X.
Since the instruction has one address field, ADD X is a one –address instruction

2. General register organization employs two or three address fields in their

instruction format. Each address field may specify a processor register or a
memory word. Any of the registers can be used as the source or destination for
computer operations.

ADD R1, R2, R3 /* R1 R2 + R3 */

ADD R1, R2, R3 is three address instruction as it has 3 register address fields R1,R2
and R3. First address field R1 is destination and remaining address fields(R2 and R3)
are sources.

ADD R1, R2 /* R1 R1 + R2 */

MOV R1, R2 /* R1 R2 */

ADD R1,X /* R1 R1 + M[X] */

the above 3 instructions are 2 address instructions as they have 2 addressfields.
3. Stack organization: All operations are done using the hardware stack. have
PUSH and POP instruction which require an address field. Thus the
instruction

PUSH X /* TOS M[X] */

will push the word at address X to the top of the stack. The stack pointer is
updated automatically

The instruction ADD

in stack consists of an operation code only with no address field. Hence ADD is a
zero address instruction. This operation will pop the top 2 data items from the
stack, adds them and pushes the sum into the stack

Q) Write a program to execute X = (A + B) * (C + D) using zero, one, two, three

address instructions Ans:
• Three-Address Instructions

ADD R1, A, B R1 ← M[A] + M[B]

ADD R2, C, D R2 ← M[C] + M[D]

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MUL X, R1, M[X] ← R1 * R2

R2
The advantage of the three-address format is that it results in short programs
The disadvantage is that the binary-coded instructions require too many bits to specify
three addresses
·Two-Address Instructions

MO R1, A R1 ← M[A]
V
ADD R1, B R1 ← R1+M[B]

MO R2, C R2← M[C]

V
ADD R2, D R2 ← R2 + M[D]

MUL R1, R2 R1 ← R1 * R2

MO X, R1 M[X]<-- R1
V
The first symbol listed in an instruction is assumed to be both a source and the
destination where the result of the operation is transferred
·One- Address Instructions

LOAD A AC ← M[A]

ADD B AC← AC + M[B]

STORE T M[T] ← AC

LOAD C AC← M[C]

ADD D AC ← AC + M[D]

MUL T AC← AC * M[T]

STORE X M[X] ← AC

T is the address of a temporary memory location required for storing the

intermediate result
Zero Address instruction

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PUSH A TOS ← A

PUSH B TOS← B

ADD TOS ← (A + B)

PUSH C TOS ← C

PUSH D TOS← D

ADD TOS ← (C + D)

MUL TOS ← (C + D) * (A + B)

POP X M[X] ← TOS

Q)Explain the different Addressing modes with an example

Ans: Addressing modes are used to find the mode of accessing address of
operand for processing the instruction. The most common addressing modes
are:
1.Implied Addressing mode.
2.Immediate Addressing Mode.
3.Register Addressing Mode
4.Register Indirect Addressing Mode
5.Auto-increment or Auto-decrement Addressing
6.Direct Addressing Mode
7.Indirect Addressing Mode
8.Relative Addressing Mode
9.Indexed Addressing Mode
10.Base Register Addressing Mode
1. Implied addressing Mode:
In this mode the operands are specified implicitly in the definition of the instruction.
For example, CMA "complement accumulator“
The operand is the accumulator register and the contents of accumulator are
complimented and the complimented result is again stored in accumulator.
Zero-address instructions in a stack-organized computer are implied- mode instructions
since the operands
are implied to be on
top of the stack. 2.
Immediate
addressing Mode:
In this mode the operand is specified in the instruction itself.
In other words, an immediate- mode instruction has an operand field rather
than an address field. For example, MVI A, 50 A ←50
This instruction stores the constant value 50 in accumulator register.
3.Register Addressing Mode:

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In this mode the operands are in registers that

reside within the CPU. For example, Add R1,R2
R1← R1 + R2
4.Register Indirect Mode:
In this mode the register contains the address of operand in memory i.e, the instruction
specifies the registers in CPU, this register contains the address of operand.
For example: LDA (R1) AC ← M[R1]
5.Auto increment or Auto Decrement mode:
An example for Auto-decrement, LDA --(R1)
R1 ← R1-1
AC ← M [R1]
6.Direct addressing mode
The operand resides in memory and its address is given directly in the address field of
the instruction.
—For example, LDA 4002 AC ← [4002] here 4002 is the value in address field of
instruction
In this mode the effective address is equal to the address part of the instruction. Here
Effective address is address of operand.
7.Indirect addressing mode:
In this mode the address field of the instruction gives the address where the
effective address is stored in memory.
—For example, LDA @4002 AC ← M[ [4002] ] here 4002 is the value in address
field of instruction
8.Relative Address Mode:
In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address.
—For example, LDA $ 40 AC ←M[PC+40] here 40 is the value in address field of
instruction
9.Indexed Addressing Mode:
In this mode the content of an index register XR is added to the address part of the
instruction to obtain the effective address.
—For example, LDA add(x) AC ← M[XR+address field value]
Index register is a special CPU register that cont+ains an index value which is
automatically incremented after its contents are accessed. The address field of
instruction defines the beginning address of array in memory.
10.Base Register Addressing Mode:
In this mode the content of a base register is added to the address part of the instruction
to obtain the effective address. This is similar to the indexed addressing mode except
that the register is now called a base register whose values are not automatically
incremented.

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