Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail-
[email protected], Website- www.vitm.edu.in
EXPERIMENT No. 8
AIM: -To verify the characteristic table of RS and JK Flip flops .
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. NOR gate IC 7402
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411
5. NAND gate IC 7400
6. Connecting wires As required
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its output states
only at times determined by clocking signal. Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is
reset when the R input high and S input is low. The Flip Flop is set when the S input is high
and R input is low. When both the inputs are high the output is in an indeterminate state.
JK FLIP FLOP:
Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- [email protected], Website- www.vitm.edu.in
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave
like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and
the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values. When the clock pulse is high, the J and K inputs reach the NOR gates.
When both the inputs are high the output toggles continuously. This is called Race around
condition and this must be avoided.
RS FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- [email protected], Website- www.vitm.edu.in
CHARACTERISTIC TABLE:
CLOCK INPUT PRESENT NEXT STATUS
PULSE S R STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 X
8 1 1 1 X
JK FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- [email protected], Website- www.vitm.edu.in
CHARACTERISTIC TABLE:
CLOCK INPUT PRESENT NEXT STATUS
PULSE J K STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 0
PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.
RESULT:
