Design Using System Verilog

Design of Combinational and Sequential Circuits:

Dr. Sujit K. Patel

Assistant Professor, DECE|TIET

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 Unit-2
• HDL modelling of combinational and sequential circuits: multiplexer, decoder, adder,
flip flops and registers, simple design examples, testbench for combinational and
sequential circuits. Mealy and Moore FSMs, Design Examples.

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 System Verilog Modeling Styles
• Modeling styles are
1. Data flow level

2. Gate level

3. Behavioral level

4. Mixed modeling

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 Modeling Styles: Examples
• Dataflow level modelling of mux:
module mux_2to1 (i0,i1,sel,y);

input logic i0,i1,sel;

output logic y;

assign y = (sel) ? i1 : i0;

// assign y= ((~sel)&i0) | (sel & i1);

endmodule
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 Modeling Styles: Examples
• Gate level modeling: module mux_2to1_Gate_Level (i0,i1,sel,y);
input logic i0,i1,sel;
output logic y;
logic y1,y2;
not n1(sel_n, sel);
and and_1(y1, i0,sel_n);
and and_2(y2,i1,sel);
or or_1(y,y1,y2);
endmodule

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 Modeling Styles: Examples
• Behavioral modelling: module mux_2to1_Beh (i0,i1,sel,y);
input logic i0,i1,sel;
output logic y;
always@(*) begin
if (sel==0)
y<=i0;
else
y<=i1;
end
endmodule
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Testbench for 2-to-1 MUX

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• Non-synthesizable code for 2-input NAND gate

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Switch level modelling of 2-input NAND gate

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Testbench for 2-Input NAND gate

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Power of System Verilog

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Dangers of Verilog: Incomplete Specification

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Incomplete Specification Infers Latches

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Avoiding Incomplete Specification

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The Sequential always Block

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Importance of the Sensitivity List

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Importance of the Sensitivity List

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Simulation

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Blocking vs. Nonblocking Assignments

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Blocking vs. Nonblocking Assignments

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x

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Assignment Styles for Sequential Logic

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Use Nonblocking for Sequential Logic

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Simulation

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Use Blocking for Combinational Logic

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Use Blocking for Combinational Logic

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Dangers of Verilog : Priority Logic

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Resulting Priority Logic

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Avoiding (Unintended) Priority Logic

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Useful Boolean Operators

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31
D-FF with synchronous enable and asynchronous reset
Reset
Input D Q Output
Clk

enable

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Testbench for D-FF with synchronous enable

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Simulation

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 Synchronous System Design

• Synchronous Design Methodology

• All storage components are synchronized with global clock
• Input data sampled at positive or negative edge of the clock signal

• Synchronous system consists of three parts

1. State register
2. Next state logic
3. Output logic

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Two-segment coding style for a DFF with enable input

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MUX D Q q
d 1

enable
Clk Asyn_reset

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Simulation

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 Binary up/down counter

clk
Up/Down 4-bit
sync_rst q
Counter
up_down

Present State Output

Next State Outputs
Up_dwon Next State register Present State
Logic
Logic
reset
clk

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Binary up/down counter

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Testbench for up/down counter

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Simulation

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 Universal shift register
clk
si_l
4-bit
si_r USR q
pi_d
Sel

Present State Output

register Logic Outputs
si_l Next State Present State
si_r Next State
Logic
pi_d clk
sel

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Universal Shift Register

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Testbench for Universal Shift Register

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Simulation

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Finite State Machine

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 Some Basic Concepts: FSM

• Any circuit with memory is a finite state machine

• Even computers can be viewed as huge FSMs

• Design of FSMs Involves

• Defining states
• Defining transitions between states

• There are two types of FSMs

• Mealy
• Moore
 Mealy FSM

• Output is a function of a present state and inputs

Inputs Next State

Logic
Next State Present State
clock Present State
reset register

Output Outputs
Logic
 Moore FSM

• Output is a function of a present state only

Inputs Next State

Loigc
Next State Present State
clock Present State
reset register

Output Outputs
Logic
 FSM Code Development
• The procedure of developing code for an FSM is similar to that of a regular
sequential circuit.

• We first separate the state register and then derive the code for the
combinational next-state logic and output logic.

• The main difference is the next-state logic.

• For an FSM, the code for the next-state logic follows the flow of a state diagram.

• We will discuss one example based on the binary sequence detector.

 Example: Sequence Detector
Develop the SV model for Mealy sequence detector which has one-bit input
and one-bit output. This generates logic ‘1’ output whenever it
recognizes sequence “101”.
 Mealy State Diagram for Sequence Detector
Desired binary sequence to be recognized by detector is “101”.
Code for Mealy Sequence Detector
//state register

//module input and outputs

Code for Mealy Sequence Detector
// Next state logic
Code for Mealy Sequence Detector
// Output logic
Testbench Code
Output Waveforms

0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0
 Moore FSM

• Output is a function of a present state only

Inputs Next State

Logic
Next State Present State
clock Present State
reset register

Output Outputs
Logic
 Example: Sequence Detector
Develop the Verilog HDL model for Moore sequence detector which has one-
bit input and one-bit output. This generates logic ‘1’ output whenever it
recognizes sequence “101”.
 Moore State Diagram for Sequence Detector
Desired binary sequence to be recognized by detector is “101”.
Code for Moore Sequence Detector
// State register

// input output ports

Code for Moore Sequence Detector // next state logic
Code for Moore Sequence Detector
Testbench Code Cont’d…
Output Waveforms

0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0
End of Lecture