DESIGN AND IMPLEMENTATION OF POWER

EFFICIENT AND FAST FULL ADDERS USING GDI

AND HYBRID LOGICS

Sanagaram Aravind Kasyap, Sai Vamsi Ch, Saiprateeka S, Sonali Agrawal

Department of Electronics and Communication Engineering,
Amrita School of Engineering, Bengaluru
Amrita Vishwa Vidyapeetham, India

Abstract: Full adder is majorly used as a basic component in various arithmetic

applications in the fields of VLSI and DSP. Any improvement in the performance of the
adder cell will impact the overall performance of the designed circuit. Power consumption
and speed are two vital parameters in evaluating the performance of a given circuit, but
conflicting design aspects. Full adders can be implemented using various logic design
techniques. In this paper, various hybrid full adders are proposed using the conventional
design and an alternative logic structure approach. The performance of the full adder
circuits is evaluated and compared with the existing implementation by performing
extensive simulations using Cadence Virtuoso and LTspice EDA tools in 45nm process
technology. The performance analysis shows that the proposed hybrid full adder is more
optimized in power consumption and delay compared to conventional CMOS and other
hybrid implementations.

Keywords: Full Adder, Gate Diffusion Input (GDI), Logic designs, Power-delay
product (PDP)

1 Introduction

The streamlined working of many large-scale real-world electronic system applications is

mostly based upon the performance of the arithmetic circuits to execute complex
algorithms like integration of digital signals, filtering of signals from noise, etc. The
most widely used circuits, in Very-Large-Scale Integration (VLSI) systems, are
adders and multipliers which are generally chosen to operate at low power with
comparatively less delay. Since the last decade, the demand for mobile and wearable
electronic gadgets has exponentially grew in market which resulted in an increased
amount of focus on low power circuit designs [1] by the semiconductor industries.
With the explosive growth and the rising demand for portable electronic products, the
designers are struggling to design with a criterion of smaller chip area, optimized
speed and battery performance. XOR along with XNOR gates constitute the basic
building blocks in various circuits that are used to realize operations like arithmetic,
compression, comparison, parity checking, code conversion, etc.
Various full adders have been proposed for optimizing design metrics such as power
[2-5], delay [6], and compared [7-9]. Commonly used logic design techniques for
designing full adders are static CMOS, PTL, CPL, DPL, and GDI. The proposed
hybrid full adder circuits are designed using various logic design implementations
pertaining to the requirement of optimizing power consumption or delay. Since these
proposed circuits include the various traits and properties which can increase the
performance of the full adder.
 Full adders are classified into non-full-swing and full-swing circuits based on
their output voltage level i.e. whenever the circuit suffers from degradation in the
output volt- age, then it is a non-full-swing circuit. When the output signal spans
completely from 0 (GND) to 1 (VDD), then it is a full-swing circuit.
In this paper, various standard implementations like static CMOS, PTL, CPL,
DPL, and GDI based full adder circuits and some extant hybrid full adder
implementations are compared. In the proposed circuits, advantages and limitations
for each logic design technique are discussed and compared with respect to voltage
degradation at the output, power consumed by the circuit, delay in the critical path,
and the product of power with delay.
The rest of the paper is classified as follows- Section II explains the literature
survey i.e. standard implementations and previous work done by various researchers.
Section III deals with the hybrid full adders using simultaneous XOR-XNOR gates.
In section IV, four hybrid full adders are proposed based on gate diffusion input
(GDI) and hybrid logic techniques using conventional and alternate internal structure.
In section V, the circuits are simulated for various metrics like power, delay and, PDP
in 45nm process technology with 1.2V supply voltage and compared with the existing
implementations. The paper reaches its conclusion in section VI.

2 Previous Work

The conventional way of designing a full adder is shown in Fig. 1, using XOR, AND
and OR logic gates to obtain the sum and carry outputs.
The basic and simpler way of designing a full-swing full adder is conventional
CMOS or static CMOS logic design technique [10]. Static CMOS works on the
principle of combining pull-up network consisting of only PMOS transistors,
connecting the source (VDD) to the output and pull-down network consisting of only
NMOS transistors, connecting the output to the ground (GND), which acts as dual of
each other to achieve full-swing operation, since PMOS and NMOS produce strong
logic 1 and 0 respectively. This technique required 2*n transistors for n inputs. Static
CMOS technique requires a greater number of transistors to design; hence it
consumes more power and area. The full adder designed using static CMOS is shown
in Fig. 2.
Another common way of designing a full adder is using pass transistor logic fam-
ilies, consisting of PTL, CPL, and DPL. Pass transistor logic (PTL) is generally pre-
ferred for low power implementations, because of using a lesser number of
transistors, but suffers from voltage degradation at the output, hence non-full-swing
output. Only one Pass Transistor Logic (PTL) network i.e. either PMOS or NMOS is
completely enough to produce the output. PTL based circuits are slightly faster
because of smaller node capacitances. SERF based PTL full adder can be designed
with 10 transistors [11] and they do not dissipate short circuit current because of no
direct path from Source (VDD) to Ground(GND) and hence overall consumption of
power is minimized. PTL based SERF full adder is shown in Fig. 3.
Fig. 1. Full adder with conventional design

Fig. 2. Full adder using static CMOS

The threshold voltage drop drawback of the PTL technique can be overcome
by using complementary pass-transistor logic (CPL) and double pass transistor logic
(DPL) [12]. CPL design requires a greater number of transistors compared to PTL
because of the need to complement the input signals. Double pass transistor logic
uses complementary transistors in order to keep it operating at full swing and to
reduce the power consumption and takes away the need of using inverters after each
block in CPL. Full adders using SR-CPL and DPL logic styles are shown in Fig. 4
and Fig. 5 respectively.
Several researchers have proposed alternate logic structures to implement full
adders [12-13] .The alternate logic structure, proposed in [13] using two XOR gates
and one 2X1 MUX is shown in Fig. 6. The full adder can be designed using a lesser
number of transistors. Many implementations of logic gates are also realized using
gate diffusion input (GDI) logic technique [14-15].
 Fig. 3. The 10 transistors PTL based SERF adder

Fig. 4. Full adder based on SR-CPL logic design

Fig. 5. Full adder based on DPL logic design

Fig. 6. Alternate logic structure to implement FA

3 Hybrid Full Adders (HFA) using Simultaneous XOR-XNOR

Various implementations of XOR-XNOR are compared and a simultaneous XOR-

XNOR has been proposed in [16]. Based on this simultaneous XOR-XNOR, six
different hybrid full adders were designed based on switch hybrid logic style and
compared with respect to power, delay, and power-delay product. Simultaneous
XOR-XNOR is shown in Fig. 7.

Fig. 7. Simultaneous XOR-XNOR

The input capacitances are almost equal for both XOR and XNOR circuits, hence
the glitches are reduced in the next stage while passing the XOR and XNOR signals
simultaneously. It has been concluded in [16] that this structure has better driving
capability and sturdiness against supply voltage scaling. The first hybrid full adder
was designed using two XOR gates and two 2X1 MUXs with 20 transistors (HFA-
20T). In HFA-17T, no separate structure is used for the generation of XNOR signal,
but the XOR signal is complemented using a NOT gate in order to reduce the number
of transistors used. Out of all the proposed implementations in [16], HFA-17T has the
lowest power consumption. HFA-17T is shown in Fig. 8.
Fig. 8. HFA-17T

With respect to speed, HFA-22T has the least delay compared to the other
implementations. If the Cin signal is used to bring forth Sum output, then the XOR
and XNOR will be the selection lines of the 2X1 MUX, hence the capacitance of
XOR and XNOR nodes reduces and the delay in time is minimized. HFA-22T is
shown in Fig. 9.

Fig. 9. HFA-22T

In addition to these, full adders were also implemented using buffers at the inputs
and outputs to improve the driving capability.
 4 Proposed Full Adders using GDI and Hybrid Techniques

The first proposed full adder is designed using the conventional method with all
the basic gates XOR, AND and OR realized using full-swing GDI logic design
technique as explained in [17] using 25 transistors. The realization of logic gates
using GDI is shown in Fig. 10. The first proposed full adder based on full-swing GDI
technique is shown in Fig 11.

V
Fig 10. (a) AND (b) OR (c) XOR gates using full-swing GDI technique

The objective behind designing this full adder is to minimize power consumption
and wiring complexity with respect to conventional CMOS implementation without
increasing propagation delay.

Fig. 11. GDI based full adder [Proposed GDI-FA-25T]

 In second full adder, XOR gate is realized using the XOR part of simultaneous
XOR-XNOR proposed in [16] as it was concluded, after performance analysis, that
the power consumption of this XOR part is lower than the XOR designed using full-
swing GDI implementation. The realization of AND and OR gates remains same. The
full adder based on GDI and hybrid logic 1 is shown in Fig. 12.

Fig. 12. Full adder based on GDI and hybrid logic 1 [Proposed GDI-HFA-25T]

Third full adder is based on the switch hybrid logic style and implemented using
two XOR gate and two 2X1 MUXs. In similar approach to HFA-17T of [16], XNOR
signal is generated by complementing XOR signal without using another circuit. 2X1
MUX is implemented using pass transistor logic (PTL) to obtain the ‘Sum’ output and
the 2X1 MUX to obtain the ‘Cout’ is implemented using transmission gate (TG) logic.
Implementation of 2X1 MUX is shown in Fig. 13.

Fig. 13. 2X1 MUX using (a) TG logic (b) PTL

The third hybrid full adder designed using 17 transistors, is shown in Fig. 14.
Fig. 14. Full adder based on hybrid logic 2 [Proposed HFA-17T]

Fourth hybrid full adder is designed using alternative internal logic structure
approach proposed in [13] shown in Fig. 6 using only two XOR gates and one 2X1
MUX. This full adder is designed for applications with utmost requirement for power
minimization or applications working stand-alone instead of in a cascaded system,
where a little bit of threshold voltage drop at the output is acceptable. The idea of
designing XOR gate with a smaller number of transistors for minimal power
consumption in trade-off for a full voltage swing at the output is mentioned in [18].
XOR gate designed using 3T is shown in Fig. 15.

Fig. 15. XOR-3T

In applications, where the full swing at the output is necessary, threshold voltage
drops at the output can be minimized by varying the W/L ratios i.e. by changing the
sizing of PMOS and NMOS transistors. The 2X1 MUX is also designed using the pass
transistor logic similar to the previous hybrid full adder implementation, in order to
reduce the transistor count and to minimize the power consumption. Full adder with
alternate logic structure using power minimal XOR gate and 2X1 MUX is shown in
Fig. 16.

Fig. 16. Full adder based on hybrid logic 3 [Proposed HFA-8T]

5 Performance Analysis

All these various existing and proposed hybrid full adder implementations are simulated using
Cadence Virtuoso in 45nm process technology with 1.2V power supply voltage. Performance
metrics like power, delay and power-delay product (PDP) for various implementations are
shown in Table 1.

Table 1 PERFORMANCE ANALYSIS

Circuit Power (μW) Delay (ns) PDP (e-15J)

HFA-20T 30.35 14.84 450.39

HFA-17T 20.45 15.3 312.88

HFA-22T 34.58 12.8 442.62

Proposed GDI-FA-25T 31.69 15.25 483.27

Proposed GDI-HFA-25T 23.19 14.54 337.18

Proposed HFA-17T 20.26 13.7 277.56

Proposed HFA-8T 17.49 11.91 208.31

In [16], it has been concluded that HFA-17T has the lowest power consumption
among all the six full adders. Table 2 shows the power consumption for all the
proposed circuits with respect to HFA-17T.

Table 2 POWER COMPARISON

Circuit Power (μW) Comparison w.r.t HFA-17T

HFA-20T 30.5 +49.14%

HFA-17T 20.45 -
HFA-22T 34.58 +69.09%
31.69 +54.96%
Proposed GDI-FA-25T

23.19 +13.39%
Proposed GDI-HFA-25T

20.26 -0.92%
Proposed HFA-17T

17.49 -14.47%
Proposed HFA-8T

From Table 2, it is concluded that proposed HFA-8T has 14.47% reduction in power
with respect to HFA-17T. In [16], it has been concluded that HFA-22T has the
lowest critical path delay among all the six full adders. Table 3 shows the delay
comparison for all the proposed circuits with respect to HFA-22T.

Table 3 DELAY COMPARISON

Circuit Delay (ns) Comparison w.r.t HFA-22T

HFA-20T 14.84 +15.93%

HFA-17T 15.3 +19.53%
HFA-22T 12.8 -
Proposed GDI-FA-25T 15.25 +19.14%
14.54 +13.59%
Proposed GDI-HFA-25T

Proposed HFA-17T 13.7 +7.03%

Proposed HFA-8T 11.91 -6.95%

From Table 3, it is concluded that proposed HFA-8T has 6.95% reduction in delay
with respect to HFA-22T. Comparison graphs for power and delay are shown below.
Fig. 17. Power consumption for various full adders

Fig. 18. Delay for various full adders

6 Conclusion

Adder is an important component having a wide range of applications and the importance of an
adder circuit cannot be emphasized enough. Keeping this in mind, a wise decision must be made
while choosing from the extensive range if adder circuit designs. The decision has to be made
based on the requirement. For example, if an adder for low power application is required, then
we select an adder circuit which is able to give adder logic while consuming relatively less
power. If a circuit should be optimized for speed, then an adder circuit with less delay is chosen,
Finally, if the designer wants a full swing perfect ;1’ and ‘0’ output it takes a little more number
of transistors to achieve it and there might be a bit compromise on power and delay. So, the
design choice of a full adder circuit used by a designer is left to the designer’s discretion based
on the total systems requirement.
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