Scribd
Upload
15 views7 pages

Fa 404

Uploaded by

Anusuri Vyshnavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views7 pages

Fa 404

Uploaded by

Anusuri Vyshnavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

DATE:25/09/24

EXPERIMENT – 8
DESIGN OF FULL ADDER
AIM: To design, simulate and verify the operation of Full Adder using Cadence.
TOOLS USED:
1. Virtuoso Tool for Schematic Designs
2. Spectre Tool for Simulation
THEORY:
A NAND gate is a fundamental building block in digital electronics, often referred to
as a "universal gate" because any other logic gate (AND, OR, NOT, etc.) can be
constructed using only NAND gates. The term NAND stands for "NOT AND,"
meaning it performs an AND operation followed by a NOT operation.
Y = A.B
TRUTH TABLE:
INPUT A INPUT B OUTPUT Y

0 0 1

0 1 1

1 0 1

1 1 0

FULL ADDER:
A full adder is a more advanced digital circuit than the half adder, used for adding
binary numbers. It can handle the addition of three input bits: two significant bits (A
and B) and a carry bit (Carry-In) from a previous stage of addition. This makes the
full adder an essential component in multi-bit binary addition operations, such as
those performed in arithmetic logic units (ALUs) and digital processors. The full
adder produces two outputs is Sum – The result of adding the three input bits. SS

228W1A0404
NAND GATE CIRCUIT

FULL ADDER USING NAND :

228W1A0404
Carry-Out – The carry bit that is passed on to the next stage of addition if the sum
exceeds one bit.
Logic
 SUM = A + B + C
 CARRY = AB + BC + CA
TRUTH TABLE:
INPUT A INPUT B INPUT C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

PROCEDURE:

1. Create a new folder and name it.


2. Open the folder and select open in terminal.
3. Give the following commands:
1. csh (enter)
2. source /home/install/cshrc (enter)
3. Virtuoso (enter)
4. In the log window choose file then new and then library.

228W1A0404
SIMULATION RESULTS:

TRANSIENT RESPONSE

DC RESPONSE

228W1A0404
5. Name the library and select technology library file as attached to an
existing technology library.
6. Click on OK.
7. Select gpdk045 and click on OK.
8. Select file and then new and celview
9. Change the library to the library name as created before and give the
cell name and click on OK.
10. In the schematic editor construct the circuit as per the given diagram. \
1. Use I for instantiating the components.
2. Use P for creating the pins.
3. Use W for providing and the connections
4. All transistor-related components are present in gpdk045
5. All the voltage-related components are present in Analog.lib.
6. To create the symbol for the schematic, choose:
7. create -> cellview -> from cellview
8. Click on OK and OK.
9. Remove instance name outerbox and rename the symbol, check and
save.
10. Choose file -> new -> give the cell name -> inverter1_test and click
on OK.
11. Connect the circuit as per the diagram, check and save it.
12.Select launch -> ADEL (1st option).
13. Choose setup -> model libraries and change is to tt.
14. Choose analysis, then choose tran. Give stop time, select moderate,
and click on OK.
15. Choose outputs to be plotted and select on design.
16. Schematic window will be open, choose the required inputs and
outputs signal and click RUN.
17. We get transient analysis.

228W1A0404
228W1A0404
18. Launch ADEL -> setup -> model libraries.
19. Select analysis-> Select dc-> Save DC operating point
20.Component parameters:
21. Select component.
22. Select DC component by clicking on vpulse
23.Set sweep voltage 0V - 1.8V.

RESULT :
Hence the operation of Full Adder has been simulated and verified, transient and dc
analysis are performed on Full Adder using Cadence tool.

228W1A0404

You might also like