FPGA technologies:

There are three FPGA programming technologies. They are:

1. SRAM technology.
2. Anti fuse technology.
3. EPROM/EEPROM technology.
1. SRAM programming technology:
SRAM cells used to store the data that can to configure. FPGA has to be reprogrammed on
power up as it is a volatile memory. It occupies large area. It allows dynamic and partial
reconfiguration.

It most widely used FPGA programming technology. It holds their data in FPGA memory. The
output of the memory cell is directly connected to another circuit and state of the memory cell
continuously controls the circuit being configured. Each combinational logic element requires
many programming bits and each programming interconnection point requires its own bit.
Advantages:
1. SRAM based FPGA can be easily programmed
2. SRAM based FPGA can be reprogrammed during the system operation, providing
dynamically reconfigurable systems.
3. The circuits used in the SRAM based FPGA can be fabricated with standard VLSI
process.
Disadvantages:
1. SRAM configuration memory burns a noticeable amount of power, even when the
program is not changed.
2. The bits in the SRAM are susceptible to theft.
3. SRAM based FPGAs have to be configured every time after power goes up and down.
2. Anti-fuse technology:
1. Anti fuse is a one-time programmable.
2. Fuses are permanently put in place.
3. The anti-part of anti fuse comes from its programming method.
4. Instead of breaking a metal connection by passing through a current through it, a link is
grown to make a connection.
5. Programming is very slow because each anti fuse must be programmed separately.
6. Programming element is an anti fuse (high impedance(open circuit) on low voltage and
low impedance (connection) on high voltage.
7. Small area
8. Non-volatile
9. Irreversible( design errors cannot be corrected)
Advantages:
1. Antifuse technology is nonvolatile. Design remain as it is even the power is down.
2. Delays due to routing are very small.
3. Anti fuse FPGAs tend to require lower power.
4. Theft problem is not there in anti fuse technology.
Disadvantages
1. Anti fuse technology requires a complex fabrication process.
2. External programmer is required to program or configure the design, after which the
design cannot be changed.
3. EPROM/EEPROM technology
1. Switch is disabled by injecting charge on the gate using high voltage between gate and
drain.
2. The charge is removed by UV light. Reprogramming through exposure to UV light.
 3. Non volatile.
4. Slower programming than SRAM.
Advantages
1. No external permanent memory is needed to program it at power up.
Disadvantages

1. Extra processing steps

2. Static power loss due to pull up resistor high resistance.

FPGA Families
• FPGA families are
– Altera flex
– Spartan
– Virtex
Altera flex:

Basic Architecture of ALTERA FLEX 8000 consists of

– Grid of Logic Array Block(LABs) each consisting of 8 independently
programmable Logic Elements(LEs)
– LABs are connected in rows & columns ,connected by FastTrack Interconnect
with Input-Output elements(IOEs) at the edges
– Ends of interconnect connected to each having
• bidirectional I/O buffer
• Flip-flop to register input or output
– Logic Element has
• 4 I/P LUT
• Programmable Register -has 4 low skew global clock ,clear or preset
control signals from Dedicated input ,I/O pin or Internal signal from LAB
local interconnect
• Dedicated Carry & cascade chains
– 4 signals common to each LE in a LAB
• 2 used as clocks
• 2 used for clear/preset control
Xilinx XC4000:

Basic Architecture of XC4000 consists of

• CLBs
• Local & Global routing resources
• Programmable I/O buffers
• SRAM based memory configuration
• Each CLB consists of
• LUT
• Multiplexers
• Registers
• Path for control signal
• Each CLB contains 3 function generators (F,G,H)
• Each function generator is based on an LUT with 5ns delay independent of
function being implemented
• 2 Function generators(F & G) can generate any arbitrary function of 4 I/ps and
third (H) can generate any Boolean functions of 3 I/Ps
 • H function block can get inputs from either F & G LUTs or from external inputs.
• The 3 Function generators are programmed to generate
• 2 different functions of 3 independent sets of variables-one function must
be registered with CLB
• An arbitary function of 5 variables
• An arbitary function of 4 variables together with some functions of 6
variables
• Some function of 9 variables
Distributed RAM:
• 3 Function generators can be used as RAM either 16X2 dual port RAM or 32X1 single
port RAM
• Don’t have block RAM but a group of CLBs form an array of memory
XILINX SPARTAN II FPGAs
1. Contains several logic & memory resources that can support 15K-200K system gates &
up to 57Kb block RAM storage
2. Contains flexible Input/output (I/O) interfaces
3. Manufactured in 0.25/0.18um CMOS technology with 6-layers metal for interconnection.
4. High performance & high system frequency of 200MHz.
5. Provides advanced Clock Control with 4 Dedicated Delay Lock Loops( DLL).
6. Supports unlimited reprogramability.

7. Each of four quadrants of CLBs is supported by DLL

8. Bounded by 406bit block RAM
9. Periphery of the chip is lined with IOBs
10. Each CLBs contains four logic cells organised as a pair of slices
11. Each logic cell has
• 4 i/p LUT
• Logic for carry and control
• D F/F
 12. Each LUT can be configured as a 16X1 RAM(distributed) and the pair of LUTs in a logic
cell configured as 16X2 bit RAM or 32X1 Bit RAM
13. IOBs are individually programmable to support reference,output voltage and termination
voltagesfor high speed memory & bus standards
14. Each IOB has 3 registers functioning as D F/F or as level sensitive latches:
• One register (TFF) used to register the signal that controls (synchronously)
programmable output buffer
• Second register(OFF) is programmed to register a signal from internal logic
( alternatively, a signal from internal logic can pass directly to the output buffer)
• Third device to register signal coming from I/O pad

• Common clock drives each register but has an independent clock enable
• Programmable delay element on the input path used to eliminate the pad-to pad hold
time
XILINX VIRTEX FPGAS
• Leading edge of Xilinx Technology
• Addresses 4 key factors influencing the solution to complex system-level and system-on-
chip (SoC) designs:
 – Level of Integration
– Amount of embedded memory
– Performance(timing)
– Subsystem interfaces
ARCHITECTURE :
• The programmable device is comprised of input/output blocks (IOBs) and internal
configurable logic blocks (CLBs).
– Programmable I/O blocks provide the interface between package pins and the
internal configurable logic.
– leading-edge I/O standards are supported by the programmable IOBs.
• Includes four major elements organized in a regular array
– Configurable Logic Blocks (CLBs) provide functional elements for combinatorial
and synchronous logic, including basic storage elements. BUFTs (3-state buffers)
associated with each CLB element drive dedicated segmentable horizontal routing
resources.
– Block SelectRAM memory modules provide large 18 Kbit storage elements of
dual-port RAM.
– Multiplier blocks are 18-bit x 18-bit dedicated multipliers.
– DCM (Digital Clock Manager) blocks provide self-calibrating, fully digital
solutions for clock distribution delay compensation, clock multiplication and
division, coarse- and fine-grained clock phase shifting.
• A new generation of programmable routing resources called Active Interconnect
Technology interconnects all of these elements.
• The general routing matrix (GRM) is an array of routing switches.
• Each programmable element is tied to a switch matrix, allowing multiple connections to
the general routing matrix
• All programmable elements, including the routing resources, are controlled by values
stored in static memory cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions of the programmable elements.
Virtex-II Features
Input/Output Blocks (IOBs):
IOBs are programmable and can be categorized as follows:
 Input block with an optional single-data-rate or double-data-rate (DDR) register
 Output block with an optional single-data-rate or DDR register, and optional 3-state
buffer, to be driven directly or through a single or DDR register
 Bidirectional block (any combination of input and output configurations)
 IOB blocks include six storage elements, as shown in figure
 Each storage element can be configured either as an edge-triggered D-type flip-flop or as
a level-sensitive latch
 On the input, output, and 3-state path, one or two DDR registers can be used.
 Double data rate is directly accomplished by the two registers on each path, clocked by
the rising edges (or falling edges) from two different clock nets.
 The two clock signals are generated by the DCM and must be 180 degrees out of phase
 There are two input, output, and 3-state data signals, each being alternately clocked out.
 • These registers are either edge-triggered D-type flip-flops or level-sensitive latches.
• IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI-X compatible (133 MHz and 66 MHz) at 3.3V
• PCI compliant (66 MHz and 33 MHz) at 3.3V
• CardBus compliant (33 MHz) at 3.3V • GTL and GTLP
The IOB elements also support the following differential signaling I/O standards:
• LVDS ,BLVDS (Bus LVDS) • ULVDS • LDT • LVPECL
• Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to
one switch matrix to access the routing resources.
CLBs
• CLB resources include four slices and two 3-state buffers.
• Each slice is equivalent and contains:
• Two function generators (F & G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Wide function capability
• Fast carry look-ahead chain
• Horizontal cascade chain (OR gate).
 • The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-
bit shift registers, or as 16-bit distributed SelectRAM memory.
• The two storage elements are either edge-triggered D-type flip-flops or level-sensitive
latches.
• Each CLB has internal fast interconnect and connects to a switch matrix to access general
routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of dual-port RAM, programmable from 16K
x 1 bit to 512 x 36 bits, in various depth and width configurations.

INTRODUCTION TO ADVANCED TECHNOLOGIES

Giga scale dilemma:
1. 1B Transistors integration capacity will be available
2. But could be unusable due to power
3. Logic Technology growth will slow down
4. Transistor performance will be limited
Solutions
1. Low power design techniques
2. Improve design efficiency—Multi everywhere
3. Valued performance by even higher integration (of potentially slower transistors).
Gigascale transistor integration capacity will be available—Power and Energy barriers.
Variations will be even more prominent — shift from Deterministic to Probabilistic design.
Short channel effects
Five different physical phenomena have to be considered in short-channel devices:
• Drain induced barrier lowering and Punch-through
• Surface scattering
• Velocity saturation
• Hot electrons
Drain-induced barrier lowering (DIBL)
• The electrons (carriers) in the channel face a potential barrier that blocks
their flows.
• The potential barrier, in small-geometry MOSFETs, is controlled by a two-
dimensional electric field vector (in other words by both VGS and VDS).
• If the drain voltage is increased the potential barrier in the channel
decreases, leading to Drain-Induced Barrier Lowering (DIBL).
• Under DIBL conduction electrons can flow between the source and drain
even if VGS < VT.
• The channel current that flows in this case is called sub-threshold current
Punch-through.
• The DIBL phenomenon can be accompanied by the so-called punch-
through, that occurs when the depletion region surrounding the drain extends
to the source.
• Punch-through minimized with thinner oxide, larger substrate doping (and
longer channel!)
Surface scattering
For small geometry MOSFECTs, the electrons mobility in the channel depends on
a two dimensional electric field (ε x , ε y ).
Velocity Saturation

Hot electrons:
High-k Dielectric
• High-K dielectric refers to a material with a high dielectric
constant (κ, kappa), as compared to silicon dioxide.
• used in semiconductor manufacturing processes where they are usually used
to replace a silicon dioxide gate dielectric or another dielectric layer of a
device.
• As metal-oxide-semiconductor field-effect transistors (MOSFETs) have
decreased in size, the thickness of the silicon dioxide gate dielectric has
steadily decreased to increase the gate capacitance (per unit area) and
thereby drive current (per device width), raising device performance.
• As the thickness scales below 2 nm, leakage currents due
to tunneling increase drastically, leading to high power consumption and
reduced device reliability
• Replacing the silicon dioxide gate dielectric with a high-κ material allows
increased gate capacitance without the associated leakage effects.
FINFET Technology
Basics of FINFET:
• Type of Multi-gate MOSFET
• Widely used over Planer MOSFET
• FIN is channel in between source & drain
• Can have two or four or more FIN in same structure
• Advantages over FET
 Low Area
 Lower leakage power
 Low voltage operation
 Lower retention voltage for SRAM
 It is better control over current
Structure of Fin FET:

In planar FET the Gate is placed above the channel and there is leakage current flowing from
source to drain even when the gate is off. Like the normal FET , FinFET consists of a source,
drain and also a gate to control the current flow.In the FinFET the channel is thin vertical fin and
gate is wrapped around it. This helps in better controlling of the channel and thus the electrical
properties are better. FinFET can have two to four fins in the same structure.
Advantages:
• Lower power Consumption
• Operates at low voltage
• Operating speed is high
• Static Leakage current s reduced upto 90%
• Compact
Disadvantages:
• Fabrication cost is higher than CMOS circuit
• Controlling fin depth is difficult
Applications of FinFET:
• Used in microprocessor
• Used In microcontroller
• Used in smart Phone
• Used in compact chip