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Lec 17 CLD

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9 views21 pages

Lec 17 CLD

Uploaded by

Zahid Abbas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE 105 Computer Logic Design

Lecture 17
STORAGE ELEMENTS: FLIP-FLOPS
 State of a latch or flip-flop is switched by a change in the
control input; this momentary change is called a trigger
 Transition it causes is said to trigger the flip-flop
 D latch with pulses in its control input = A flip-flop
 Flip-flop is triggered every time pulse goes to logic-1 level
 When triggered, any changes in data input will change output
and state of the latch
 When Latches are used for the storage elements
 A serious difficulty and problem with the latch is that it
responds to a change in the level of a clock pulse
 State of the latches may keep changing for as long as the
clock pulse stays at the active level
STORAGE ELEMENTS: FLIP-FLOPS
 Changes in the output when the D input changes while the
clock pulse stays at logic 1
 Key to the proper operation of a flip-flop is to trigger it
only during a signal transition
 Clock pulse goes through
two transitions:
from 0 to 1 and the return
from 1 to 0
 Positive transition is
defined as the positive
edge and the negative
transition as the negative edge
STORAGE ELEMENTS: FLIP-FLOPS
Two ways to form a flip-flop:
 One way is to employ two latches in a special configuration
that isolates the output of the flip-flop and prevents it
from being affected while the input to the flip-flop is
changing
 Another way is to produce a flip-flop that triggers only
during a signal transition (from 0 to 1 or from 1 to 0) of
the synchronizing signal (clock) and is disabled during the
rest of the clock pulse
 We will now proceed to show the implementation of both
types of flip-flops
Edge-Triggered D Flip-Flop
 A D flip-flop with two D latches and an inverter
 First latch is called Master and the second Slave
 Circuit samples the D input and changes its output Q only
at the negative edge of controlling clock Clk
Edge-Triggered D Flip-Flop
When Clk = 0, (output of inverter is 1)
 Slave latch is enabled
 And its output Q is equal to the master output Y
 Master latch is disabled
 Because Clk = 0
When Clk = 1, (when input pulse changes to the logic-1 level)
 Master latch is enabled and data from the external D
input are transferred to the master
 Slave latch is disabled as long as the clock remains at the
1 level, because its enable input is equal to 0
 Any change in the input changes the master output at Y,
but cannot affect the slave output
Edge-Triggered D Flip-Flop
 When the clock pulse returns to 0,
 Master is disabled and is isolated from the D input
 At the same time, Slave is enabled and the value of Y is
transferred to the output of the flip-flop at Q
 Thus, a change in the output of the flip-flop can be
triggered only by and during the transition of the clock
from 1 to 0
Edge-Triggered D Flip-Flop
 Behavior of the master–slave flip-flop just described
dictates that
(1) the output may change only once
(2) a change in the output is triggered by the negative edge of
the clock, and
(3) the change may occur only during the clock’s negative level
 The value that is produced at the output of the flip-flop is
the value that was stored in the master stage immediately
before the negative edge occurred
Edge-Triggered D Flip-Flop
 It is also possible to design the circuit so that the flip-flop
output changes on the positive edge of the clock
 This happens in a flip-flop that has an additional inverter
between the Clk terminal and the junction between the
other inverter and input En of the master latch
 Such a flip-flop is triggered with a negative pulse, so that
the negative edge of the clock affects the master and the
positive edge affects the slave and the output terminal
Edge-Triggered D Flip-Flop
 Another
construction
of an edge-
triggered D
flip-flop uses
three SR
latches
Edge-Triggered D Flip-Flop
 Two latches respond to D (data) and Clk (clock) inputs
 Third latch provides the outputs for the flip-flop
 When Clk = 0, the S and R inputs of the output latch are
maintained at the logic-1 level
 This causes the output to remain in its present state

 When Clk =1, If D = 0, R changes to 0. This causes the flip-


flop to go to the reset state, making Q = 0
Edge-Triggered D Flip-Flop
 If there is a change in the D input while Clk = 1, terminal R
remains at 0 because Q is 0
 Thus, the flip-flop is unresponsive to further changes in
the input
 When the clock returns to 0, R goes to 1, placing the
output latch in the quiescent condition without changing
the output
 Similarly, if D = 1 when Clk goes from 0 to 1, S changes to
0
 This causes the circuit to go to Set state, making Q = 1.
 Any change in D while Clk = 1 does not affect the output
Edge-Triggered D Flip-Flop
Summarizing
 When the input clock in the positive-edge-triggered flip-
flop makes a positive transition, the value of D is
transferred to Q
 A negative transition of the clock (i.e., from 1 to 0) does
not affect the output, nor is the output affected by
changes in D when Clk is in the steady logic-1 level or the
logic-0 level
 Hence, this type of flip-flop responds to the transition
from 0 to 1 and nothing else
Edge-Triggered D Flip-Flop
 Similar to the symbol used for the D latch, except for the
arrowhead-like symbol in front of the letter Clk,
designating a dynamic input
 Sign > denotes the fact that the flip-flop responds to the
edge transition of the clock. A bubble outside the block
adjacent to the dynamic indicator designates a negative
edge for triggering the circuit
 Absence of a bubble designates a positive-edge response
Other Flip-Flops
 Very large-scale integration circuits contain several
thousands of gates within one package
 Flip-flop is constructed from an interconnection of gates
 Most economical and efficient flip-flop constructed in this
manner is the edge-triggered D flipflop, because it
requires the smallest number of gates
 Other types of flip-flops can be constructed by using
 D flip-flop
 and external logic
 Two flip-flops less widely used in digital systems are the
 JK flip-flop
 and T flip-flop
JK Flip-Flop
 Synchronized by a clock signal, the JK flip-flop has two
inputs and performs three operations
 The circuit diagram of a JK flip-flop constructed with a D
flip-flop and gates is shown
JK Flip-Flop
 J input sets the flip-flop to 1, K input resets it to 0
 When both inputs are enabled, the output is complemented
 Circuit applied to the D input:
D = JQ’ + K’Q
 When J = 1 and K = 0, D = Q + Q’ = 1, so the next clock
edge sets the output to 1
 When J = 0 and K = 1, D = 0, so the next clock edge resets
the output to 0
 When both J = K = 1 and D = Q’ , the next clock edge
complements the output
 When both J = K = 0 and D = Q , the clock edge leaves the
output unchanged
T Flip-Flop
 T (toggle) flip-flop is a complementing flip-flop
 It can be obtained from a JK flip-flop when inputs J and K
are tied together, Fig(a)
 When T = 0 (or J = K = 0), a clock edge does not change
the output
 When T = 1 (or J = K = 1), a clock edge complements output
T Flip-Flop
 T flip-flop is useful for designing binary counters
 T flip-flop can be constructed with a D flip-flop and an
exclusive-OR gate, Fig(b)
 Expression for the D input is D = T Q = TQ’ + T’Q
 When T = 0, D = Q and there is no change in the output.
 When T = 1, D = Q’ and the output complements.
 Graphic symbol for this flip-flop has a T symbol in input
Flip-Flop Characteristic Tables
 Characteristic table defines the logical properties of a
flip-flop by describing its operation in tabular form
Flip-Flop Characteristic Tables
 Characteristic tables define the next state (i.e., the state
that results from a clock transition) as a function of the
inputs and the present state.
 Q ( t ) is the present state (i.e., the state present prior to
the application of a clock edge)
 Q(t + 1) is the next state one clock period later
 Thus, Q(t) denotes the state of the flip-flop immediately
before the clock edge, and Q(t + 1) denotes the state that
results from the clock transition.

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