Lecture 3:

CMOS
Transistor
Theory
 Outline
q Introduction
q MOS Capacitor
q nMOS I-V Characteristics
q pMOS I-V Characteristics
q Gate and Diffusion Capacitance

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 2

 Goal of this section
q Present intuitive understanding of device
operation
q Introduction of basic device equations
q Introduction of models for manual analysis
q Introduction of models for SPICE simulation
q Future trends

CMOS VLSI Design 4th Ed.

 Diodes
q Diodes do not appear in CMOS digital design as
separate devices.
q However, they are present as junctions and parasitic
elements in all devices.
q We will use a simple 1D analysis.
q We will not concern ourselves too much with the DC
behavior.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 4

Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge r
Density
+ x (b) Charge density.
Distance
-

Electrical x
Field x
(c) Electric field.

V
Potential
y0 (d) Electrostatic
x potential.
-W 1 W2

CMOS VLSI Design 4th Ed.

 DC Characteristics

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 6

Diode Current

CMOS VLSI Design 4th Ed.

 Forward Bias

pn (W2)
pn0

Lp

np0

-W1 0 W2 x
p-region n-region

diffusion
Typically avoided in Digital ICs
CMOS VLSI Design 4th Ed.
 Reverse Bias

pn0

np0

-W1 0 W2 x
p-region n-region

diffusion

The Dominant Operation Mode

CMOS VLSI Design 4th Ed.
 Models for Manual Analysis

ID = IS(eV D/fT – 1) ID
+ +
+
VD VD VDon
–
– –

(a) Ideal diode model (b) First-order diode model

CMOS VLSI Design 4th Ed.

 Junction Capacitance

where

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 11

Junction Capacitance

CMOS VLSI Design 4th Ed.

 Junction Capacitance
q m is known as the grading coefficient.
q Keep in mind that Cj is a small signal parameter. For
large signal switching, an equivalent capacitance
has to be calculated as

q Ceq has been defined such that the same amount of

charge is transferred as the nonlinear model

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 13

 Junction Capacitance
q As a numerical example, a diode is switched
between 0 and -2.5 V. The diode has Cj0 = 2 X 10-3
F/m2, AD = 0.5 (µm)2, F0 = 0.64 V, m = 0.5.
q Keq = 0.622, Ceq = 1.24 fF/(µm)2.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 14

Diffusion Capacitance

CMOS VLSI Design 4th Ed.

 Diffusion Capacitance
q Effective in forward bias

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 16

 Diffusion Capacitance
q From this lifetime analysis of excess charge,

q Note that Cd is also a small signal capacitance

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 17

 Other Diode Parameters
q Secondary Effects
– Resistivity of regions outside junction
– Breakdown voltage
– Temperature dependence
• FT has a linear dependence
• IS doubles every 8˚C
• Overall, current doubles every 12˚C.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 18

 SPICE Model
q The following summarize diode behavior:

q n is called the emission coefficient and concentrates

the non-idealities listed above.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 19

SPICE Parameters

CMOS VLSI Design 4th Ed.

 Introduction
q So far, we have treated transistors as ideal switches
q An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
q Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 21

 MOS Capacitor
q Gate and body form MOS
capacitor polysilicon gate
V <0
q Operating modes +
g
silicon dioxide insulator

- p-type body
– Accumulation
– Depletion (a)

– Inversion 0<V <V g t

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 22

 Terminal Voltages
q Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs + +
Vgs Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs Vd

- +
Vds
q Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds ³ 0
q nMOS body is grounded. First assume source voltage is 0 too.
q Three regions of operation
– Cutoff
– Linear (Resistive)
– Saturation (Active)

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 23

 nMOS Cutoff
q No channel
q Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 24

 nMOS Linear
q Channel forms
q Current flows from d to s
V > Vt
– e from s to d
- Vgd = Vgs
gs
+ g +
- -
q Ids increases with Vds s d
Vds = 0
n+ n+
q Similar to linear resistor p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 25

 nMOS Saturation
q Channel pinches off
q Ids independent of Vds
q We say current saturates
q Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 26

 I-V Characteristics
q In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 27

 Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion.
– Gate – oxide – channel
q Qchannel = CV
q C = Cg = eoxWL/tox = CoxWL Cox = eox / tox
q V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 28

 Carrier velocity
q Charge is carried by electrons.
q Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
q Carrier velocity v proportional to lateral E-field
– v = µE µ called mobility
q Time for carrier to cross channel:
– t=L/v

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 29

 nMOS Linear I-V
q Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
W æV - V - Vds öV
= µCox ç gs ÷ ds
L è
t 2 ø
W
= b æçVgs - Vt - ds ö÷Vds
V b = µCox
è 2ø L

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 30

 nMOS Saturation I-V
q If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
q Now drain voltage no longer increases current

æ
I ds = b çVgs - Vt -
Vdsat öV
2 ÷ dsat
è ø
b
( - Vt )
2
= V gs
2

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 31

 nMOS I-V Summary
q Shockley 1st order transistor models

ì
ï 0 Vgs < Vt cutoff
ï
ï æ Vds öV V < V
I ds = í b çVgs - Vt - ÷ ds linear
è 2 ø
ds dsat
ï
ï b
(Vgs - Vt )
2
ïî Vds > Vdsat saturation
2

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 32

 Example
q Your book will be using a 0.6 µm process
– From AMI Semiconductor
– tox = 100 Å 2.5
V =5
– µ = 350 cm /V*s
gs
2
2
– Vt = 0.7 V 1.5 V =4

Ids (mA)
gs

q Plot Ids vs. Vds 1

V =3
– Vgs = 0, 1, 2, 3, 4, 5 0.5
gs

V =2
– Use W/L = 4/2 l 0
V =1 gs
gs

0 1 2 3 4 5
W æ 3.9 ´ 8.85 ×10-14 ö æ W ö W Vds
b = µ Cox = ( 350 ) ç -8 ÷ç ÷ = 120 µA/V
2

L è 100 × 10 øè L ø L

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 33

 pMOS I-V
q All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
q Mobility µp is determined by holes
– Typically 2-3x lower than that of electrons µn
– 120 cm2/V•s in AMI 0.6 µm process
0

q Thus pMOS must be wider to

Vgs = -1
Vgs = -2

-0.2
provide same current Vgs = -3

Ids (mA)
– In this class, assume -0.4
Vgs = -4

µn / µp = 2 -0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 34

 Capacitance
q Any two conductors separated by an insulator have
capacitance
q Gate to channel capacitor is very important
– Creates channel charge necessary for operation
q Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 35

 Level 1 Implementation in SPICE

q Including the channel length modulation, body effect

and overlaps,

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 36

 The Body Effect
0 .9

0 .8 5

0 .8

0 .7 5

0 .7
(V )

0 .6 5
T
V

0 .6

0 .5 5

0 .5

0 .4 5

0 .4
-2 .5 -2 -1 .5 -1 -0 .5 0
V (V )
BS

CMOS VLSI Design 4th Ed.

 SPICE Model
Name Symbol SPICE Type
Name
Lateral Diffusion LD LD Physical
Oxide Thickness tox TOX Physical
Channel length modulation l LAMBDA Physical
Surface Mobility µ U0 Physical
Substrate Doping NA NSUB Physical
Current Parameter kp KP Electrical
Work Function fS PHI Electrical
Threshold Voltage VT0 VTO Electrical
Body Effect Parameter g GAMMA Electrical

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 38

 SPICE Model
q Electrical parameters override when provided.
q Otherwise, they are calculated from physical
parameters.
q LAMBDA is an empirical parameter.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 39

 Level 2 Implementation in SPICE

q Now, let us remove some of the wrong assumptions.

q Voltage across channel is not constant any more
q The threshold voltage is not a constant any more

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 40

 Level 2 Implementation in SPICE

q To find the equation in the active region, take the

derivative of ID and equate to 0.
q VDS = VDS,sat when ID is maximum.

q Note that ID is dependent on g even if VSB = 0.

q VT is not explicitly used in the equations.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 41

 More Corrections
q Mobility is reduced with increasing gate voltage.
– We will study this effect in detail later.
q Current conduction occurs below the threshold
voltage.
– We will study this effect later.
q Channel length modulation has to be corrected.
q Threshold voltage depends on W and L.
q Parasitic resistances in the source and drain
q Latchup
q Speed limit of carriers

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 42

 Speed Limit of Carriers
q Ohm’s Law is not true

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 43

 Speed Limit of Carriers
q Velocity is proportional to electric field for low fields

q Velocity is saturated for high fields

q To ensure continuity, use the following

approximation for velocity.

q Then,

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 44

 Speed Limit of Carriers
q That equation is still too complex for hand analysis.
q Substitute the values at the critical electric field to
find the current at the transition point.

q An even simpler approach is as follows

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 45

A Unified Model for Manual Analysis

CMOS VLSI Design 4th Ed.

Transistor Model for Manual Analysis

CMOS VLSI Design 4th Ed.

 The Transistor as a Switch

VGS ³ V T
R on ID
V GS = VD D
S D
Rmid

R0

V DS
VDD/2 VDD

CMOS VLSI Design 4th Ed.

Drain-Source Resistance
q Large signal drain-source resistance is a nonlinear
quantity varying across operating regions.
q One can define an equivalent resistance

q For a weakly nonlinear function,

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 49

Drain-Source Resistance
q Applying the general formula for a transistor
switching from VDD to VDD/2,

q Alternatively, using the endpoints and averaging,

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 50

Drain-Source Resistance
5
x 10
7

5
(O hm )

4
eq

3
R

0
0 .5 1 1 .5 2 2 .5
V (V )
DD

CMOS VLSI Design 4th Ed.

Drain-Source Resistance

CMOS VLSI Design 4th Ed.

Drain-Source Resistance
q Note the following
– R is inversely proportional to W/L
– For VDD >> VT + VD,sat/2, R is independent of VDD.
– When VDD is close to VT, resistance increases.

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 53

 MOS Capacitances
G

CGS CGD

S D

CSB CGB CDB

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 54

 Gate Capacitance
q Approximate channel as connected to source
q Cgs = eoxWL/tox = CoxWL = CpermicronW
q Cpermicron is typically about 2 fF/µm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 55

 Gate Capacitance

Operation Region Cgb Cgs Cgd

Cut-off CoxWLeff Cov Cov

Resistive 0 CoxWLeff/2 + Cov CoxWLeff/2 + Cov

Active 0 (2/3) CoxWLeff + Cov Cov

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 56

 Diffusion Capacitance
q Csb, Cdb
q Undesirable, called parasitic capacitance
q Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 57

Capacitances in 0.25 µm CMOS Process

CMOS VLSI Design 4th Ed.

 Sub-Threshold Conduction
-2
10
The Slope Factor
Linear
qVGS
10
-4
CD
I D ~ I 0e nkT
, n = 1+
Cox
-6
10 Quadratic
(A)

S is DVGS for ID2/ID1 =10

ID

-8
10

-10 Exponential
10

-12
VT
10
0 0.5 1 1.5 2 2.5 Typical values for S:
VGS (V)
60 .. 100 mV/decade

CMOS VLSI Design 4th Ed.

Sub-Threshold ID vs VGS
qVGS
æ qV
- DS ö
I D = I 0e nkT ç1 - e kT ÷
ç ÷
è ø

VDS from 0 to 0.5V

CMOS VLSI Design 4th Ed.

Sub-Threshold ID vs VDS
qVGS
æ qV
- DS ö
I D = I 0e nkT ç1 - e kT ÷(1 + l × VDS )
ç ÷
è ø

VGS from 0 to 0.3V

CMOS VLSI Design 4th Ed.

 Scaling

Parameter Relation Full Scaling Fixed V General

scaling Scaling
W, L, tox - 1/S 1/S 1/S
VDD, VT - 1/S 1 1/U
NSUB V/W2depl S S2 S2/U
Area/Device WL 1/S2 1/S2 1/S2
Cox 1/tox S S S
Cgate CoxWL 1/S 1/S 1/S
kn, kp CoxW/L S S S

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 62

 Scaling (Continued)
Parameter Relation Full Scaling Fixed V General
Scaling Scaling
ID,sat CoxWV 1/S 1 1/U
Current ID,sat/Area S S2 S2/U
Density
Ron V/ID,sat 1 1 1
Intrinsic RonCgate 1/S 1/S 1/S
Delay
Power ID,satV 1/S2 1 1/U2
Power Power/Area 1 S2 S2/U2
Density

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 63