Technical Guide

Types MiCOM P441 & P442

Distance Protection Relays

Chapter 3
Relay Description
TECHNICAL GUIDE TG 1.1671
MiCOM P441 & P442 Volume 1
DISTANCE PROTECTION RELAYS Chapter 3
Contents
Page 1 of 1
SECTION 1. RELAY SYSTEM OVERVIEW 1
1.1 Hardware overview 1
1.1.1 Main processor board 1
1.1.2 Co-processor board 1
1.1.3 Input module 1
1.1.4 Power supply module 1
1.1.5 Supplementary input and output boards 1
1.1.6 IRIG-B board (P442 only) 1
1.2 Software overview 2
1.2.1 Real-time operating system 3
1.2.2 System services software 3
1.2.3 Platform software 3
1.2.4 Protection & control software 3
1.2.5 Disturbance Recorder 3
SECTION 2. HARDWARE MODULES 4
2.1 Main processor and co-processor boards 4
2.2 Internal communication buses 4
2.3 Input module 5
2.3.1 Transformer board 5
2.3.2 Input board 5
2.4 Power supply module (including output relays) 7
2.4.1 Power supply board (including RS485 communication interface) 7
2.4.2 Output relay board 8
2.5 IRIG-B board (P442 only) 8
2.6 Mechanical layout 8
SECTION 3. RELAY SOFTWARE 9
3.1 Real-time operating system 9
3.2 System services software 9
3.3 Platform software 10
3.3.1 Record logging 10
3.3.2 Settings database 10
3.3.3 Database interface 10
3.4 Protection and control software 10
3.4.1 Overview - protection and control scheduling 11
3.4.2 Signal processing 11
3.4.3 Programmable scheme logic 12
3.4.4 Event and Fault Recording 12
3.4.5 Disturbance recorder 12
SECTION 4. DISTANCE ALGORITHMS 13
4.1 Distance and Resistance Measurement 13
4.2 "High-Speed" Algorithms 15
4.2.1 Fault Modelling 15
4.2.2 Detecting a Transition 17
4.2.3 Confirmation 18
4.2.4 Defining Direction 18
4.2.5 Phase Selection 19
4.2.6 Summary 19
4.3 "Conventional" Algorithms 20
4.3.1 Convergence Analysis 20
4.3.2 Start-Up 21
4.3.3 Phase Selection 21
4.3.4 Directional Decision 22
4.3.5 Directional Decision during SOTF/TOR 22
4.4 Faulted Zone Decision 23
4.5 Tripping Logic 24
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Contents
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4.6 Fault Locator 24
4.6.1 Selecting the fault location data 25
4.6.2 Processing algorithms 25
4.7 Power swing detection 25
4.7.1 Power swing detection 26
4.7.2 Line in one pole open condition (during single-pole trip) 26
4.7.3 Conditions for isolating lines 27
4.7.4 Tripping logic 27
4.7.5 Fault Detection after Single-phase Tripping (one-pole-open condition) 27
4.8 Double Circuit Lines 28
4.9 DEF Protection Against High Resistance Ground Faults 29
4.9.1 High Resistance Ground Fault Detection 29
4.9.2 Directional determination 29
4.9.3 Phase selection 30
4.9.4 Tripping Logic 30
4.9.5 SBEF – Stand-By earth fault (not communication-aided) 31
SECTION 5. SELF TESTING & DIAGNOSTICS 33
5.1 Start-up self-testing 33
5.1.1 System boot 33
5.1.2 Initialisation software 33
5.1.3 Platform software initialisation & monitoring 34
5.2 Continuous self-testing 34

Figure 1: Relay modules and information flow 2

Figure 2: Main Input Board 6
Figure 3: Relay software structure 9
Figure 4: Signal acquisition and processing 11
Figure 7: Distance and fault resistance estimation 13
Figure 8: Phase-to-earth loop impedance 14
Figure 9: Phase-to-phase loop impedance 15
Figure 10: Pre, Fault and Fault Inception Value 16
Figure 11: Transition detection 17
Figure 12: Directional determination using superimposed values 18
Figure 12: High-Speed algorithms 19
Figure 13: Start-up characteristic 20
Figure 14: Phase-to-earth loop impedance 23
Figure 15: Power swing 26
Figure 16: Selective Protection Blocking 27
Figure 17: Direction Reversal from Sequential Clearing of Parallel Lines 28
Figure 18: Directional Comparison Protection Permissive Scheme 30
Figure 19: Directional comparison protection blocking scheme 31
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Section 1. RELAY SYSTEM OVERVIEW

1.1 Hardware overview

The relay hardware is based on a modular design whereby the relay is made up of
several modules which are drawn from a standard range. Some modules are
essential while others are optional depending on the user’s requirements.
The different modules that can be present in the relay are as follows:
1.1.1 Power supply module
The power supply module provides a power supply to all of the other modules in the
relay, at three different voltage levels. The power supply board also provides the
RS485 electrical connection for the rear communication port. On a second board the
power supply module contains relays which provide 7 output contacts.
1.1.2 Main processor board
The processor board performs most of the calculations for the relay (fixed and
programmable scheme logic, protection functions other than distance protection) and
controls the operation of all other modules within the relay. The processor board also
contains and controls the user interfaces (LCD, LEDs, keypad and communication
interfaces).
1.1.3 Co-processor board
The co-processor board manages the acquisition of analogue quantities, filters them
and calculates the thresholds used by the protection functions. It also processes the
distance algorithms.
1.1.4 Input module
The input module converts the information contained in the analogue and digital
input signals into a format suitable for the co-processor board. The standard input
module consists of two boards: a transformer board to provide electrical isolation and
a main input board which provides analogue to digital conversion and 8 isolated
digital inputs.
1.1.5 Supplementary input and output boards
The P441 has one supplementary output board to provide 7 output contacts.
The P442 contains two supplementary output boards to provide 14 output contacts. It
has also one supplementary input board which provides 8 isolated digital inputs.
1.1.6 IRIG-B board (P442 only)
This board, which is optional, can be used where an IRIG-B signal is available to
provide an accurate time reference for the relay. There is also an option on this board
to specify a fibre optic rear communication port, for use with IEC60870
communication only.
All modules are connected by a parallel data and address bus which allows the
processor board to send and receive information to and from the other modules as
required. There is also a separate serial data bus for conveying sample data from the
input module to the processor. Figure 1 shows the modules of the relay and the flow
of information between them.
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Present values CPU code & data,

Alarm, event, fault & of all Default settings &
maintenance setting database parameters, language text,
settings data
records software code
Battery
backed-up E²PROM SRAM Flash
SRAM EPROM

Front LCD panel RS232 Front comms port

Parallel test port CPU
LEDs Main processor board
Comms between CPU code
IRIG-B signal main & coprocessor & data
IRIG-B board boards
Fibre optic (optional)
rear comms
port optional Timing FPGA SRAM
data

CPU
Serial data bus
(sample data)

Coprocessor board
Power supply, rear comms,
data, output relay status Parallel data bus Digital input values

Digital inputs (x8 or x16)

Opto-ilsolatedinputs
Output relay contacts

Output relays
(x14 or x21)

Relay board ADC Input board

Power supply (3 voltages),

rear comms data Analogue input signals

Power supply Transformer

board board

Power Watchdog Field Rear RS485 Current & voltage inputs (6 to 8)

supply contacts voltage communication port

Figure 1: Relay modules and information flow

1.2 Software overview

The software for the relay can be conceptually split into four elements: the real-time
operating system, the system services software, the platform software and the
protection and control software. These four elements are not distinguishable to the
user, and are all processed by the same processor board. The distinction between the
four parts of the software is made purely for the purpose of explanation here:
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1.2.1 Real-time operating system

The real time operating system is used to provide a framework for the different parts
of the relay’s software to operate within. To this end the software is split into tasks.
The real-time operating system is responsible for scheduling the processing of these
tasks such that they are carried out in the time available and in the desired order of
priority. The operating system is also responsible for the exchange of information
between tasks, in the form of messages.
1.2.2 System services software
The system services software provides the low-level control of the relay hardware. For
example, the system services software controls the boot of the relay’s software from
the non-volatile flash EPROM memory at power-on, and provides driver software for
the user interface via the LCD and keypad, and via the serial communication ports.
The system services software provides an interface layer between the control of the
relay’s hardware and the rest of the relay software.
1.2.3 Platform software
The platform software deals with the management of the relay settings, the user
interfaces and logging of event, alarm, fault and maintenance records. All of the
relay settings are stored in a database within the relay which provides direct
compatibility with Courier communications. For all other interfaces (i.e. the front
panel keypad and LCD interface, Modbus and IEC60870-5-103) the platform
software converts the information from the database into the format required. The
platform software notifies the protection & control software of all setting changes and
logs data as specified by the protection & control software.
1.2.4 Protection & control software
The protection and control software performs the calculations for all of the protection
algorithms of the relay. This includes digital signal processing such as Fourier filtering
and ancillary tasks such as the measurements. The protection & control software
interfaces with the platform software for settings changes and logging of records, and
with the system services software for acquisition of sample data and access to output
relays and digital opto-isolated inputs.
1.2.5 Disturbance Recorder
The disturbance recorder software is passed the sampled analogue values and logic
signals from the protection and control software. This software compresses the data
to allow a greater number of records to be stored. The platform software interfaces
to the disturbance recorder to allow extraction of the stored records.
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Section 2. HARDWARE MODULES

The relay is based on a modular hardware design where each module performs a
separate function within the relay operation. This section describes the functional
operation of the various hardware modules.

2.1 Main processor and co-processor boards

The relay is based around a TMS320C32 floating point, 32-bit digital signal
processor (DSP) operating at a clock frequency of 40MHz. This processor performs
most of the calculations for the relay including most protection functions, and control
of the data communication and user interfaces including the operation of the LCD,
keypad and LEDs.
The processor board is located directly behind the relay’s front panel which allows the
LCD and LEDs to be mounted on the processor board along with the front panel
communication ports. These comprise the 9-pin D-connector for RS232 serial
communications (e.g. using MiCOM S1 and Courier communications) and the 25-pin
D-connector relay test port for parallel communication. All serial communication is
handled using a two-channel 85C30 serial communications controller (SCC).
The memory provided on the main processor board is split into two categories,
volatile and non-volatile: the volatile memory is fast access (zero wait state) SRAM
which is used for the storage and execution of the processor software, and data
storage as required during the processor’s calculations. The non-volatile memory is
sub-divided into 4 groups:
• 2MB of flash memory for non-volatile storage of software code and text together
with default settings,
• 256kB of battery backed-up SRAM for the storage of disturbance, event, fault and
maintenance record data,
• 32kB of E2PROM memory for the storage of configuration data, including the
present setting values,
• 1.5MB for SRAM software execution.
The co-processor board uses the same type of processor as the main processor
board. The non-volatile memory is contained in a 512 kB SRAM for software
execution.
Communication between the processor boards' CPUs is assured via an FPGA located
on the co-processor board.

2.2 Internal communication buses

The relay has two internal buses for the communication of data between different
modules. The main bus is a parallel link which is part of a 64-way ribbon cable. The
ribbon cable carries the data and address bus signals in addition to control signals
and all power supply lines. Operation of the bus is driven by the main processor
board which operates as a master while all other modules within the relay are slaves.
The second bus is a serial link which is used exclusively for communicating the digital
sample values from the input module to the main processor board. The DSP
processor has a built-in serial port which is used to read the sample data from the
serial bus. The serial bus is also carried on the 64-way ribbon cable.
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2.3 Input module

The input module provides the interface between the relay processor board and the
analogue and digital signals coming into the relay. The input module consists of two
PCBs; the main input board and a transformer board. The P441 and P442 relays
provide three voltage inputs and four current inputs. They also provide an additional
voltage input for the check sync function.
2.3.1 Transformer board
The transformer board holds up to four voltage transformers (VTs) and up to five
current transformers (CTs). The current inputs will accept either 1A or 5A nominal
current (menu and wiring options) and the voltage inputs are 110V nominal voltage.
The transformers are used both to step-down the currents and voltages to levels
appropriate to the relay’s electronic circuitry and to provide effective isolation between
the relay and the power system. The connection arrangements of both the current and
voltage transformer secondaries provide differential input signals to the main input
board to reduce noise.
2.3.2 Input board
The main input board is shown as a block diagram in figure 2. It provides the circuitry
for the digital input signals and the analogue-to-digital conversion for the analogue
signals. Hence it takes the differential analogue signals from the CTs and VTs on the
transformer board(s), converts these to digital samples and transmits the samples to
the processor board via the serial data bus. On the input board the analogue signals
are passed through an anti-alias filter before being multiplexed into a single
analogue-to-digital converter chip. The A-D converter provides 16-bit resolution and
a serial data stream output. The digital input signals are opto isolated on this board
to prevent excessive voltages on these inputs causing damage to the relay's internal
circuitry.
The signal multiplexing arrangement provides for 16 analogue channels to be
sampled. The P440 range of products provides 4 current inputs and either 3 or 4
voltage inputs. 3 spare channels are used to sample 3 different reference voltages
for the purpose of continually checking the operation of the multiplexer and the
accuracy of the A-D converter. The sample rate is maintained at 24 samples per cycle
of the power waveform by a logic control circuit which is driven by the frequency
tracking function on the main processor board. The calibration E2PROM holds the
calibration coefficients which are used by the processor board to correct for any
amplitude or phase errors introduced by the transformers and analogue circuitry.
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Up to 5 current inputs 3/4 voltage inputs

Up to 5
CT

CT

VT

VT
4
Transformer board

Input board

Up to 5
single

single
single

single
Diffn

Diffn

Diffn
Diffn
to

to

to
to

Anti-alias filters
Up to 5
filter
pass

pass

pass

pass
Low

filter

Low

filter

Low

filter

Low
4
16:1
Multiplexer

isolator
Optical
Noise
filter
Buffer
16-bit
ADC

8 digital inputs
Sample
control

8
8
Calibration

interface
E2 PROM

Serial

Optical
isolator
Noise
filter
board
Trigger from processor

Serial sample
data bus
Parallel bus

Buffer

Parallel bus

Figure 2: Main Input Board

The other function of the input board is to read the state of the signals present on the
digital inputs and present this to the parallel data bus for processing. The input board
holds 8 optical isolators for the connection of up to eight digital input signals. The
opto-isolators are used with the digital signals for the same reason as the
transformers with the analogue signals; to isolate the relay’s electronics from the
power system environment. A 48V ‘field voltage’ supply is provided at the back of the
relay for use in driving the digital opto-inputs. The input board provides some
hardware filtering of the digital signals to remove unwanted noise before buffering
the signals for reading on the parallel data bus. Depending on the relay model, more
than 8 digital input signals can be accepted by the relay. This is achieved by the use
of an additional opto-board which contains the same provision for 8 isolated digital
inputs as the main input board, but does not contain any of the circuits for analogue
signals which are provided on the main input board.
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2.4 Power supply module (including output relays)

The power supply module contains two PCBs, one for the power supply unit itself and
the other for the output relays. The power supply board also contains the input and
output hardware for the rear communication port which provides an RS485
communication interface.
2.4.1 Power supply board (including RS485 communication interface)
One of three different configurations of the power supply board can be fitted to the
relay. This will be specified at the time of order and depends on the nature of the
supply voltage that will be connected to the relay. The three options are shown in
table 1 below.

Nominal dc Operative range dc Nominal ac Operative range ac

24-48 V 19 to 65 V - -
48-125 V 37 to 150 V 30-100 Vrms 24 to 100 V
110-250 V 87 to 300 V 100-240 Vrms 80 to 265 V

Table 1: Power supply options

The output from all versions of the power supply module are used to provide isolated
power supply rails to all of the other modules within the relay. Three voltage levels are
used within the relay, 5.1V for all of the digital circuits, ±16V for the analogue
electronics, e.g. on the input board, and 22V for driving the output relay coils. All
power supply voltages including the 0V earth line are distributed around the relay via
the 64-way ribbon cable. One further voltage level is provided by the power supply
board which is the field voltage of 48V. This is brought out to terminals on the back of
the relay so that it can be used to drive the optically isolated digital inputs.
The two other functions provided by the power supply board are the RS485
communications interface and the watchdog contacts for the relay. The RS485
interface is used with the relay’s rear communication port to provide communication
using one of either Courier, Modbus or IEC60870-5-103 protocols. The RS485
hardware supports half-duplex communication and provides optical isolation of the
serial data being transmitted and received. All internal communication of
data from the power supply board is conducted via the output relay board which is
connected to the parallel bus.
The watchdog facility provides two output relay contacts, one normally open and one
normally closed which are driven by the processor board. These are provided to give
an indication that the relay is in a healthy state.
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2.4.2 Output relay board

The output relay board holds seven relays, three with normally open contacts and
four with changeover contacts. The relays are driven from the 22V power supply line.
The relays’ state is written to or read from using the parallel data bus. Depending on
the relay model seven additional output contacts may be provided, through the use of
up to three extra relay boards.

2.5 IRIG-B board (P442 only)

The IRIG-B board is an order option which can be fitted to provide an accurate timing
reference for the relay. This can be used wherever an IRIG-B signal is available. The
IRIG-B signal is connected to the board via a BNC connector on the back of the relay.
The timing information is used to synchronise the relay’s internal real-time clock to an
accuracy of 1ms. The internal clock is then used for the time tagging of the event,
fault maintenance and disturbance records.
The IRIG-B board can also be specified with a fibre optic transmitter/receiver which
can be used for the rear communication port instead of the RS485 electrical
connection (IEC60870 only).

2.6 Mechanical layout

The case materials of the relay are constructed from pre-finished steel which has a
conductive covering of aluminium and zinc. This provides good earthing at all joints
giving a low impedance path to earth which is essential for performance in the
presence of external noise. The boards and modules use a multi-point earthing
strategy to improve the immunity to external noise and minimise the effect of circuit
noise. Ground planes are used on boards to reduce impedance paths and spring
clips are used to ground the module metalwork.
Heavy duty terminal blocks are used at the rear of the relay for the current and
voltage signal connections. Medium duty terminal blocks are used for the digital logic
input signals, the output relay contacts, the power supply and the rear communication
port. A BNC connector is used for the optional IRIG-B signal. 9-pin and 25-pin
female D-connectors are used at the front of the relay for data communication.
Inside the relay the PCBs plug into the connector blocks at the rear, and can be
removed from the front of the relay only. The connector blocks to the relay’s CT inputs
are provided with internal shorting links inside the relay which will automatically short
the current transformer circuits before they are broken when the board is removed.
The front panel consists of a membrane keypad with tactile dome keys, an LCD and
12 LEDs mounted on an aluminium backing plate.
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Section 3. RELAY SOFTWARE

The relay software was introduced in the overview of the relay at the start of this
chapter. The software can be considered to be made up of four sections:
• the real-time operating system
• the system services software
• the platform software
• the protection & control software
This section describes in detail the latter two of these, the platform software and the
protection & control software, which between them control the functional behaviour of
the relay. Figure 3 shows the structure of the relay software.
Protection & Control
Software Measurements and event, fault
& disturbance records
Disturbance
recorder task

Protection
Programmable & task
fixed scheme logic

Platform Software
Fourier signal Protection
Event, fault, Remote
processing algorithms
disturbance, communications
maintenance record interface -
logging IEC60870-5-103
Supervisor task
Protection & control settings

Remote
Settings communications
database interface - Modbus

Sampling function -
copies samples into
2 cycle buffer Control of output contacts and Front panel Local & Remote
programmable LEDs interface - LCD & communications
keypad interface - Courier

Sample data & digital

logic inputs Control of interfaces to keypad, LCD,
LEDs, front & rear comms ports.
Self-checking maintenance records

System services software

Relay hardware

Figure 3: Relay software structure

3.1 Real-time operating system

The software is split into tasks; the real-time operating system is used to schedule the
processing of the tasks to ensure that they are processed in the time available and in
the desired order of priority. The operating system is also responsible in part for
controlling the communication between the software tasks through the use of
operating system messages.

3.2 System services software

As shown in figure 3, the system services software provides the interface between the
relay’s hardware and the higher-level functionality of the platform software and the
protection & control software. For example, the system services software provides
drivers for items such as the LCD display, the keypad and the remote communication
ports, and controls the boot of the processor and downloading of the processor code
into SRAM from non-volatile flash EPROM at power up.
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3.3 Platform software

The platform software has three main functions:
• to control the logging of records that are generated by the protection software,
including alarms and event, fault, and maintenance records.
• to store and maintain a database of all of the relay’s settings in non-volatile
memory.
• to provide the internal interface between the settings database and each of the
relay’s user interfaces, i.e. the front panel interface and the front and rear
communication ports, using whichever communication protocol has been
specified (Courier, Modbus, IEC60870-5-103).
3.3.1 Record logging
The logging function is provided to store all alarms, events, faults and maintenance
records. The records for all of these incidents are logged in battery backed-up SRAM
in order to provide a non-volatile log of what has happened. The relay maintains four
logs: one each for up to 32 alarms, 250 event records, 5 fault records and
5 maintenance records. The logs are maintained such that the oldest record is
overwritten with the newest record. The logging function can be initiated from the
protection software or the platform software is responsible for logging of a
maintenance record in the event of a relay failure. This includes errors that have
been detected by the platform software itself or error that are detected by either the
system services or the protection software function. See also the section on
supervision and diagnostics later in this chapter.
3.3.2 Settings database
The settings database contains all of the settings and data for the relay, including the
protection, disturbance recorder and control & support settings. The settings are
maintained in non-volatile E2PROM memory. The platform software’s management of
the settings database includes the responsibility of ensuring that only one user interface
modifies the settings of the database at any one time. This feature is employed to avoid
conflict between different parts of the software during a setting change. For changes to
protection settings and disturbance recorder settings, the platform software operates a
‘scratchpad’ in SRAM memory. This allows a number of setting changes to be applied to
the protection elements, disturbance recorder and saved in the database in E2PROM.
(See also chapter 1 on the user interface). If a setting change affects the protection &
control task, the database advises it of the new values.
3.3.3 Database interface
The other function of the platform software is to implement the relay’s internal
interface between the database and each of the relay’s user interfaces. The database
of settings and measurements must be accessible from all of the relay’s user
interfaces to allow read and modify operations. The platform software presents the
data in the appropriate format for each user interface.

3.4 Protection and control software

The protection and control software task is responsible for processing all of the
protection elements and measurement functions of the relay. To achieve this it has to
communicate with both the system services software and the platform software as well
as organise its own operations. The protection software has the highest priority of any
of the software tasks in the relay in order to provide the fastest possible protection
response. The protection & control software has a supervisor task which controls the
start-up of the task and deals with the exchange of messages between the task and
the platform software.
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3.4.1 Overview - protection and control scheduling

After initialisation at start-up, the protection and control task is suspended until there
are sufficient samples available for it to process. The acquisition of samples is
controlled by a ‘sampling function’ which is called by the system services software
and takes each set of new samples from the input module and stores them in a two-
cycle buffer. The protection and control software resumes execution when the number
of unprocessed samples in the buffer reaches a certain number. For the P140 feeder
protection relay, the protection task is executed twice per cycle, i.e. after every 12
samples for the sample rate of 24 samples per power cycle used by the relay. The
protection and control software is suspended again when all of its processing on a set
of samples is complete. This allows operations by other software tasks to take place.
3.4.2 Signal processing
The sampling function provides filtering of the digital input signals from the opto-
isolators and frequency tracking of the analogue signals. The digital inputs are
checked against their previous value over a period of half a cycle. Hence a change in
the state of one of the inputs must be maintained over at least half a cycle before it is
registered with the protection and control software.

Figure 4: Signal acquisition and processing

The frequency tracking of the analogue input signals is achieved by a recursive
Fourier algorithm which is applied to one of the input signals, and works by detecting
a change in the measured signal’s phase angle. The calculated value of the
frequency is used to modify the sample rate being used by the input module so as to
achieve a constant sample rate of 24 samples per cycle of the power waveform. The
value of the frequency is also stored for use by the protection and control task.
When the protection and control task is re-started by the sampling function, it
calculates the Fourier components for the analogue signals. The Fourier components
are calculated using a one-cycle, 24-sample Discrete Fourier Transform (DFT). The
DFT is always calculated using the last cycle of samples from the 2-cycle buffer, i.e.
the most recent data is used. The DFT used in this way extracts the power frequency
fundamental component from the signal and produces the magnitude and phase
angle of the fundamental in rectangular component format. The DFT provides an
accurate measurement of the fundamental frequency component, and effective
filtering of harmonic frequencies and noise. This performance is achieved in
conjunction with the relay input module which provides hardware anti-alias filtering to
attenuate frequencies above the half sample rate, and frequency tracking to maintain
a sample rate of 24 samples per cycle. The Fourier components of the input current
and voltage signals are stored in memory so that they can be accessed by all of the
protection elements’ algorithms. The samples from the input module are also used in
an unprocessed form by the disturbance recorder for waveform recording and to
calculate true rms values of current, voltage and power for metering purposes.
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3.4.3 Programmable scheme logic

The purpose of the programmable scheme logic (PSL) is to allow the relay user to
configure an individual protection scheme to suit their own particular application. This
is achieved through the use of programmable logic gates and delay timers.
The input to the PSL is any combination of the status of the digital input signals from
the opto-isolators on the input board, the outputs of the protection elements, e.g.
protection starts and trips, and the outputs of the fixed protection scheme logic. The
fixed scheme logic provides the relay’s standard protection schemes. The PSL itself
consists of software logic gates and timers. The logic gates can be programmed to
perform a range of different logic functions and can accept any number of inputs.
The timers are used either to create a programmable delay, and/or to condition the
logic outputs, e.g. to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front
panel of the relay and the output contacts at the rear.
The execution of the PSL logic is event driven; the logic is processed whenever any of
its inputs change, for example as a result of a change in one of the digital input
signals or a trip output from a protection element. Also, only the part of the PSL logic
that is affected by the particular input change that has occurred is processed. This
reduces the amount of processing time that is used by the PSL. The protection and
control software updates the logic delay timers and checks for a change in the PSL
input signals every time it runs.
This system provides flexibility for the user to create their own scheme logic design.
However, it also means that the PSL can be configured into a very complex system,
and because of this setting of the PSL is implemented through the PC support
package MiCOM S1.
3.4.4 Event and Fault Recording
A change in any digital input signal or protection element output signal causes an
event record to be created. When this happens, the protection and control task sends
a message to the supervisor task to indicate that an event is available to be processed
and writes the event data to a fast buffer in SRAM which is controlled by the
supervisor task. When the supervisor task receives either an event or fault record
message, it instructs the platform software to create the appropriate log in battery
backed-up SRAM. The operation of the record logging to battery backed-up SRAM is
slower than the supervisor’s buffer. This means that the protection software is not
delayed waiting for the records to be logged by the platform software. However, in
the rare case when a large number of records to be logged are created in a short
period of time, it is possible that some will be lost if the supervisor’s buffer is full
before the platform software is able to create a new log in battery backed-up SRAM. If
this occurs then an event is logged to indicate this loss of information.
3.4.5 Disturbance recorder
The disturbance recorder operates as a separate task from the protection and control
task. It can record the waveforms for up to 8 analogue channels and the values of up
to 32 digital signals. The recording time is user selectable up to a maximum of 10
seconds. The disturbance recorder is supplied with data by the protection and control
task once per cycle. The disturbance recorder collates the data that it receives into the
required length disturbance record. It attempts to limit the demands it places on
memory space by saving the analogue data in compressed format whenever possible.
This is done by detecting changes in the analogue input signals and compressing the
recording of the waveform when it is in a steady-state condition. The compressed
disturbance records can be decompressed by MiCOM S1 which can also store the
data in COMTRADE format, thus allowing the use of other packages to view the
recorded data.
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DISTANCE PROTECTION RELAYS Chapter 3
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Section 4. DISTANCE ALGORITHMS

The operation is based on the combined use of two types of algorithms:
• "High-Speed" algorithms using the superimposed current and voltage values that
are characteristic of a fault. These are used for phase selection and directional
determination. The distance calculation is performed by the "measurement
algorithms."
• "Conventional" algorithms using the impedance values measured while the fault
occurs. These are used for phase selection and directional determination.
The distance calculation is performed by the "measurement algorithms."
The "High-Speed" algorithms have priority over the "Conventional" algorithms.
The latter are actuated only if "High-Speed" algorithms have not been able to clear
the fault within two cycles of its detection.

4.1 Distance and Resistance Measurement

To measure the distance and apparent resistance of a fault, the following equation is
solved on the loop with a fault:

Figure 5: Distance and fault resistance estimation

The following describes how to solve the above equation (determination of D fault
distance and R fault resistance). The line model used will be the 3×3 matrix of the
line impedances (resistive and inductive) of the three phases, and mutual values
between phases.
Raa + Daa Rac + Dac Rac + Dac
Rab + Dab Rbb + Dbb Rbc + Dbc
Rac + Dac Rcc + Dbc Rcc + Dcc
Where: Raa=Rbb=Rcc and Rab=Rbc=Rac
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The line model is obtained from the positive and zero-sequence impedance. The use
of two different zero-sequence impedance settings is permitted on the relay, as
follows:
· Z01: zero-sequence impedance used to calculate faults in zone 1.
· Z02: zero-sequence impedance used to calculate faults in zones 2, etc.
The solutions "D" and "R" are obtained by solving the system of equations (one
equation per step of the calculation) using the Gauss Seidel method.
Σ(VL x IF) – DN-1 x Σ(ZL x I x IF) Σ(VL x ZL x I) – RF N-1 x Σ(IF x ZL x I)
RN = DN =
Σ (IF)² Σ (ZL x I)²

Phase-to-earth loop impedance

Zs i ZL X/ Phase R Fault/(1 + K0)

3

ZL
Zs i2 ZL
Z Fault
Zs i1 ZL

R / Phase
V3N V2N V1N RFault
kS ZS V1 V2 V3 kL ZL

Location
of DR
Figure 6: Phase-to-earth loop impedance

The impedance model for the phase-to-earth loop is :

VαN = ZL x D x (Iα + kO x 3 I0) + RF x IF
with α = phase A, B or C
The model for the current IF circulating in the fault is (3I0) during the first 40 ms and
then Iα.
The (3I0) current is used for the first 40 milliseconds to model the fault current, thus
eliminating the load current before the circuit breakers are operated during the 40ms
(one pole tripping). After the 40ms, the phase current is used.
VAN = ZL x D x (IA + kO x 3 I0) + RFault x IF
VBN = ZL x D x (IB + kO x 3 I0) + RFault x IF
VCN = ZL x D x (IC + kO x 3 I0) + RFault x IF
x 4 kO residual compensation factors
= 12 phase-to-earth loops are continuously monitored.
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Phase-to-phase loop impedance

Zs ZL X/ Phase R Fault/2
i3

ZL
Zs i2 ZL
Z Fault
Zs ZL RFault
i1

R / Phase
V3N V2N V1N V3

Location
of DR

Figure 7: Phase-to-phase loop impedance

The impedance model for the phase-to-phase loop is :
Vαβ = ZL x D x Iαβ + RF /2 x IF
with αβ = phase AB, BC or CA
The model for the current W circulating in the fault Iαβ.
VAB = ZL x D x IAB + RFault /2 x IF
VBC = ZL x D x IBC + RFault /2 x IF
VCA = ZL x D x ICA + RFault /2 x IF
= 3 loops phase-to-phase loops are continuously monitored

4.2 "High-Speed" Algorithms

The patented high-speed algorithm has been proven with 10 years of service at all
voltage levels from MV to EHV networks. The P440 relay has ultimate reliability of
phase selection and directional decision far superior to standard distance techniques
using superimposed algorithms. These algorithms or delta algorithms are based on
transient components and they are used for the following functions:
Detection of the fault
By comparing the superimposed values to a threshold which is low enough to be
crossed when a fault occurs and high enough not to be crossed during normal
switching outside of the protected zones.
Establishing the fault direction
Only a fault can generate superimposed values; therefore, it is possible to determine
direction by measuring the transit direction of the superimposed energy.
Phase selection:
As the superimposed values no longer include the load currents, it is possible to make
high-speed phase selection.
4.2.1 Fault Modelling
Consider a stable network status-the steady-state load flow prior to any start. When a
fault occurs, a new network is established. If there is no other modification, the
differences between the two networks (before and after the fault) are caused by the
fault. The network after the fault is equivalent to the sum of the values of the status
before the fault and the values characteristic of the fault. The fault acts as a source
for the latter, and the sources act as passive impedance in this case.
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VR IR
R F

ZS ZL ZL ZR

Relay
VF (prefault voltage)

VR = Voltage at Relay Location

I R = Current at Relay Location

Unfaulted Network (steady state prefault conditions)

V R' IR '
R F

ZS ZL ZL ZR

Relay

RF
VR ' = Voltage at Relay Location

I R ' = Current at Relay Location

Faulted Network (steady state)

VR IR
R F

ZS ZL ZL ZR

Relay

-V F

V R = Voltage at Relay Location

I R = Current at Relay Location RF

Fault Inception

Figure 10: Pre, Fault and Fault Inception Value

The only modifications that occur are caused by the fault, as follows:
The circuit breaker(s) should be closed just prior to fault inception (2 cycles). The
conditions before the fault must be accurately known and must allow extrapolation.
The source characteristics should not change noticeably. This is true for fault
detection times (1/4 cycle) which are very small in relation to the mechanical and
electrical time constants of generators.
When these requirements are fulfilled, the superimposed values are used to
determine the fault inception. The network is then said to be "healthy" before the fault
occurrence.
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Network Status Monitoring

The network status is monitored continuously to determine whether the "High-Speed"
algorithms may be used. To do so, the network must be "healthy," which is
characterised by the following:
• The line is energised from one or both ends.
• All voltages are between 70% and 130% of the nominal value.
• The residual voltage is less than 10% of the nominal value.
• The residual current is less than 10% of the nominal value + 3.3% of the
maximum current flowing on a line.
• A power swing is not taking place on the network.
• The measured loop impedances are outside the characteristic.
• Frequency control has been established.
Note: For the network to be declared "healthy," these conditions must be verified
over the period or at least 500 ms (else, SOTF).

4.2.2 Detecting a Transition

In order to detect a transition, the MiCOM P441-P442 compares sampled current
and voltage values at the instant "t" with the values predicted from those stored in the
memory one period and two periods earlier.

2T
G
G = Current or Voltage

T
G(t)

G(t-2T) G(t-T)
Gp(t)

Time
t-2T t-T t

Figure 9: Transition detection

Gp(t) = 2G(t-T) - G(t-2T) where Gp(t) are the predicted values of either the sampled
current or voltage
A transition is detected on one of the current or voltage input values if the absolute
value of (G(t) - Gp(t)) exceeds a threshold of 0.2 In or 0.1 × Un / √3 = 0.1Vn.
With: U = line-to-line voltage
V = line-to-ground voltage = U / √3
G(t) = G(t) - Gp(t) is the transition value of the reading G.
The high-speed algorithms will be started if ∆U or ∆I is detected on one sample.
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4.2.3 Confirmation
In order to eliminate the transitions generated by possible operations or by high
frequencies, the transition detected over a succession of three sampled values is
confirmed by checking for at least one loop for which the two following conditions are
met:
∆ V > threshold V, where threshold V = 0.1 Un /√3 = 0.1 Vn
and
∆ I > threshold l, where threshold I= 0.2 In.
The start-up of the high-speed algorithms will be confirmed if ∆U and ∆I are detected
on three consecutive sample.
4.2.4 Defining Direction
The "Delta" detection of the fault direction is determined from the sign of the three-
phase energy for the transition values characterising the fault.
VR

IR
F

ZS ZL ZL ZR

Relay

-V F

V R = Voltage at Relay Location

RF
I R = Current at Relay Location

Forward Fault

VR
IR
R

ZS ZL ZL ZR

Relay

-V F

V R = Voltage at Relay Location

RF
I = Current at Relay Location
R

Reverse Fault

Figure 10: Directional determination using superimposed values

To do this, the following sum is calculated:
ni
S= ∑ ( ∆Va
no
i x ∆Iai + ∆Vbi x ∆Ibi + ∆Vc i x ∆Ic i )

where no is the instant at which the fault is detected, ni is the instant of the calculation
and S is the calculated transition energy.
· If the fault is in the forward direction, then S<0.
· If the fault is in the reverse direction, then S>0.
The directional criterion is valid if
S >5 x (0.1 Vn x 0.2 In cos 85°)
This sum is calculated on five successive samples.
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4.2.5 Phase Selection

Phase selection is made on the basis of a comparison between the transition values
for the derivatives of currents Ia, Ib and Ic:
∆I'a, ∆I'b, ∆I'ab, ∆I'bc, ∆I'ca
Note: The derivatives of the currents are used to eliminate the effects of the DC
current component.
Hence:
Sa = Σ (∆I'a)²
Sb = Σ (∆I'b)²
Sc = Σ (∆I'c)²
Sab = Σ (∆I'ab)²
Sbc = Σ (∆I'bc)²
Sca = Σ (∆I'ca)²
The phase selection is valid if the sum (Sab+Sbc+Sca) is higher than a threshold.
This sum is not valid if the positive sequence impedance on the source side is far
higher than the zero sequence impedance. In this case, the conventional algorithms
are used to select the faulted phase(s).
Sums on one-phase and two-phase loops are performed. The relative magnitudes of
these sums determine the faulted phase(s).
For example, assume
Sab<Sbc<Sca
Sa<Sb<Sc
If Sab<<Sbc, the fault has had little effect on the loop A to B. If the fault is not
detected as single-phase by the previous criterion, the fault conditions are multi-
phase, in this case B to C.
Note: If Sab≈Sbc≈Sca and Sa≈Sb≈Sc , the fault is three-phase (the fault occurs on the
three phases).

4.2.6 Summary
A transition is detected if ∆I > 20% In or ∆V >10% Vn
Then three tasks are starting in parallel:
• Fault confirmation : ∆I and ∆V (3 consecutive samples)
• Faulty phase selection (4 consecutive samples)
• Fault directional decision (5 consecutive samples)

Confirmation

Phase selection

Start Directional decision

Figure 11: High-Speed algorithms

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DISTANCE PROTECTION RELAYS Chapter 3
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4.3 "Conventional" Algorithms

These algorithms do not use the superimposed values but use the impedance values
measured under fault conditions. They are based on reactance and resistance
measurements.
They are used in the following circumstances:
• The condition before the fault could not be modelled.
• The superimposed values are not exclusively generated by the fault.
This may be true if the following occurs:
• A breaker closing occurs during a fault.
• The fault is not recent and so the operating conditions of the generators have
changed, or corrective action has been taken, i.e., opening the circuit breakers.
This occurs generally after the first trip.
• operating conditions are not linear.
The conventional algorithms are also suited to detect low current faults that do not
have the required changes in current and voltage for the "high-speed" (superimposed)
algorithms. Therefore, their use assures improved coverage.
The "Conventional" algorithms run continuously with "high-speed" algorithms. If the
"high speed" algorithms cannot declare faulted phase(s) and direction, the
conventional algorithms will.
Note: The distance measurement of the fault is taken on the loop selected by the
"high-speed" or "conventional" phase selection algorithms. This
measurement uses the fault
values.

4.3.1 Convergence Analysis

This analysis is based on the measurements of distance and resistance of the fault.
These measurements are taken on each single-phase and two-phase loops. They
determine the convergence of these loops within a parallelogram-shaped, start-up
characteristic.
D

L = line length in km or miles

D3 = Z3/Zd x L
D4 = Zd x L Dlim = X3

For multi phase fault :

 = argument of Z1(positive sequence impedance)
For single phase fault :

  argument of (2Z 1 + Z01)/3

1
for zone 1 d
1  argument of (2Z 1 + Z02)/3
-R R R
for zone 2, etc... lim lim

-D = X4
lim

Figure 12: Start-up characteristic

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Let Rlim and Dlim be the limits of the starting characteristic.

The pair of solutions (DN-1, RN-1) and (DN, RN):
• RN-1< Rlim, and RN< Rlim, and RN-1 - RN< 10% Rlim
• DN-1< Dlim and DN < Dlim and DN-1 - DN < 10% Dlim
with Rlim being the resistance limit for the single and multi phase faults. This
convergence is dependent on the equations not being collinear thus allowing the
terms in D and R to be discriminated.
The zone limits are +Dlim = Z3 D, -Dlim = Z4 D, + Rlim, and - Rlim. The slope of
the characteristic mimics the characteristic of the line.
To model the fault current:
• Two-phase loops: the values (Ia - Ib), (Ib - Ic), or (Ic - Ia) are used.
• Single-phase loops: The results of these algorithms are mainly used as a backup;
therefore, the circuit breaker located at the other end is assumed to be open.
To model the fault current, the values Ia, Ib and Ic are used.
4.3.2 Start-Up
Start-up is initiated when at least one of the six measuring loops converges within the
characteristic.
4.3.3 Phase Selection
If the fault currents are high enough with respect to the maximum load currents
current-based phase selection is used; if not, impedance-based phase selection is
required.
Current Phase Selection
Amplitudes I'a, I'b, I'c are derived from the measured three-phase currents Ia, Ib, Ic.
These values are then compared to each other and to the two thresholds S1 and S2:
• First threshold is SI= 3I'n
• Second threshold is S2 = 5I'n
Example:
If I'a< I'b < I'c:
If I'c > S2 and I'a > SI, the fault is three-phase.
If I'c> S2, I'b > S1 and I'a < S1, the fault is two-phase, on phases B and C.
If I'c> S2 and I'b< S1, the fault is single-phase, on phase C.
If I'c< S2, the current phase selection cannot be used. Impedance phase selection
should then be used.
Impedance Phase Selection
Impedance phase selection is obtained by checking the convergence of the various
measuring loops within the start-up characteristic, as follows:
·T = Presence of zero-sequence voltage or current.
· Za = Convergence within the characteristic of the loop A.
· Zb = Convergence within the characteristic of the loop B.
· Zc = Convergence within the characteristic of the loop C.
· Zab = Convergence within the characteristic of the loop AB.
· Zbc = Convergence within the characteristic of the loop BC.
· Zca = Convergence within the characteristic of the loop CA.
In addition, the following are also defined:
· Ra = Za x Zbc with Zbc = convergence within the characteristic of the loop BC.
· Rb = Zb x Zca with Zca = convergence within the characteristic of the loop CA.
· Rc = Zc x Zab with Zab = convergence within the characteristic of the loop AB.
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· Rab = Zab x Zc with Zc = convergence within the characteristic of the loop C.

· Rbc = Zbc x Za with Za = convergence within the characteristic of the loop A.
· Rca = Zca x Zb with Zb= convergence within the characteristic of the loop B.
Following are the different phase selections:
· Sa = T x Ra x Rb x Rc single-phase A to ground fault
· Sb = T x Rb x Ra x Rc single-phase B to ground fault
· Sc = T x Rc x Rb x Rc single-phase C to ground fault
· Sab = T x Rab x Za x Zb double-phase A to B to ground fault
· Sbc = T x Rbc x Zb x Zc double-phase B to C to ground fault
· Sca = T x Rca x Za x Zc double-phase C to A to ground fault
· Sab = T x Rab x Rbc x Rca double-phase A to B fault
· Sbc = T x Rbc x Rab x Rca double-phase B to C fault
· Sca = T x Rca x Rab x Rbc double-phase B to C fault
· Sabc = Za x Zb x Zc x Zab x Zbc x Zca three-phase fault
For a three-phase fault, the fault resistance of one of the two-phase loops is less than
half of the fault resistances of the other two-phase loops, it will be used for the
directional and distance measuring function. If not, the loop AB will be used.
Note: Impedance phase selection is used only if current phase selection is
unable to make a decision.
4.3.4 Directional Decision
The fault direction is defined on the basis of the calculation of the phase shift between
the stored voltage and the derivative of a current. The current and the voltage used
are those of the measuring loop(s) defined by the phase selection.
For the two-phase loops, the calculation of the phase shift between the stored voltage
and the derivative of the current on the faulty two-phases.
For the single-phase loops, the calculation of the phase shift between the stored
voltage and the current (I'x + K0I'r),
where:
I'x = derivative of current on the faulted single-phase where x = A, B, or C
Ir = residual current = 3 I0
K0 = ground compensation factor, where for example K01 = (Z0–Z1)/3Z1
The directional angle is fixed - 30° , + 150°.
4.3.5 Directional Decision during SOTF/TOR (Switch On To Fault/Trip On Reclose)
The directional information is calculated from the stored voltage values. The
calculations vary depending on the type of fault, i.e., single-phase or multiphase.
Single-phase fault
The reference voltage is stored in memory when the fault appears. When the fault is
eliminated by single-phase tripping, the high-speed single-phase auto-reclose (AR) is
started.
If a fault appears less than three cycles after the AR starts, the stored voltage value
remains valid as the reference and is used to calculate direction.
If no fault appears during the three cycles after the AR starts, the reference voltage
value becomes that of one of the healthy phases.
If a fault appears during the continuation of the AR cycle or reclosure occurs, the
stored voltage value remains valid for 10 seconds.
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If a stored voltage does not exist (SOTF) when one or more loops are convergent
within the start-up characteristic, the directional is forced forward and the trip is
instantaneous. If the settable switch on to fault current threshold I>3 is exceeded on
reclosure, the relay instantaneously trips three-phase.
Two-phase or three-phase fault
The reference voltage is stored in memory when the fault appears. When the fault is
cleared, the stored voltage value remains valid for 10 seconds. If reclosure occurs
during these 10 seconds, the direction is calculated using the stored voltage value.
If a stored voltage does not exist when one or more loops are convergent within the
start-up characteristic, the forward direction is forced and the trip is instantaneous
when protection starts. If the switch on to fault current threshold I>3 is exceeded on
reclosure, the relay trips instantaneously three-phase.
The distance element trips immediately as soon as one or more loops converge within
the start-up characteristic during SOTF.

4.4 Faulted Zone Decision

The Decision of the faulted zone is determined by either the zone "High-Speed" or
"Conventional" algorithms.
The zones are defined for a convergence between the X and R limits related to each
zone. So, the solution pair (Rn, Xn) is said to be convergent if:
• Rn-1 < Ri and Rn < Ri and |Rn-1 - Rn| < 10% x Ri
• Xn-1 < Xi and Xn < Xi and |Xn-1 - Xn| < k% x Xi
where k= 5% for zone 1 and 10% for other zones
and i=1, 1X, 2, p, 3 and 4.

Z1

2 1 0
3
4..
R

Figure 13: Phase-to-earth loop impedance

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4.5 Tripping Logic

Three tripping modes can be selected:
One-pole trip at T1: Single-phase trip for Z1 at T1 and Pilot Aided trip at T1. All
other zones trip three-phase at their respective times for any fault types (∅-G, ∅-∅,
∅-∅-G, ∅-∅-∅, ∅-∅-∅-G).
One-pole trip at T1 and T2: Single-phase trip for Z1 at T1, Pilot Aided trip at T1,
and Z2 at T2. All other zones trip three-phase at their respective times for
any fault types (∅-G, ∅-∅, ∅-∅-G, ∅-∅-∅, ∅-∅-∅-G).
Three- pole trip for all zones: Three-phase trip for all zones at their respective times
for any fault types (∅-G, ∅-∅, ∅-∅-G, ∅-∅-∅, ∅-∅-∅-G). Pilot aided
trips will be three-phase with times corresponding to the pilot logic applied.

Zone Time
Z1 T1
Z1X T1
Z2 T2
Zp Tp
Z3 T3
Z4 T4
There are five time delays associated with the six zones present. Zone 1 and
extended zone 1 have the same time delay.

4.6 Fault Locator

The fault locator measures the distance by applying the same distance calculation
principle as that used for the fault-clearing, distance-measurement algorithm.
However, the dedicated fault locator measurement is more accurate as it is based on
a greater number of samples, and it uses the fault currents as models, as shown
below:
For a single-phase fault AN : ∆ (Ia–I0)
BN : ∆ (Ib–I0)
CN : ∆ (Ic–I0)
For a two-phase fault AB : ∆ (Ia–Ib)
BC : ∆ (Ib–Ic)
CA : ∆ (Ic–Ia)
For a three-phase fault ABC : ∆ (Ia–Ib)
The calculation is based on the following equation:
· V = D × Vd + R × If, where x = distance of fault
· If = Fault current image
· Vd = Voltage drop on line per unit length
Phase-to-earth loop impedance
U = Z1.(I + K0.Ir) + Zm.Im + R.W with W= ∆I – I0
Phase-to-phase loop impedance
U = Z1.(I + K0.Ir) + Zm.Im + R.W with W= ∆I (∆I = ∆I' - ∆I")
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4.6.1 Selecting the fault location data

Selection of the analogue data that is used depends on
• How the fault is processed by the algorithms.
• The line model.
4.6.2 Processing algorithms
Distance to fault calculation will use the high speed algorithms if
• A fault is detected by the high-speed algorithms
• The tripping occurred within the T1 or T2 time delays
• The distance to the fault is less than 105% of the line.
In this case, the distance to fault saved in the fault report will be displayed as:
Distance to the fault = 24.48 km (L) accuracy 3%
If all three of these conditions are not met, the distance to fault value will be the same
value used by the distance protection. The format of the display will then be as
follows:
Distance to the fault = 31.02 km accuracy 5%
Note: The more accurate fault location will be post scripted with an (L). This will
occur when conditions are favourable for using the more accurate algorithm
for distance to fault calculation.
4.6.2.1 Line Model Selection
The fault locator can distinguish between two types of line, as follows:
• · Single lines.
• · Parallel lines with mutual coupling.
Mutual coupling between transmission lines is common on power systems. Significant
effects on distance relay operation during faults involving ground may occur.
Typically, the positive and negative, mutual-sequence impedances are negligible, but
zero-sequence mutual coupling may be large, and either must be factored onto the
settings, or accommodated by measurement of parallel, mutually-coupled lines
residual (ground) current, where zero-sequence current information is available. The
value of the residual currents from parallel lines is then integrated into the distance
measurement equation.
The relay is capable of measuring and using mutually coupled residual current
information from parallel lines. The mutual current is measured by a dedicated
analogue input.

4.7 Power swing detection

Power swings are caused by a lack of stability in the network with sudden load
fluctuations. A power swing may cause the two sources connected by the protected
line to go out of step (loose synchronism) with each other.
The power swing detection element may be used to selectively prevent when the
measured impedance point moves into the start-up characteristic from a power swing
and still allows tripping for a fault (fault evolving during a power swing). The power
swing detection element may also be used to selectively trip once an out-of-step
condition has been declared.
Figure 15 illustrates the characteristics of power swing.
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Powerswing Z3
Boundary Stable R
Characteristic Unstable
Swing Swing

Z4

Figure 15: Power swing

4.7.1 Power swing detection

The power swing detection element is used to detect a power swing or loss of
synchronism condition as it passes through near the loop convergence (start-up)
characteristic (Z3 and Z4). Power swing detection is based on the status of the line to
be protected:
Power swings are characterised by the simultaneous appearance of three impedance
points in the start-up zone, passing through the power swing band .Their speed of
entry (passing through the resistance limits that define the power swing detector) is
slower than that in the case of three-phase faults, which is instantaneous.
A power swing is detected and declared if:
• At least one single-phase impedance is within the start-up zone after having
crossed the power swing band in more than 5 ms.
• The three impedance points have been in the power swing band for more than 5
ms.
• At least two poles of the breaker are closed (impedance measurement possible on
two phases).
4.7.2 Line in one pole open condition (during single-pole trip)
In this case, the power swing only occurs on two phases. A power swing is detected
if:
• At least one single-phase impedance is within the start-up zone after having
crossed the power swing band in more than 5ms.
• The two impedance points have been in the power swing band for more than 5
ms.
Note: During an open-pole condition, the P440 monitors the power swing on two
single-phase loops. No external information is needed if the voltage
transformers are on the line side. If the voltage transformers are on the
bus side, the “pole discrepancy” signal should be used. The “pole
discrepancy” input represents a “one-circuit-breaker-pole-open” condition.
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4.7.3 Conditions for isolating lines

If there is a power swing, it may be necessary to trip and disconnect the two out-of-
step sources. There are various tripping and blocking options available that are used
to select if the line is tripped for power swings or not.
The selective blocking of remote zones allows the P440 to separate the network near
the electrical zero by tripping zone 1 only. Therefore, in the example given in figure
16, the relay D trips out.
Electrical Zero

A B C D E F

Relay set for out-of-step tripping, zone 1.

Figure 16: Selective Protection Blocking

4.7.4 Tripping logic

Depending on the blocking or unblocking selected, the P440 will trip or block as the
swing passes through the zones.
Note: If selected, tripping will occur if the impedance stays in any zone longer than
its time delay.
There is a master unblocking timer that is used to override any blocked zone
(unblocking time delay). This is used to separate the sources (open the breaker, 3-
phase trip) in the event that a block was taking place, and the impedance remained
in the blocked zone for a relatively long time. This would be indicative of a serious
overcurrent condition as a result of too great a power transfer after a disturbance (a
power swing that does not pass through or recover). If the impedance point moves
out of the start-up characteristic again before the time delay expires, a trip is not
issued and the adjustable time delay is reset.
Unblocking the Zones Blocked due to Faults
In order to protect the network against a fault that may occur during power swing,
blocking signals can be stopped when current thresholds are exceeded. The
adjustable unblocking current thresholds are
A residual current threshold equal to 0.1 In + (kr x Imax(t)).
A negative-sequence current threshold equal to 0.1 In + (ki x Imax(t)).
A phase current threshold: IMAX.
Where:
kr = an adjustable coefficient for residual current
ki: = an adjustable coefficient for negative sequence current
Imax: maximum current detected on one phase
In: nominal current
4.7.5 Fault Detection after Single-phase Tripping (one-pole-open condition)
After a circuit breaker pole has opened, there is no current and voltage on the
applicable phase, which allows the protection unit to detect whether a one-pole cycle
of the voltage transformer are on a line side.
The reception of “poles discrepancy” input signal allows the protection unit to detect
one-pole-open condition blocking if the voltage transformer is on the bus side.
If another fault appears during a one-pole cycle or just after the voltage has been
restored on the applicable phase, direction is defined and phase selection performed.
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4.8 Double Circuit Lines

Double circuit lines must be taken into account in the operating principle of the
protection scheme to avoid unwanted tripping of “sound” phases, which could be the
result of an excessively general phase selection.
Phase selection for an inter-circuit fault
During a two-phase fault selection, for example on loop AB, the P440 checks
direction on the two adjacent ground loops, (Aneutral and Bneutral). The direction is
determined using either the conventional algorithm or the high-speed algorithm
(using superimposed quantities), depending on fault severity. If superimposed
components are used, the transient (fault) energy is summated phase by phase.
S a = ∑ (∆V a × ∆I a ) and Sb = ∑ (∆Vb × ∆I b )
The directions of the two adjacent ground loops are compared, as follows:
• If the two directions are forward, the fault is a two-phase fault on the protected
line.
• If only one of the directions is forward, for instance Sa, the fault is single-phase
(A to Neutral) on the protected line.
• If the two directions are reverse, the fault is not on the protected line.
Protection against Current Reversal (Transient Blocking)
When a fault occurs on a line, which is parallel to the protected line, the pilot
schemes on the protected line may be subjected current reversals from sequential
clearing on the parallel line. A fault on the parallel line may start by appearing
external to the protected line in the reverse direction, and then, after a sequential
operation of one of the parallel line breakers, the fault appears forward. This
situation can affect security of certain pilot schemes on the protected line.

Figure 17: Direction Reversal from Sequential Clearing of Parallel Lines

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The P440 provides protection against the effects of this phenomenon by employing
transient blocking. An adjustable timer is available that will block direct and
permissive transfer trip signals from being used in the P440 logic, and will also block
the P440 from sending direct or permissive transfer trip signals. This timer is
designated as “Reverse Guard Timer”.
This provides protection against fault current reversal and will still allow fast tripping
in the event of faults occurring in zone 1, if zone 1 is independent (not used as
overreach zone).

4.9 DEF Protection Against High Resistance Ground Faults

Protection against high-resistance ground faults, also called DEF (Directional Earth
Fault), is used to protect the network against highly resistive faults. High resistance
faults may not be detected by distance protection. DEF Protection can be applied in
one of the two following modes: faults using the following:
• The main operating mode, directional comparison protection uses the signalling
channel and is a communication-aided scheme.
• In backup-operating mode SBEF (Stand-By Earth Fault), an inverse/definite time
ground overcurrent element with 2 stages is selectable. A communication channel
is not used.
Both the main and backup mode use the same method for fault detection and
directional determination.
The use of Aided-Trip logic in conjunction with the DEF element allows faster trip
times, and can facilitate single-phase tripping if single-phase tripping is applied to the
breaker.
The DEF directional comparison protection may be applied on the same signal
channel as the distance protection, or it may be applied on an independent channel.
When used on the same signalling channel as the distance protection, if the distance
protection picks up, it has priority (the output from the DEF element is blocked from
asserting the Carrier Send common output).
The use of directional comparison protection with an independent signalling channel
allows the distance functions and DEF function to operate in parallel. Each function is
routed to its own Carrier Send output. If a ground fault is present where both the
distance and DEF elements pick up, the faster of the two functions will perform the
trip.
4.9.1 High Resistance Ground Fault Detection
A high resistance fault is detected when residual voltage and current thresholds are
exceeded:
• ∆Ι ≥ 0.05 In
• ∆ V ≥ 0.1 Vn (L-G)
A fault is confirmed if these thresholds are exceeded for 1 ½ cycles
4.9.2 Directional determination
The fault direction is determined by measuring the angle between the residual voltage
and the residual current derivative. The fault is forward if the angle is between –14°
and +166°. A negative or zero sequence polarisation is selectable in order to
determinate the earth fault direction.
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4.9.3 Phase selection

The phase is selected in the same way as for distance protection except that the
current threshold is reduced.
Note: If the phase has not been selected within one cycle, a three-phase selection
is made automatically.
4.9.4 Tripping Logic
Legend For Tripping Logic Diagrams (DEF)
Abbreviation Definition
Vr> Threshold of residual voltage (3Vo)
Ir_Forv> Threshold of residual current for forward fault
Forward Forward directional with zero/negative sequence
polarisation
Reverse Reverse directional with zero/negative sequence
polarisation
DEF blocking Blocking of DEF element
Carrier Receive DEF Carrier received for the principal line protected (same
channel as distance protection)
Ir_Rev Threshold of residual current for reverse fault (0.6 Ir_Forv)
Tripping mode Single or three-phase tripping (selectable)
Z< starting Convergence at least 1 of 6 loops within the tripping
characteristic (internal starting of the distance element)
Transmission Time Transmission time delay for blocking scheme
t_cycle Additional time delay (150ms) of 1 pole AR cycle

Vr>threshold
Ir fwd threshold
Forward decision & DEF Carrier Send
(DIST if shared
Reverse decision
DEF Timer Block channel)

DEF permissive signal receive &

or (DIST if shcared channel) & Single Phase Trip

Ir rev threshold
&

1 pole dead
0
 T & Three Phase Trip
Z< starting
& t-AR cycle

Independant channels DIST/DEF

Single phase selection

Force 3-pole trip


Multy-phase selection

Figure 18: Directional Comparison Protection Permissive Scheme

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& DEF Carrier Send

(or DIST if shared
channel)

Vr>threshold
Ir fwd threshold 0
Forward decision &
Reverse decision t
DEF Timer Block Transmission
time

DEF blocking signal receiv

&
(or DIST if shared channel)

Ir rev threshold
& Single Phase Trip
&

1 pole dead
0
 T & Three Phase Trip
Z< starting
& t-AR cycle

Independant channels DIST/DEF

Single phase selection

Force 3-pole trip


Multy-phase selection

Figure 19: Directional comparison protection blocking scheme

If the DEF directional comparison transmission is selected on the same channel that is
used to transmit distance teleprotection messages, the DEF will have the same
tripping logic as the main protection (permissive or blocking).
4.9.5 SBEF – Stand-By earth fault (not communication-aided)
This protection trips the local breaker directly, without a teleprotection signal, if a high
resistance fault remains after a time delay. The time delay varies inversely with the
value of the fault current. The selectable inverse time curves comply with the ANSI
and IEC standards (see Appendix).
This protection three-pole trips and can block autoreclosing.

CTS Block
&
IN>x start
& SBEF

Slow VTS
Block
& Directional
Check
Vx > Vs & IDMT/DT Trip
Ix > Is

SBEF Timer Block

 FAULTY PHASE (S)
Algorithms AN BN CN AB/ABN BC/BCN CA/CAN ABC/ABCN
High-Speed startup ∆Ia>0.2In or ∆Ib>0.2In or ∆Ic>0.2In or ∆Iab>0.2In or ∆Ibc>0.2In or ∆Ica>0.2In or ∆Iabc>0.2In or
∆Va>0.1Vn ∆Vb>0.1Vn ∆Vc>0.1Vn ∆Vab>0.1Vn ∆Vbc>0.1Vn ∆Vca>0.1Vn ∆Vabc>0.1Vn
Conventional startup Startup is initialized when at least one of the 6 measuring loops converges within the characteristic.
TECHNICAL GUIDE

High-Speed Sbc < Sca < Sab Sca<Sbc < Sab Sab<Sbc<Sca Sbc<Sac<Sab Sac<Sab<Sbc Sab<Sbc<Sca
MiCOM P441 & P442

Sab ≈ Sbc ≈ Sca

algorithm phase Sbc << Sca Sca << Sbc Sab<<Sbc Sbc ≈ Sac Sac ≈ Sab Sab ≈ Sbc Sa ≈ Sb ≈ Sc
selection c
Sc < S b < S a Sa < C < Sb Sa<Sb<Sc Sc <Sb<Sa Sa<Sb<Sc Sb<Sc<Sa
Conventional T x Ra x Rb x Rc T x Rb x Rc x Ra T x Rc x Ra x Rb T x Rab x Za x Zbor T x Rbc x Zb x Zcor T x Rca x Za x Zcor Za x Zb x Zc x Zab
DISTANCE PROTECTION RELAYS

algorithm phase T x Rab x Rbc x Rca T x Rbc x Rab x Rca T x Rca x Rab x Rbc x Zbc x Zca
selection
High-speed algorithm ni

direction S= ∑ (∆V a × ∆I a ) + (∆Vb × ∆Ib ) + (∆Vc × ∆I c )

n0
determination
Conventional Va Vb Vc Va - Vb Vb - Vc Vc - V a Va - Vb
Quantities used by the different algorithms

algorithm directional
determination
I’a + K0I’r I’b + k0’r I’c + k0I’r I’a - I’b I’b - I’c I’c - I’a I’a - I’b
Supervision algorithm U = Va U = Vb U = Vc U = Va - Vb U = Vb - Vc U = Vc - Va U = Va - Vb
V = M2Ia V= M2Ib V = M2Ic V = M x (Ia - Ib) V = M x (Ib - Ic) V = M x (Ic - Ia) V = M x (Ia - Ib)
W = Ia W = Ib W = Ic W = Ia - Ib W = Ib - Ic W = Ic - Ia W = Ia - Ib
Measurement U = Va U = Vb U = Vb U = Va - Vb U = Vb - Vc U = Vc - Va U = Va - Vb
algorithm for zone 1 V = M1Ia V = M1Ib V = M1Ic V = M x (Ia - Ib) V = M x (Ib - Ic) V = M x (Ic - Ia) V = M x (Ia - Ib)
W = Ir W = Ir W = Ir W= Ia - Ib W = Ib - Ic W = Ic - Ia W = Ia - Ib
Measurement U = Va U = Vb U = Vb U = Va - Vb U = Vb - Vc U = Vc - Va U = Va - Vb
algorithm for zones V = M2Ia V = M2Ib V = M2Ic V = M x (Ia - Ib) V = M x (Ib - Ic) V = M x (Ic - Ia) V = M x (Ia - Ib)
2, p, 3 and 4
W = Ir W = Ir W = Ir W = Ia - Ib W = Ia - Ib W = Ic - Ia W = Ia - Ib
M: impedance for multi-phase faults
Volume 1
TG 1.1671

Page 32 of 34
Chapter 3
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DISTANCE PROTECTION RELAYS Chapter 3
Page 33 of 34

Section 5. SELF TESTING & DIAGNOSTICS

The relay includes a number of self-monitoring functions to check the operation of its
hardware and software when it is in service. These are included so that if an error or
fault occurs within the relay’s hardware or software, the relay is able to detect and
report the problem and attempt to resolve it by performing a re-boot. This involves
the relay being out of service for a short period of time which is indicated by the
‘Healthy’ LED on the front of the relay being extinguished and the watchdog contact
at the rear operating. If the restart fails to resolve the problem, then the relay will take
itself permanently out of service. Again this will be indicated by the LED and watchdog
contact.
If a problem is detected by the self-monitoring functions, the relay attempts to store a
maintenance record in battery backed-up SRAM to allow the nature of the problem to
be notified to the user.
The self-monitoring is implemented in two stages: firstly a thorough diagnostic check
which is performed when the relay is booted-up, e.g. at power-on, and secondly a
continuous self-checking operation which checks the operation of the relay’s critical
functions whilst it is in service.

5.1 Start-up self-testing

The self-testing which is carried out when the relay is started takes a few seconds to
complete, during which time the relay’s protection is unavailable. This is signalled by
the ‘Healthy’ LED on the front of the relay which will illuminate when the relay has
passed all of the tests and entered operation. If the testing detects a problem, the
relay will remain out of service until it is manually restored to working order.
The operations that are performed at start-up are as follows:
5.1.1 System boot
The integrity of the flash EPROM memory is verified using a checksum before the
program code and data stored in it is copied into SRAM to be used for execution by
the processor. When the copy has been completed the data then held in SRAM is
compared to that in the flash EPROM to ensure that the two are the same and that no
errors have occurred in the transfer of data from flash EPROM to SRAM. The entry
point of the software code in SRAM is then called which is the relay initialisation code.
5.1.2 Initialisation software
The initialisation process includes the operations of initialising the processor registers
and interrupts, starting the watchdog timers (used by the hardware to determine
whether the software is still running), starting the real-time operating system and
creating and starting the supervisor task. In the course of the initialisation process the
relay checks:
• the status of the battery.
• the integrity of the battery backed-up SRAM that is used to store event, fault and
disturbance records.
• the voltage level of the field voltage supply which is used to drive the opto-isolated
inputs.
• the operation of the LCD controller.
• the watchdog operation.
At the conclusion of the initialisation software the supervisor task begins the process
of starting the platform software.
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Page 34 of 34

5.1.3 Platform software initialisation & monitoring

In starting the platform software, the relay checks the integrity of the data held in
E2PROM with a checksum, the operation of the real-time clock, and the IRIG-B board
if fitted. The final test that is made concerns the input and output of data; the
presence and healthy condition of the input board is checked and the analogue data
acquisition system is checked through sampling the reference voltage.
At the successful conclusion of all of these tests the relay is entered into service and
the protection started-up.

5.2 Continuous self-testing

When the relay is in service, it continually checks the operation of the critical parts of
its hardware and software. The checking is carried out by the system services software
(see section on relay software earlier in this chapter) and the results reported to the
platform software. The functions that are checked are as follows:
• the flash EPROM containing all program code and language text is verified by a
checksum.
• the code and constant data held in SRAM is checked against the corresponding
data in flash EPROM to check for data corruption.
• the SRAM containing all data other than the code and constant data is verified
with a checksum.
• the E2PROM containing setting values is verified by a checksum.
• the battery status.
• the level of the field voltage.
• the integrity of the digital signal I/O data from the opto-isolated inputs and the
relay contacts is checked by the data acquisition function every time it is executed.
The operation of the analogue data acquisition system is continuously checked by
the acquisition function every time it is executed, by means of sampling the
reference voltages.
• the operation of the IRIG-B board is checked, where it is fitted, by the software
that reads the time and date from the board.
In the unlikely event that one of the checks detects an error within the relay’s
subsystems, the platform software is notified and it will attempt to log a maintenance
record in battery backed-up SRAM. If the problem is with the battery status or the
IRIG-B board, the relay will continue in operation. However, for problems detected in
any other area the relay will initiate a shutdown and re-boot. This will result in a
period of up to 5 seconds when the protection is unavailable, but the complete restart
of the relay including all initialisations should clear most problems that could occur.
As described above, an integral part of the start-up procedure is a thorough
diagnostic self-check. If this detects the same problem that caused the relay to restart,
i.e. the restart has not cleared the problem, then the relay will take itself permanently
out of service. This is indicated by the ‘Healthy’ LED on the front of the relay, which
will extinguish, and the watchdog contact which will operate.