al, Industrial, and Exten Perip 3of 9 X

Low-power consumption:
<2 mA@ SV, 4MHz
15mA typical @ 3V, 32
kHz

<ImA typical standby current

hat are the PICI6C6X Microcontroller Peripheral Features

D TimerO: 8-bit timer/counter with 8-bit prescaler

D Timerl: 16-bit timer/counter with prescale, can be incremented during sleep via
external crystal/clock
C Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
O Capture/Compare/PWM (CCP) module(s)
D Capture is 16-bit, max resolution is 12.5 ns, Compare is l6-bit, max resolution is
200 ns.PWM max resolution is 10-bit.
D Synchronous Serial Port (SSP) with SPl and IC
O Universal Synchronous Asynchronous ReceiverTransmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls.
E Brown-out detection circuitry for Brown-out Reset (BOR)

4.What are the PIC 16c6x family device?

devicetypesl as indicated in the
For the PIC16C6X family of devices, there are four
device number:
standard
y and operate over the
1. C,as in PIC16Có Page 2 / 33
voltage Tange.
 Google Classwork X 2.1 Modul X Two mark

5 drive.google.com/file/d/1t-vU7rvwLQbl_S1Encf1 QPe3XCij5...

Two mark quest ... reference.pdf Open B Share

Global interrupt enable bit, GE INTCO
GIE cleared) all interrupts. When bit GI! Watchdog 3 of 6
1

interrupt will vector immediately. lndividual interrupts can be disabled through their
corresponding
enable bits in the INTCON register. GIE is clearcd on resct.
3. What is WATCH DOG TIMER (WDT):
The Watchdog Timer is a tree running on-chip RC oscillator which does
not require any external
components. This RC oscillatoris separate from the RC oscillator of the OSC1/CLKIN pin,. That
means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the
device has been stopped, for example, by exccution of aSLEEP instruction. During normal operation,
a WDT time-out generates a device reset. If the device is in SLEEP mode, a WDT
time-out causes the
device to wake-up and continue with nOFmal operation. The
WDT can be permanently disabled by
clearing configuration bit WDTE.

4.Write the WATCH DOG TIMER REGISTER

Address Name Bit 7 Bit 6 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1

2007h Config. bits (1) BODEN() CP1 CPO PWRTE1)| WDTE FOSC1 FOSCO
81h,181hOPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO

5.Write the interrupts Whiah from SLEEP.

The following peripheral Page 7 / 33
4.Write the WATCH D0G TIMER
REGISTER
Addross Namo Bit 7 Bit 6 Bit 5 Bit4 Bn3
2007h Bh 2 BIt1
Config. bits (1)
BODEN1) CP1 CPO
Bit 0
81h,181h OPTION PWRTEI) WDTE FOSC1 FOSCO
RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO

5.Write the interrupts Which wvake up the

peripheral interrupts from SLEEP.
The following peripheral interrupts can wake the
1. TMR1 interTupt. Timerl must be device from SLEEP:
2. SSP (Start/Stop)bit detect interrupt.operating as an asynchronous counter.
3.SSP transmit or receive in slave mode (SPII2C).
4. CCP capture mode interrupt.
5.Parallel Slave Port read or wIite.
6. USART TX or RX (synchronous slave mode).
6.What is TIMER 0?
The Timer0 module is a simple 8-bit overflow counter.
The clock source can be either the internal system clock or an external
clock
When the clock source is an external clock, the Timer) module can be selected to increment on
either the rising or falling edge.
The Timer0 module also has a programmable prescaler option.
This prescaler can be assigned to either the Timer)module or the Watchdog Timer.
Bit PSA (OPTION) assigns the prescaler, and bits PS2 PSO (OPTION) determine the prescaler
value.
TMRO can increment at the following rates. 1:1
when the prescaler is assigned to Watchdog Timer, 1:2, 1:4, 1:8, 1:16, 132, 1:64, 1:128, and
1256. Synchronization of the external clock occurs after the prescaler.
When theprescaler is uscd,the external clock frequency may be higher then the device's frequcney.
The maximum frequery IS30 MHz gIven tn nign tng to requirements of the clock
Page 8 33
 Org0 synchorn Oof O
BcfSTATUS.RPO X
clrf PORTA
bsf STATUS.RPO
movlw 0010000H
movwf TRISA. End

15. What is the status ot ADON?

When ADON=0 then AD is off, when ADON=| then AD is
turned ON..
16. What are the bit postions of
ADCON?
DO-ADON,D1-ADIF D2-Go/Done D3-CHSO,D4-CHS1,D5-undefined,D6
ADSCO,D7-ADSC1.
17. Explain about UART?
Universal asynchronous receiver transmitter. UART IS useful for
transmission of datas in asynchoronous mode. receiving and

18. What is
svnchronous and asynchronous transnmission.
Asynchronous start and stop bit allowed for transmission of data
Synchronous no start and stop bit only block hcader data
19.What is baud rate in asynchronous mode?
The baud rate in asynchoronous mode is given by B.R
speed,and Fosc/l6(x+1) for high speed. Fosc/64.(x+1) for low
20. How do you configure the ports as input and
output?

Any ports can be made as input by setting the port bits and they can be set as output
by resctting the pg
Page 13 |33 /
 12C. 7of 13
X

Anyports can be made as

by rescting the port input by setting the port bits and
bits. they can be set as output

21. How USART can be

The Universal configured?
Synchronous
one of the twoserial VO Asynchronous Receiver Transmitter (USART) module is
modules.
Interface SCI). The USART can be
or USART is also known as a Serial
(full duplex) configured as Communications
II. Asynchronous
IIL Synchronous
- Master (half
Synchronous -Slave duplex)
(half duplex)
22. What do you mean by
IC
At the low end of the Bus!?
communicationis FC The spcctrum oft
name IHC is communication options. for "inside the box"
Circuit) bus shorthand for a standard Inter-IC
(integrated
FC provides good support for
peripheral devices that are accessed communication with various slow, on-board
hardware resource necds. It is aintermittently,
Its
simple.
while being extremely modest in
speeds low-bandwidth,
Most available IFC devices operate at short-distance protocol.
up to 400Kbps
23. What do you mean by
Baud
The BRG supports both the Rate Generator (BRG)?
iS a dedicated 8-bit baud rate Asynchronous and Synchronousmodes of the USART It
Tunning 8-bit timer the desiredgenerator. The SPBRG register
baud rate and Fosc, the ncarestcontrols
the period of a free
Tegister can be calculated using the formula integer value for the PBRG
SYNC BRGH =0(LowSpced) BRGH =1(High Speed)
Baud Rate
0 (Asynchronous) Baud Rate FOSCI(16(X+1)
=FOSCK64(X+1)
Synchronous) Baud Rate
Page 14 / 33
33
 Open
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PA
ARM. 11 of 125
1. What is ARM
Processor? X
An ARM processor is one of a family of CPUs based on
set computer) the
makes 32-bit andarchitecture developed by Advanced RISC RISC (reduced instruction
64-bit
perform asmaller numberRISC multi-core prOCessors. RISC
Machines (ARM).ARM
a higher speed, of types of
computer prOceSsOTS are designed to
instuctions so that
performing more millions of instructions per second can operate at
they
2. (MIPS).
What are the features of ARM
D Load/store architecture. processor?
O An
DMostly
orthogonal instruction set.
OEnhanced single-cycle execution.
I 64 and 32-bit power-saving design.
execution states for
Hardware virtualization support. scalable high performance.
3. What are the
applications of ARM processor?
ARM processors are extensivcly used in
Smartphonestablets, multimediaplayers and otherconsumer
mobile
electronic deVIces such as
devices, such as wearables.
Bccausc of their reduced nstruction sct, thcy require
Smaller die size for the ntegrated circuitry (IC). Thefewer trans1sterS, which enables
reduced complexity and lower power ARM processors smaller size,
Increasingly miniaturized devices consumption makes them suitable for

4. What is meant by
Pipelining?
To improve the utilization of the
hardware resources, and als0 the prOcessor
throughput wouldbe to startthe next instruction beforethe current one has finished.
This technique is called pipelining.
5. What are the performance of Reduced Instruction Set
Computer (RISC)?
Pipelining pipelining is thesimplest form of concurrency to implement
ina processor and deliverS around
two to three times speed up.
I Ahigh clock rate with single cycleexecution 3MHZ for random accesses and
6Mhz for sequentialaccesses.

6. What are the drawbacks of RISC processor?

RISCs generalove poorcode
Instruction set Page 16
/33
densily (meansece of fixed length
RISCS donteNA
 5. What are the performance of Reduced nstruction Set Computer (RISC)?
Pipelining pipelining is the simplest form of concurrency to implement
in a processor and delivers around two to three times speed
up.
D A high clock rate with single cycle
execution 3MHz for random accesses and
6Mhz for sequential accesses.
6. What are the drawbacks of RISC processor?
RISCs generally have poor code density(means consequence of fixed
Instruction set)compared with CISCs length
D RISCs don t execute x86 code
Itis hard to fix though PC emulation software is available for many
platforms. RISC

7. Whatis a software development tool of ARM processor?

17

The ARM is supported by a toolkit which includes an instruction set emulator for
hardware modelling and software testing and benchmarking, an assembler C and
Cttcompilers, alinker and asymbolic debugger.
8. What is the example of RISC architecture?
O Berkeley RISC I and
O standford MIPS. Page 16 33

GN