DesignCon 2009

Characterization and Focus

Calibration of ATE Systems for
High-Speed Digital Applications

Jose Moreira, Verigy

[email protected]

Bernhard Roth, Verigy

[email protected]
Abstract
This paper discusses the challenge of characterizing and calibrating an automated test
system, including the DUT test fixture and socket, for high-speed digital applications. To
address this challenge, this paper introduces the concept of the “data eye profile” where
we analyze the performance of the data eye at different data rates, including its overall
timing accuracy, in the context of a multi-channel automated test system. These results
are then used for calibrating the system performance at the DUT socket in the test fixture.

Authors’ Biographies

Jose Moreira is a senior application consultant in the Center of Expertise of Verigy’s

Semiconductor Test Solutions division in Böblingen, Germany. He focuses on the
challenges of testing high-speed digital devices especially in the area of signal integrity
and jitter testing. He joined Agilent Technologies (now Verigy) in 2001 and holds a
Master of Science degree in Electrical and Computer Engineering from the Technical
University of Lisbon, Portugal.

Bernhard Roth is a senior design engineer in the ASIC team of Verigy’s Semiconductor
Test Solutions division in Böblingen, Germany. He focuses on the development of
Verigy's high-performance pin-electronics and holds several patents in that area. He
joined Hewlett-Packard (now Verigy via Agilent Technologies) in 1978 and holds a
Dipl.-Ing (FH) degree of the Fachhochschule Ulm, Germany.

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Introduction
Using automated test equipment (ATE) or stand alone instruments to characterize or
validate the design of multi-gigabit digital I/O cells in complex integrated circuits raises
several challenges. One important challenge is that the device under test (DUT) is located
on a test fixture that connects the DUT to the measurement instrumentation. This test
fixture can have a significant effect on the signals to be measured from the DUT as well
as the signals being used to stimulate the DUT. This is due to items such as the socket,
PCB traces or cables and multiple interface points such as connectors and pogo pins as
shown in Figure 1.
Instrument specifications that are defined at the input or output of the measurement
equipment provide little value when the data rates are high enough that the DUT test
fixture and the socket are the performance bottlenecks.

Figure 1: The ATE signal integrity chain from the ATE instrumentation pin-electronics to the DUT
socket.
Another challenge is that typical instrument calibration and control parameters (e.g.
output amplitude level) do not correspond to the application parameters the test engineer
needs to control. For example, to perform a receiver sensitivity measurement, a test
engineer is interested in stimulating the DUT with a waveform having a specific data eye
height which is then reduced until there is a failure condition at the DUT receiver. The
problem is that a standard ATE system (or even a bench type pattern generator
instrument) only allows the test engineer to control the driver amplitude that is calibrated
at DC levels (i.e. it corresponds to the data eye voltage rails when sending a static “1”
pattern with the programmed amplitude level). This calibration is done at the ATE pogo
pin interface, i.e. the DUT test fixture is not included. The ATE vendor might specify the
minimum guaranteed data eye height at a given data rate and data pattern at the pogo pin
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interface (e.g. 85% of programmed amplitude) but typically this value is not calibrated
for. The specification corresponds to the worst case with some additional margin and the
DUT test fixture is typically not included in this specification. When the test fixture is
included, it corresponds to a very specific and optimal configuration.

On the other side, ATE and bench instrumentation manufacturers face the challenge that
their equipment will be used on a wide variety of applications with very different types of
test fixtures. The only available option for the manufacturer is to provide the specification
at the instrument interface that connects to the test fixture or with a specific test fixture
that represents a typical application. The only solution to this dilemma is for the
instrument manufacturers to help the end users to develop efficient ways to measure the
performance of their measurement setup at the DUT socket, and if possible use this data
to generate a specification at the DUT and even provide some calibration factors. This is
clearly customer/application dependent, and for that reason needs to be performed by the
end user in conjunction with the manufacturer of the instrument.

One way to address this challenge is to understand the performance of the ATE system at
the DUT socket. The question then becomes: does one need to characterize the
performance at the DUT socket for all possible data rates that are to be tested or is
characterizing at the highest data rate enough.

Specifying and characterizing ATE performance at the DUT using the maximum data
rate for the application might not be the appropriate approach since it could happen that
the worst case scenario for the overall timing accuracy of the ATE system might not
occur at the maximum data rate. It could be dependent on the type of discontinuities
found on the DUT test fixture. This is especially important in applications that need to be
characterized over multiple data rates and timing schemes. For example, a
HyperTransport III I/O cell might have a maximum data rate of 6.4Gbps with a clock
forwarding clocking scheme but must still also be backward compatible with
HyperTransport I which might be operating at 2.0Gbps with a source-synchronous
clocking scheme. The amount of level jitter or noise added by the test fixture loss will
also depend on the data rate which means that a parameter like driver eye height will also
depend on the data rate.

To address this data rate dependency, the parameters of an ATE system that are critical to
the performance of a given application must be specified together with the data rate at
which the application is running. To achieve this, the concept of the data eye profile is
used where the key parameters at the DUT socket are specified for each possible data
rate.

This paper describes the effects of the test fixture and socket on high-speed digital
signals, followed by an introduction to the concept of the data eye profile where we
show, through simulation, the influence of the test fixture discontinuities and losses
which need to be addressed through calibration parameters for guaranteeing the
specification at the DUT socket. Finally, the paper compares the two different techniques

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to focus calibrate an ATE system at the DUT socket (simulation and in-situ
measurement) which also includes a discussion on the needed probing techniques.

Test Fixture Influence on Calibration Parameters at the

DUT
As already mentioned in the introduction, the DUT test fixture is currently the main
signal integrity bottleneck on an ATE system and its importance will continue to increase
as we move to higher data rates and pin counts [1,2,3]. On a typical test fixture for high-
speed digital applications (like the one shown in Figure 21) the following items are
usually critical for the performance of the ATE test fixture:

1. Trace geometry.
2. Dielectric material.
3. Pogo via and inter-layer via design.
4. Relays and relay footprint with associated transition vias.
5. DUT socket (or prober interface for at-speed wafer probing applications).

For some applications there might be additional parameters such as a dual transmission
line or “fly-by” design for bi-directional applications [4].

Figure 2: Dielectric material influence on the test fixture loss (left) and trace geometry influence in
the form of the trace width and length on the test fixture loss (right).
Figure 2 shows a comparison of the loss of a 19mil stripline with different dielectric
materials [5] as well as the effects of changes to the trace geometry (i.e. the trace width)
of a stripline. Both graphs correspond to the dielectric loss and skin effect loss that exist
on any signal routed on a PCB [6]. Typically these two effects are dominant even in well
designed test fixtures, and even changing trace geometry or dielectric material cannot
overcome the significant path length that is required for high-speed digital test fixtures.
To address this situation, modern ATE pin electronics include loss compensation
techniques (e.g. equalization) to compensate for some of the signal trace loss.
Inter-layer vias between different layers on the test fixture PCB or pogo vias that provide
the connection between a pogo pin based ATE interface and the test fixture can create a
significant discontinuity if not properly designed. Figure 3 shows one example of two

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pogo via designs and their respective insertion loss [7], showing that an optimized design
can significantly improve performance.

Microstrip Air
Transmission Line KV/m
34

PCB Layers 6

Pogo Pins 0
Air

Figure 3: Inter-layer vias and pogo vias can create significant discontinuities if not proper designed
using 3D EM simulation tools (left). The right figure shows two different designs for a pogo via
showing a significant performance difference for the same pogo assembly.

Relays have always been a critical part of test fixtures. But with the increase in data rates,
relays can also create significant discontinuities on the signal path. The challenge is two-
fold: not only does a proper relay need to be chosen for the application, but also the
footprint of the relay, including the transition vias from the signal stripline to the top of
the test fixture, must be properly designed [8]. Figure 4 shows one example of using a
full 3D-EM simulation tool for analyzing and optimizing the footprint for a relay
intended for a high-speed digital application.

Figure 4: Surface mounted relays create an impedance discontinuity that requires proper choice of
the relay and also optimization of the relay footprint through 3D EM simulation.
The DUT socket (or probe card for wafer probing applications) is the “last mile”
connecting the ATE system to the DUT. For multi-gigabit applications using BGA
packages with several hundreds I/O pins, even when choosing a state of the art socket (or
probe card), the effects of the socket can be significant for an ATE design verification
application.

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One should also consider the effect of the test fixture on the skew between the signals of
a differential pair, and between different signal pairs on a bus. One source of skew error
is the length matching of the signal traces on the PCB. Even if the length is
geometrically matched, non-homogeneities on the dielectric material (e.g. the dielectric
weave [9]) might change the propagation velocity of the signal and create a skew error
between matched length pairs.

The pin electronics of the ATE can also be a source of skew errors. These skew errors are
partially corrected by the standard ATE calibration, but a residual error might still exist
and will usually dominate the skew errors from an optimized DUT test fixture [10].
Depending on the application, the test engineer might need to obtain a higher degree of
skew matching at the DUT socket than what is guaranteed by ATE standard calibration.
It is also important to note that usually ATE specifications for the skew between channels
(e.g. in the form of the overall timing accuracy (OTA)) need to take into account the
worst case scenario between any channel on the ATE system. In a specific application
where only the skew between a specific subset of channels is important, such as the
channels corresponding to a source-synchronous bus, the maximum skew between those
channels can be much lower than the ATE specification. Knowing the exact value still
requires measuring the performance at the DUT socket for the channels of interest under
the conditions of the application.

Although one might infer that inter-channel timing accuracy is only important for source-
synchronous interfaces like HyperTransport I, having precise control on the inter channel
skew is also important to be able to properly characterize non-source synchronous high-
speed interfaces such as clock forwarding or an embedded clock. This allows not only to
characterize channel de-skewing algorithms that some of these interfaces utilize but also
to better analyze any crosstalk issues that might arise on the DUT (e.g. in the DUT
package). This skew control is also critical in the characterization of some high-speed
memory applications.

The Data Eye Profile Concept

The data eye profile concept is a way to display the important data eye diagram
properties as they change with data-rate. One approach for calculating the data eye profile
is the step-response, which can characterize a passive signal path completely. An
alternative approach would be characterization in the frequency domain through S-
parameters.

To generate the data eye diagram for computing the data eye profile without simulating
long PRBS data patterns at several data-rates, a once-simulated (or measured) step-
response can be easily used to efficiently compute the data eye diagram and extract the
needed information at each data rate.

For computing the data eye profile, the 50%-crossing of the step-response is considered
the calibration point corresponding to the time instant we switch from one bit to the next.

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Some typical data eye diagram properties that can change with data rate, and therefore
included in the data eye profile concept are:

• Effective data eye opening: The vertical data eye opening at the middle of the
data eye.
• Nominal data eye opening: The vertical data eye opening 0.5UI away from the
time zero calibrated point (note that in systems with multiple channels, this time
zero is the same for every channel).
• Maximal data eye opening: The maximum eye opening one can achieve at any
point on the data eye.
• Timing error (negative and positive): This value corresponds to the worst case
timing offset for a given bit transition which is before the calibrated “time zero”
for the entire system (negative timing error), or after the “time zero” (positive).
The difference between these two values will correspond to the peak-peak jitter
value. For an ATE system this value is directly related to the edge placement
accuracy (EPA).
• Timing shift: This value corresponds to the difference between the calibrated
“time zero” and the average of the positive and negative timing error defined on
the previous bullet.
• Jitter: This is the peak-peak jitter value which will correspond to the maximum
timing error variation.

Other interesting properties would be the peak-peak voltage, the transition time, etc.
Some of the properties are displayed in Figure 5. The time zero is the cal-point and the
timings for nominal (nom), effective (eff) and maximal (max) data eye opening or height
are shown.

Figure 5: Typical properties of an inner eye opening at a single data-rate.

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Figure 6 shows one approach to quickly compute the data eye profile. Each rising or
falling edge of the “perfect” data pattern is substituted with the corresponding step
response where the perfect rising edge is substituted by the 50% point of the step
response. All the edges are then added to compute the final waveform. Additional
waveforms are generated this way, representing different bit-streams. From all these
waveforms a data eye diagram is generated to compute the data eye parameters of
interest. This procedure is then repeated for each data rate point on the data eye profile.

Figure 6: Using the step response to quickly measure the data eye performance for computing the
data eye profile.
Figure 7 presents one example of a non-ideal step-response with some ringing which is
caused by reflections or mismatches in the simulated DUT test fixture. Figure 8 shows
the computed data eye profile computed for the step response. Note that the data rate
dependency of both the timing-errors/jitter and the data eye height are not necessarily
monotonic in nature. With the increasing the data-rate in this example, the relative
performance does not always get worse. This behavior is caused by the resonances of the
ringing seen in the step response. Figure 9 shows two computed data eye diagrams at
different data rates showing this effect.
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 Figure 7: Example of a step response including some ringing.

Figure 8: Computed data eye profile showing (from top) timing errors, jitter, timing shift in pS and
effective eye-opening in percentage of the programmed amplitude at the ATE driver.

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Figure 9: Computed data eye diagram from the step response showing a 'better' data eye opening or
height at a higher data rate (left, 1600Mbit/s) than at lower data rate (right, 800Mbit/s).

To better analyze the effects of the step response shape on the data eye profile, Figure 10
shows another example of a two simulated step responses from an ATE system with a
single mismatch on the test fixture that manifests itself as a short bump at different
locations. Figure 11 shows the computed data eye profile.

Figure 10: Two examples of step responses with a single mismatch.

In Figure 11, it is interesting to observe the data-rate dependent behavior of the timing-
errors and the data eye height. Starting with low data rates and moving to the higher data
rates, the bump first wanders into the center of the eye which reduces the data eye height,
it then moves out of the center of the eye with the effect of increasing the data eye height.
It finally moves into the signal transition which increases the timing error and the jitter.
This behavior repeats itself as we continue to move to higher data rates. From these
observations it becomes clear that a bump far away from a step creates more 'activity' on
the data-rate dependency than one close to the step.

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Figure 11: Computed data eye profile showing effect of the mismatches in the two step responses.
A final example of a step response is one where there are no discontinuities but simply
the low pass filter behavior from a lossy ATE test fixture. Figure 12 shows two simulated
step responses corresponding to two different lossy test fixtures, while Figure 13 shows
the computed data eye profile. Since there are no significant discontinuities in this case,
the data eye profile shows a monotonic behavior in which the performance gets worst as
we move to higher data rates.

Figure 12: Step response for an ATE system with only a low pass behavior and no reflective or
resonant discontinuities.
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 Figure 13: Computed data eye profile showing the monotonic low-pass behavior.

Focus Calibration at the DUT Socket using the Data Eye

Profile
There are four possible approaches one can use to address the challenge of developing a
procedure for obtaining the data eye profile at the DUT socket for use in a focus
calibration. They are:

1. Develop a simulation model of the DUT test fixture based on the test fixture
layout, trace geometry, and dielectric material properties. Together with a
simulation model of the ATE system, it is possible to simulate the data eye
profile.
2. Measure the manufactured DUT test fixture performance using S-parameters or
TDR/TDT, and together with a model of the ATE system simulate the data eye
profile.
3. Measure the data eye profile directly on the ATE system by measuring the data
eye performance at the DUT socket with external instrumentation for each data
rate point. We refer to this approach as in-situ calibration.
4. Measure the step response directly at the DUT socket with external
instrumentation and compute the data eye profile from the measured step
response.

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Option 1 has the advantage that no measurements are needed since the model is based on
the DUT test fixture design data such as the dielectric material parameters, signal trace
geometry, via models, etc. The drawback of this technique is that the accuracy of the
results will only be as good as the accuracy of the models used. Also the creation of
accurate models is not a trivial task and can be significantly time consuming. This
approach was the one used for the introduction to the data eye profile concept in the
previous sections.

Option 2 addresses the modeling challenge of the DUT test fixture by using a
measurement based modeling approach in which the test fixture signal traces are
measured, and the measurement results are used as the test fixture model. This model is
then combined with a model of the ATE pin electronics for simulating the ATE system
performance at the DUT socket. Typically the ATE pin electronics model is provided by
the ATE manufacturer. This approach has the advantage that no modeling of the DUT
test fixture is needed and it will be discussed in more detail later in this paper.

Option 3 uses a pure measurement approach without any modeling or simulation. In this
approach the signal at the DUT socket is measured for the ATE driver focus calibration,
or stimulated with a reference source for the ATE receiver calibration. This approach has
the advantage that no modeling or simulation tools are needed, and it is also a more
natural approach to most test engineers lacking simulation experience. One disadvantage
is that it needs to be performed using the ATE system. This can be important since this
takes the time out of other ATE tasks like device characterization, test program
debugging or production testing. This technique can also provide the most accurate
results since it utilizes all of the components of the actual test setup. This approach will
also be discussed in more detail later on this paper.

Option 4 also uses a pure measurement approach without any modeling or simulation but
unlike option 3, only the step response is measured. This means that only one
measurement is done for the ATE driver path (e.g. using an equivalent time oscilloscope
and probing at the DUT socket), and one measurement on the ATE receive path (e.g.
using a pattern generator to provide a step response waveform at the DUT socket to be
measured by the ATE receiver). The data eye profile would then be computed from the
step response. The main advantage of this approach is the fact that only one measure is
needed compared to measuring the data eye at each data rate point of option 3, but it still
requires the measurement to be done on the ATE system and the accuracy will depend on
how accurate the data eye can be computed from the step response.

Probing the DUT Test Fixture

To simulate or measure the data eye profile at the DUT socket for a focus calibration
approach, it is first necessary to develop an approach to measure the test fixture. For a
simulation based approach we need to be able to measure the test fixture from the pogo
via interface to the DUT socket. For an in-situ calibration approach we only need to be
able to measure at the DUT socket.

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Figure 14: Probing at the DUT socket with a micro-coaxial probe (left) and probing the pogo via with
a custom designed pogo assembly replicating the pogo assembly connection of the ATE system
(right).
Figure 14 (left) shows one approach for providing a measurement point at the DUT
socket using a micro-coaxial probe and an interposer. Figure 14 (right) shows another
approach to measure the test fixture at the pogo via side using a custom pogo assembly
with a mechanical bracket. A detailed discussion on these probing approaches and the
associated performance and calibration techniques is presented in reference [11].

Simulation Based Focus Calibration

As previously discussed, when using a simulation based approach to obtain the data eye
profile, it is necessary to measure the DUT test fixture with instrumentation like a vector
network analyzer (VNA) or a TDR/TDT module. Figure 15 shows a bench top
measurement setup used to perform the measurement on the signal paths of a test fixture
using the techniques presented in the previous section. Note that one major advantage of
this methodology is that there is no need to use the ATE system or have any knowledge
of the ATE system operation.

Figure 15: Bench setup for measuring the S-parameters of the signal traces of a test fixture for the
Verigy V93000 ATE system.
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In Figure 15 a four port VNA was used to characterize a differential pair on a DUT test
fixture for a multi-gigabit digital application. Figure 16 shows the measured insertion loss
where the -3db point is approximately at 1 GHz. This test fixture is clearly too lossy for
the target application maximum data rate of 5 Gbps. It is important to note that this test
fixture was intended to be used with ATE pin electronics (Verigy PinScale HX) which
contains equalization circuitry that, although compensating for some of the test fixture
loss, cannot compensate completely for such a lossy test fixture [12]. This measurement
result was enough to convince the engineer to redesign the test fixture to reduce the loss
of the signal path. For the purpose of this paper we will use this test fixture as a
demonstration vehicle in this and following sections.

Figure 16: Measured insertion loss (S21) for a text fixture single-ended signal trace including the
DUT socket (17 inch 8mil trace on NELCO4000-13 SI). The differential to which this single-ended
trace is part of was routed using a non-coupled configuration.
The measured S-parameters were imported into a simulation setup together with a model
of the ATE pin electronics. The simulation was performed using Agilent Technologies
ADS as shown in Figure 17.

Figure 17: Simulation setup of the ATE pin electronics plus the measured DUT test fixture S-
parameters.
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Figure 18 shows the simulated date eyes at two different data rates as seen at the DUT
receiver, which in this case is modeled by a perfect 100 Ohm differential termination. It
is easy to see the degradation of the data eye with the increased data rate. Figure 19
shows the simulated data eye profile of the data eye height for this specific signal trace on
the DUT test fixture. This result can then be used as a focus calibration parameter for
tests like receiver sensitivity.

Figure 18: Simulation results: data eye at the DUT receiver at a data rate of 1 Gbps (left) and 6.4
Gbps (right).

Figure 19: Data eye profile obtained through simulation using the test fixture signal trace S-
parameters and a model of the ATE driver for a PRBS7 data pattern. The programmed amplitude
on the ATE driver model was 800mV.

The ATE receiver signal path can be measured and simulated in the same way to obtain a
data eye profile for the ATE receiver to be used with focus calibration. Although in this
section we used the measured S-Parameters, for time domain simulations, it is also
possible to use the measured step or impulse response with the additional benefits they
provide for time domain simulations [13].
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One type of focus calibration that usually is not possible with this methodology is the
inter-channel skew driver/receiver calibration. The reason for this is that usually the
major contributor for the channel to channel skew is the ATE system pin electronics and
not the DUT test fixture. This skew is of course compensated by the standard ATE
calibration that usually employs a TDR approach. If the test engineer needs to improve
the calibration through a focus calibration methodology, the approach presented in this
section does not work because inter-channel skew for a specific set of channels is not
possible to be included in the simulation model provided by the ATE manufacturer.

In-Situ Focus Calibration

As discussed previously, the in-situ approach to measure the data eye profile for focus
calibration is to measure the test fixture DUT socket with the ATE system driver/receiver
included in the measurement. External instrumentation is used for this measurement
where the ATE driver performance is measured with an oscilloscope, and the ATE
receiver through a calibrated stimulus provided by a pattern generator.

Figure 20 and Figure 21 show the measurement setup for an in-situ focus calibration of a
test fixture on a Verigy V93000 ATE system showing the different measurement
instruments. An external high-precision RF source is used as trigger for all instruments
and this source also provides a 10Mhz reference signal to the ATE system master clock
guaranteeing frequency synchronization across the entire measurement setup. For the
ATE driver focus calibration, an Agilent Technologies 86100C equivalent time
oscilloscope (also known as DCA) with a 70 GHz remote sampling head is used. For the
ATE receiver focus calibration, an Agilent Technologies N4903A serial BERT is used as
a digital stimulus reference source. For the receiver calibration, a pre-calibration step is
also performed where the performance of the N4903A generator is calibrated to the end
of the cables that will be connected to the micro-coaxial probes. This can be done using
the equivalent time oscilloscope. This pre-calibration only needs to be performed once.

Figure 20: In-situ focus calibration measurement setup.

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Figure 21: Probing the DUT test fixture socket with an interposer and a double micro-coaxial probe.

Figure 22 shows a picture of the graphic user interface (GUI) of the focus calibration
software developed for automating the needed instrument control and data gathering. It
controls the external instruments through GPIB and communicates with the ATE control
software (Verigy SmarTest) that is running on the same Linux workstation.

Figure 22: The Verigy V93000 SmarTest software and the focus calibration graphic user interfaces.

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Figure 23 shows the data eye measured with the equivalent time oscilloscope at the DUT
socket using two different data rates for the signal trace in Figure 16 including the ATE
pin electronics driver.

Figure 23: In-situ measurement results: data eye at the DUT socket for a data rate of 1 Gbps (left)
and 6.4 Gbps (right) using a PRBS7 data pattern.

Figure 24 shows the measured data eye height profile for the ATE driver at the test
fixture DUT socket for the exact same signal trace used on the simulation based focus
calibration section.

Figure 24: ATE driver data eye height profile at the test fixture DUT socket for two different data
patterns (PRBS7 and a bit clock pattern). The programmed amplitude on the ATE driver was
800mV.

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In Figure 24 it is possible to observe a monotonic behavior on the driver data eye height
profile in regards to the data rate. This is expected for a lossy test fixture without major
discontinuities as already observed in Figure 13. Another important observation is the
effect of the data pattern on the data eye profile. In this case the clock pattern will have
no data dependent jitter (DDJ) contributing to the timing and levels, while the PRBS7
pattern will have DDJ from the test fixture loss that in turns further reduces the data eye
height. This shows that if one intends to use the data eye profile for focus calibration, it is
important to use the same pattern that is intended to be used on the end application.

Figure 25 shows the data eye profile for the ATE receiver data eye height. Like for the
driver eye height it is possible to observe the monotonic degradation with the data rate
and the pattern influence as expected. The other important item that was already
mentioned is the calibration of the reference stimulus source. For this measurement the
stimulus source driver must have a calibrated data eye height since the programmed
amplitude might not correspond to the driver eye height depending on the instrument
performance and the used cables. Figure 25 also shows the difference between the data
eye profiles if the stimulus source is calibrated before the data eye profile measurement
on the ATE system is done or if no calibration on the stimulus source is done. It can be
seen that even with state-of-the art equipment one benefits from calibrating the source
stimulus.

Figure 25: ATE receiver data eye profile at the test fixture DUT socket for two different data
patterns (PRBS7 and a clock pattern). The calibrated data eye height from the stimulus external
pattern generator was 800mV.
It is also important to note on these measurements that the pin electronics integrated
equalization will compensate for part of the test fixture loss. If we did a data eye profile

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of this test fixture with a driver/receiver without any equalization the results would be
significantly worse.

Figure 26 (left) shows the data eye profile for the timing shift (also sometimes identified
as timing skew) for one ATE driver pin referenced to another pin. The target application
on this example is a HyperTransport (HT) interface where the forwarded clock is the
reference and the ATE driver is one of the data pins in the HT bus. The figure shows a
clearly non-monotonic behavior. Since we are using a clock pattern, there is no timing
error due to the test fixture DDJ which means that the observed data rate dependence is
mainly due to the residual skew from the ATE system after the standard calibration. This
is a typical behavior for any test and measurement system and by using this data eye
profile data, it is then possible to further focus calibrate the system to obtain a very tight
skew calibration.

Figure 26 (right) shows another example of using the data eye profile for calibration of a
jitter tolerance test. The figure shows the measured peak-peak jitter at the DUT socket
when the ATE driver is providing a stimulus waveform with a programmed value of
sinusoidal jitter added to the waveform. Since the test fixture will add a certain amount of
DDJ to the waveform, the amount peak-peak jitter at the DUT socket does not correspond
to the programmed value. Although in this approach the jitter peak-peak value was used,
one could use the same approach using the deterministic jitter (DJ) value obtained
through a jitter separation approach.

Figure 26: Representation of the timing shift (or timing skew) of one ATE driver pin compared to a
reference pin using a clock pattern (left). Measured peak-peak jitter value at the DUT socket for a
PRBS7 data pattern at 4 Gbps with a given amplitude of sinusoidal jitter added at a frequency of
1Mhz (right).

The other approach for in-situ calibration is to measure the step response and then
compute the data eye profile. Figure 27 shows the measured step response at the DUT
socket from the ATE driver and the computed data eye profile. Note that the measured
step response includes not only the degradation due to the test fixture but also the ATE
driver performance and the equalization from the ATE pin electronics that improves the
step response when comparing with the performance that would be obtained from the test
fixture alone and a driver with no equalization.
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Figure 27: Measured step response at the DUT socket (left) and the computed data eye profile for the
data eye height from the measured step response (right).

Conclusions
With the test fixture determining the performance of an ATE system for high-speed
digital applications, and given the variety of performances a test fixture can have
depending on the application specifics, it becomes clear that specifications at the
instrument connectors (or ATE pogo pins) are not sufficient for characterization and
design verification testing. Multi-gigabit applications clearly need ATE specifications
that identify the performance and calibrate the ATE system at the DUT socket.

The concept of the data eye profile provides a framework to evaluate the effects of the
ATE test fixture and environment in the context of a typical high-speed digital
application. This data can then be used to provide a focus calibration to the DUT socket.

Determining which strategy is best for obtaining the needed data eye profile for the focus
calibration either through simulation or in-situ measurement really depends on the
specifics of the application and the available resources. The option to outsource the test
fixture signal path measurement and avoid adding to the workload of the test engineer
and adding to the time on the ATE system (which is usually at a premium) may be a
deciding factor. The engineer could then use this measurement data combined with a
model of the ATE pin-electronics to simulate the performance at the DUT. The ATE
resource dependent option of using in-situ measurements can be used to avoid any errors
that are inherent in a simulation by providing directly observable data. Figure 28 shows a
comparison between both approaches using the data from the previous. Although there is
a difference between the results (as can be expected), the important point is that not doing
any type of focus calibration would imply almost a 50% error on a receiver sensitivity
test at 3Gbps.
The S-parameter based simulation shows the worst results but on the other side is the
only one that did not require any measurements in-situ on the ATE system, but its
accuracy is dependent on the accuracy of the used models.

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Figure 28: Comparison of the data eye profile between a simulation based approach (using the signal
trace measured S-parameters) and an in-situ measurement approach. The programmed driver
amplitude is 800mV.

Acknowledgements
We would like to first acknowledge the contribution of Heidi Barnes from Verigy for this
paper through her work on signal integrity especially on the interposer design and
probing methodology. We would like to thank Kevin White from Verigy for the
mechanical design of the socket probing solution and Stefan Richter from Emsyen for the
implementation of the focus calibration GUI. We would also like to thank Callum
McCowan from Verigy for being the first user of this approach, providing important
feedback and also Roger Nettles and Joerg-Walter Mohr for the constructive discussions
and detailed review of this paper.
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