BISWAJIT_MANDI_11000223012
GOVERNMENT COLLEGE OF ENGINEERING
AND TEXTILE TECHNOLOGY, SERAMPORE
(COTINNUOUS
ASSESMENT-2)
TOPIC: INSTRUCTION CYCLE
NAME: BISWAJIT MANDI
UNIVERSITY ROLL NO: 11000223012
REGISTRATION NO: 231100110102
STREAM: INFORMATION TECHNOLOGY
SEMSTER: 3TH
SUBJECT: COMPUTER ORGANISATION
PAPERCODE: PCC-CS302
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INDEX
1. INTRODUCTION 3
2. CHARECTERISTIC 4 - 10
3. ADVANTAGES & DISADVANTAGES 11
4. CONCLUSION 12
5. REFERENCE 12
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INTRODUCTION
INSTRUCTION CYCLES:
The Central Processing Unit, or CPU, is the computer system’s brain. The CPU, regarded as
the most critical component of a computer system, is in charge of processing, handling, and
maintaining all of a computer’s instructions and operations throughout its operation.
The CPU uses a cycle known as the Instruction cycle to process all of these instructions and
operations. The instruction cycle is the time it takes a CPU to execute and retrieve a complete
education. We will go over the registers used in all processes in this context.
As mentioned before, the primary function of a CPU is to execute and run a program. A set
of instructions is to be processed to run such a program. Every education in a given program
undergoes the instruction cycle stages until the whole program is finally executed.
This cycle begins as soon as the system is switched on and ends when it is shut down. Therefore,
every single task on a computer undergoes this cycle, and the process is repeated until the
system is shut dwn.
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CHARECTERISTIC
Memory address registers(MAR) : It is connected to the address lines of the
system bus. It specifies the address in memory for a read or write operation.
Memory Buffer Register(MBR) : It is connected to the data lines of the system bus.
It contains the value to be stored in memory or the last value read from the memory.
Program Counter(PC) : Holds the address of the next instruction to be fetched.
Instruction Register(IR) : Holds the last instruction fetched
In computer organization, an instruction cycle, also known as a fetch-decode-execute cycle, is
the basic operation performed by a central processing unit (CPU) to execute an instruction. The
instruction cycle consists of several steps, each of which performs a specific function in the
execution of the instruction. The major steps in the instruction cycle are:
Fetch:
In the fetch cycle, the CPU retrieves the instruction from memory. The instruction is typically
stored at the address specified by the program counter (PC). The PC is then incremented to point
to the next instruction in memory.
Decode:
In the decode cycle, the CPU interprets the instruction and determines what operation needs to
be performed. This involves identifying the opcode and any operands that are needed to execute
the instruction.
Execute:
In the execute cycle, the CPU performs the operation specified by the instruction. This may
involve reading or writing data from or to memory, performing arithmetic or logic operations on
data, or manipulating the control flow of the program.
There are also some additional steps that may be performed during the instruction cycle,
depending on the CPU architecture and instruction set:
Fetch operands:
In some CPUs, the operands needed for an instruction are fetched during a separate cycle before
the execute cycle. This is called the fetch operands cycle.
Store results: In some CPUs, the results of an instruction are stored during a separate cycle
after the execute cycle. This is called the store results cycle.
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Interrupt handling:
In some CPUs, interrupt handling may occur during any cycle of the instruction cycle. An
interrupt is a signal that the CPU receives from an external device or software that requires
immediate attention. When an interrupt occurs, the CPU suspends the current instructiand
executes an interrupt handler to service the interrupt.These cycles are the basic building blocks
of the CPU’s operation and are performed for every instruction executed by the CPU. By
optimizing these cycles, CPU designers can improve the performance and efficiency of the
CPU, allowing it to execute instructions faster and more efficiently.
The Instruction Cycle –
Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-
operations. In the above examples, there is one sequence each for the Fetch, Indirect,
Execute and Interrupt Cycles.
The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always
followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on
the state of the system.
We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates the
state of processor in terms of which portion of the cycle it is in:-
1 : Fetch Cycle
2 : Indirect Cycle
3 : Execute Cycle
4 : Interrupt Cycle
At the end of the each cycles, the ICC is set appropriately. The above flowchart of Instruction
Cycle describes the complete sequence of micro-operations, depending only on the instruction
sequence and the interrupt pattern(this is a simplified example). The operation of the processor is
described as the performance of a sequence of micro-operation. Different Instruction Cycles:
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The Fetch Cycle –
At the beginning of the fetch cycle, the address of the next instruction to be executed is in the
Program Counter(PC)
Step 1: The address in the program counter is moved to the memory address register(MAR),
as this is the only register which is connected to address lines of the system bus.
step 2: The address in MAR is placed on the address bus, now the control unit issues a READ
command on the control bus, and the result appears on the data bus and is then copied into the
memory buffer register(MBR). Program counter is incremented by one, to get ready for the next
instruction. (These two action can be performed simultaneously to save time)
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Step 3: The content of the MBR is moved to the instruction register(IR).
Thus, a simple Fetch Cycle consist of three steps and four micro-operation. Symbolically, we can
write these sequence of events as follows:-
Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents successive time units.
We assume that a clock is available for timing purposes and it emits regularly spaced clock
pulses. Each clock pulse defines a time unit. Thus, all time units are of equal duration. Each
micro- operation can be performed within the time of a single time unit.
First time unit: Move the contents of the PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR. Increment
content of PC by I.
Third time unit: Move contents of MBR to IR.
Note: Second and third micro-operations both take place during the second time unit.
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The Indirect Cycles –
Once an instruction is fetched, the next step is to fetch source operands. Source Operand is being
fetched by indirect addressing( it can be fetched by any addressing mode, here its done by
indirect addressing). Register-based operands need not be fetched. Once the opcode is executed,
a similar process may be needed to store the result in main memory. Following micro-operations
takes place:-
Here, this instruction adds the content of location X to register R. Corresponding
micro- operation will be:-
We begin with the IR containing the ADD instruction.
Step 1: The address portion of IR is loaded into the MAR.
Step 2: The address field of the IR is updated from the MBR, so the
reference Memory locationis read.
Step 3: Now, the contents of R and MBR are added by the ALU.
Lets take a complex example :-
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Here, the content of location X is incremented by 1. If the result is 0, the next instruction will be skipped.
Corresponding sequence of micro-operation will be :-
Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not) and action
(PC is incremented by 1) can be implemented as one micro-operation.
Note : This test and action micro-operation can be performed during the same time unit during
which the updated value MBR is stored back to memory.
The Interrupt Cycle:
At the completion of the Execute Cycle, a test is made to determine whether any
enabled interrupt has occurred or not. If an enabled interrupt has occurred then Interrupt
Cycle occurs. The nature of this cycle varies greatly from one machine to another.
Lets take a sequence of micro-operation:-
Step 1: Contents of the PC is transferred to the MBR, so that they can be saved for return.
Step 2: MAR is loaded with the address at which the contents of the PC are to be saved.
PC is loaded with the address of the start of the interrupt-processing routine.
Step 3: MBR, containing the old value of PC, is stored in memory.
Note: In step 2, two actions are implemented as one micro-operation. However, most
processor provide multiple types of interrupts, it may take one or more micro-operation to
obtain the save_address and the routine_address before they are transferred to the MAR and
PC respectively.
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Uses of Different Instruction Cycles
Here are some uses of different instruction cycles:
Fetch cycle:
This cycle retrieves the instruction from memory and loads it into the processor’s instruction
register. The fetch cycle is essential for the processor to know what instruction it needs to
execute.
Decode cycle:
This cycle decodes the instruction to determine what operation it represents and what
operands it requires. The decode cycle is important for the processor to understand what it
needs to do with the instruction and what data it needs to retrieve or manipulate.
Execute cycle:
This cycle performs the actual operation specified by the instruction, using the operands
specified in the instruction or in other registers. The execute cycle is where the processor
performs the actual computation or manipulation of data.
Store cycle:
This cycle stores the result of the operation in memory or in a register. The store cycle is
essential for the processor to save the result of the computation or manipulation for
future use.
The advantages and disadvantages of the instruction cycle depend on various factors, such as
the specific CPU architecture and the instruction set used. However, here are some general
advantages and disadvantages of the instruction cycle:
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ADVANTAGES & DISADVANTAGES
Advantages
Standardization: The instruction cycle provides a standard way for CPUs to execute
instructions, which allows software developers to write programs that can run on multiple
CPU architectures. This standardization also makes it easier for hardware designers to build
CPUs that can execute a wide range of instructions.
Efficiency: By breaking down the instruction execution into multiple steps, the CPU can
execute instructions more efficiently. For example, while the CPU is performing the execute
cycle for one instruction, it can simultaneously fetch the next instruction.
Pipelining: The instruction cycle can be pipelined, which means that multiple instructions
can be in different stages of execution at the same time. This improves the overall
performance of the CPU, as it can process multiple instructions simultaneously.
Disadvantages:
Overhead: The instruction cycle adds overhead to the execution of instructions, as each
instruction must go through multiple stages before it can be executed. This overhead can
reduce the overall performance of the CPU.
Complexity: The instruction cycle can be complex to implement, especially if the CPU
architecture and instruction set are complex. This complexity can make it difficult to design,
implement, and debug the CPU.
Limited parallelism: While pipelining can improve the performance of the CPU, it also has
limitations. For example, some instructions may depend on the results of previous
instructions, which limits the amount of parallelism that can be achieved. This can reduce the
effectiveness of pipelining and limit the overall performance of the CPU.
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CONCLUSION
The instruction fetching decode cycle is an essential operation in a computer system that
deals with primary operations in the CPU. Until the system enters the shutdown phase, it
continues indefinitely in a looping scenario. All computer processor system instructions use
the instruction fetch and decode cycle to execute operations.
REFERENCE
https://www.geeksforgeeks.org/different-instruction-cycles/
-:THANKS YOU:-
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