REV Description Date Drawn Electrical Mechanical Safety Approved

S0 Release for EVT stage PSU S1F Oct 14’20 Suriyan.P Saowanee.Kron Jaruwath Rattiya Walalak
Release for S2F
-update DC input brown in/out
-update Dips >95 % reduction 0. 5
Mar
S1 period, B (was A) Suriyan.P Saowanee.Kron Jaruwath Rattiya Walalak
- 13.2 EMC Requirement by adding 01’2021
(5 dB margin for DC input)

- Update SMB Alert 1mS-5mS

Mar
S2 - Update sharing accuracy at Suriyan.P Saowanee.Kron Jaruwath Rattiya Walalak
output current >50% of 2400W 23’2021

DCC-Thailand5
Document is released
2021.04.09 16:54:28
+07'00'

台達電子工業股份有限公司 DESCRIPTION:
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
DOCUMENT NO. : REV.
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION.
ES-TDPS-2400HB A S2
SHEET 1 OF 74
 1 SCOPE

This document describes the functional requirements and characteristics for multi-sources common CRPS power supply for the
customer projects.

Power Supply Features

Power Supply Features

• 100~127Vac/200~240Vac input via IEC grounded connector
• HVDC input operation 180-300Vdc (Safety label 240Vdc)
• AC input connector IEC 320-C20
• High efficiency to meet 80 plus Titanium Level
• Hot pluggable and N+1 redundant
• Single 4056 fan for PSU self cooling (265mm form factor)
• PMBus 1.2 compliant
• Single bi-color LED

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 2 OF 74
 2 INPUT REQUIREMENTS
The power supply shall operate normally without any user intervention. The input must have primary to secondary isolation within the power supply.

2.1 Input Requirements

Below lists the power supply requirements:

Specification Min Nominal Max Notes

AC Input voltage
90 100-127 140
(VRMS)
auto-ranging
AC Input voltage
180 200-240 264
(VRMS)
DC Input voltage
180 240 300 China HVDC
(VDC)
AC Frequency (Hz) 47 50/60 63

Leakage current (mA) 0.8 Tested at maximum input voltage

Inrush current (A) 35

Efficiency See section 2.5

Power Factor See section 2.6

10 @ High Line at 100% load (2400W)

Holdup time (mS) 14 @ High Line at 70% load (1680W)

20 @ Low Line at max load (1000W)

7 @ High Line at 100% load (2400W)

Ride Through (ms) 11 @ High Line at 70% load (1680W)

20 @ Low Line at max load (1000W)

Table 1 : Input Requirements

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 3 OF 74
 2.2 Input Voltage and Current Requirements
With any combination of nominal rated AC voltage, frequency, environment, and with any combination of rated continuous output loading, the steady state

input current to the power supply shall not exceed the values in the following table. The steady state AC RMS input voltage shall be single phase sinusoidal,

rectified AC or a steady-state DC input voltage, and shall be within the following limits:

Input Voltage Input Current

[VACRMS or VDC] [Amps]

100~127Vac 15

200~240Vac 15

200-240Vdc 15

Table 2 : Maximum Input Current

2.3 240VDC Input Specification (China Certs only)

The power supply must be able to operate normally with 240VDC input.
• Operating range: 180VDC to 300VDC
• PMBus commands must function normally
• Power timing requirements met
• Output power requirements
• LED functioning
• In Cold Standby mode or always standby mode the PSU must turn on quickly and maintain voltage
regulation limits in the event the active PSU experiences a loss of AC input or fault.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 4 OF 74
 2.4 Inrush Current
After AC power is applied to the power supply, any initial inrush current surge or spike of 10
milliseconds or less shall not exceed 35 amps peak, due to the charging of the X-caps. Any additional
inrush current surges or spikes in the form of AC cycles or multiple AC cycles shall not exceed 35 amps
peak. This shall be true for the full input AC range and frequency.

Repetitive on/off cycling of the AC mains shall not damage the power supply.

2.5 Efficiency
Following table lists the required power supply efficiency (Pout / Pin) as a function of the output load current.
Input Voltage
10% Load 20% Load 50% Load 100% Load
[VRMS]
230VACRMS >90% >94% >96% >91%

Table 3 : Power Supply Efficiency Requirements

Notes:
1. The supplier will use the “Generalized Internal Power Supply Efficiency Test Protocol”, latest
revision. A link to the document can be found on the 80 Plus web site found
at http://www.plugloadsolutions.com/80PlusPowerSupplies.aspx.
2. 80 Plus certification to meet Titanium rating is required.

2.6 Power Factor

The power factor shall be equal to or gerater than that shown in the following table.
Input Voltage
10% Load 20% Load 50% Load 100% Load
[VRMS]

100Vac ~ 240Vac >0.90 >0.96 >0.98 >0.99

Table 4 : Power Factor Requirement

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 5 OF 74
 2.7 iTHD
The below table shown the power supply “Total Harmonic Distortion” limits which according
EN61000-3-2 standard under 230/240Vac, 50/60Hz and 208Vac, 60Hz conditions.
5% Load 10% Load 20% Load 50% Load 100% Load

Max. iTHD% <20% <15% <10% <8% <5%

Table 5 : iTHD Requirement

2.8 Input Harmonic Current Limits

The power supply shall meet the requirements of IEC 61000-3-2 as defined for Class A equipment.
Power supplies must meet the Japan harmonic requirements. This section does not pertain to DC input.
Class “A” Limit
Harmonic Order (n) Japan Limit
(A)
3 2.3 2.3 + 0.00283(P-600)
5 1.14 1.14 + 0.00108(P-600)
7 0.77 0.77 + 0.00083(P-600)
9 0.40 0.40 + 0.00033(P-600)
11 0.33 0.33 + 0.00022(P-600)
13 0.21 0.21 + 0.00022(P-600)
15 ≤n ≤ 39
2.25 /n 0.15 + 0.00300(P-600)/n
Where n = odd harmonics
2 1.08 1.08 + 0.00033(P-600)
4 0.43 0.43 + 0.00017(P-600)
6 0.30 0.30 + 0.00012(P-600)
8 ≤n ≤ 40
1.84/n 0.23 + 0.00072(P-600)/n
Where n = even harmonics
Table 6 : Input Harmonic Distortion Limits

Notes:
1) For test voltages other than 230VAC, the limit is multiplied by a factor of 230 divided by the
nominal test voltage.
2) P is the active input power in watts.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 6 OF 74
 2.9 Input Connector and Wiring
The AC input connector shall be an IEC 320-C20 connector rated for 20A at 100 VAC and 16A at 250
VAC. Refer to the power supply mechanical drawing for the physical location of the AC input connector.

2.10 Brownout And Recovery

The PSU shall not be damaged if input voltage drops below the minimum low line voltage specified in
following table. The PSU will operate normally after input voltage within the range specified in following
table without manual intervention. On/Off oscillation during a Brownout condition is not allowed.
VACRMS VDC

Vin (Turn On) 81V~89V 175V-180V

Vin (Turn Off) 69V~79V 165V-170V

Table 7 : Brown Out and Recovery

2.11 Input Fusing

The power supply shall have one line fused in the single line fuse on the line (Hot) wire of the AC
input. The line fusing shall be acceptable for all safety agency requirements. The input fuse shall be a
fast blow type. AC inrush current shall not cause the AC line fuse to blow under any conditions. All
protection circuits in the power supply shall not cause the AC fuse to blow unless a component in the
power supply has failed. This includes DC output load short conditions.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 7 OF 74
 3 DC OUTPUT REQUIREMENTS
There are two DC outputs generated by the power supply: +12Vsb and +12V will be present whenever
the DC input is within specification. The +12V is controlled via the PS_ON signals. All output voltages
shall be diode / MOSFET ‘Ored” to allow for sharing between two supplies in the system.

3.1 DC Output Voltages Regulation

below lists the allowable DC output voltages for the power supply under all line and load conditions,
including ripple / noise and dynamic current.

+12V +12Vsb
Remark
[Volt] [Volt]
Minimum 11.4 11.4

Nominal 12.00 12.00 Vrms

Maximum 12.6 12.6

Table 8 : Output Voltage DC Requirements

Notes:
1) The power supply must operate without loads on any or all of the output voltages, without
indicating any over-voltage or under-voltage conditions.
2) The output voltages are measured/evaluated on the system [backplane] side of the mating output
connectors

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 8 OF 74
 3.2 Output Currents
The minimum and maximum DC rated currents for each output level are given in below.

Output Min current Max current

Remark
Rails [Amp] [Amp]
+12Vsb 0 3

+12V 1 83.35 100~127Vac

200V~240Vac
+12V 1 200
240Vdc
Table 9 : Output Current Requirements

3.3 Ripple and Noise

The maximum output ripple/noise of the power supply is defined in below. This is measured over a
bandwidth of 20MHz at the power supply output connector. A decoupling network composed of a 10uF
aluminum electrolytic capacitor in parallel with a 0.1uF ceramic capacitor shall be soldered across each
group of output pins at the mating connector for output rails measurement and 22nF ceramic capacitor for
signals measurement. To minimize lead inductance, the capacitor leads shall be kept as short as possible.

Ripple
Output Rails
[mV P-P]
+12Vsb 200

+12V 200

Table 10 : Ripple and Noise Requirements

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 9 OF 74
 3.4 Dynamic Current
The output voltages shall remain within limits specified for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50Hz and 5kHz at
duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The
Δ step load may occur anywhere within the MIN load to the Peak load conditions.

During a load step, the output voltage must remain within the regulation limits given in below.
Output Step Load [Amp] Slew Rate Capactive Load Min Voltage Max Voltage
Rails (see Note 1 and 2) [A/uS] [uF] [VDC] [VDC]
+12Vsb 1 0.5 1000 11.4 12.6

+12V 100 0.5 2200 11.4 12.6

Table 11 : Dynamic Current Limits

Note 1: During 100% load change shall not cause the power supply shut down.
2: For dynamic condition of 12V minimum load is 5A.

3.5 Capacitive Loading

The capacitive loading for each output is listed in the table below.

Minimum Maximum
Output
Capacitance Capacitance
Voltage
[uF] [uF]
+12Vsb 1,000 3,100

+12V 2,200 70,000

Table 12 : Capacitive Loading

3.6 Output Voltage Overshoot

Any overshoot on any output level at turn-on shall be less than 105% of the maximum regulation limit and should
not cause an over-voltage fault condition for any load or input voltage.During hot-plug of the power supply, the
Output Voltage Overshoot requirements also must be met (see the section named “Concurrent Maintenance”).For
over-voltage tolerancing during hot-plug, see the Concurrent Maintenance section.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 10 OF 74
 3.7 Residual Voltage
The residual voltage at the outputs shall not exceed 100mV when input power is applied to the supply,
the power supply is OFF and there is no load.

3.8 No Load Operation

If the load is removed from the output, the PSU must start up and operate normally.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 11 OF 74
 3.9 Control Loop Bandwidth and Stability
The power supply must have acceptable phase margin (45 degrees or higher ) ,gain margin (10dB or higher) and
bandwidth for all conceivable input and output conditions including known system capacitance.

 At minimum load, the power supply must be stable for minimum through maximum system capacitance
configurations.
 At full load, the power supply must be stable with system capacitance between the minimum system
capacitance and maximum system capacitance.
 The power supply should also display stable transient responses when the outputs are subjected to the dynamic
loading described in Section 3.4 .
 The power supply must also be stable when powering a negative impedance load such as a VRM.

Note: Switchable preload resistors might be required on the outputs to maintain the dynamic response to load
changes within the system. These loads keep the output inductor near continuous conduction to maintain the wide
bandwidth of the supply with light loads.
The PSU shall include a 10-ohm resistor in every voltage feedback loop (for measuring loop response),
at a point where all information is in one path and where a low impedance drives a high impedance.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 12 OF 74
 4 REDUNDANT OPERATION
The power supply will be used in a system with one additional, redundant, power supply.
The load is shared between the power supplies that are OR-ed together. When two power supplies are
ORed together, they will be used in an N+1 configuration.

4.1 Active Current Sharing

The +12V outputs of two supplies connected in parallel (1+1 redundancy) must meet the regulation
requirements of a single supply. Under normal operation, the +12V outputs must share current between
two supplies. If one of the supplies fails, the remaining supply must pick up all of the load without any of
the outputs dropping out of regulation. No current sharing is required on the +12Vsb output. An active
current-share method shall be used, where a Ishare pin for each current-sharing output level must be
connected to the equivalent pin on the other supply which is sharing the total load for that output level.
The must meet current sharing accuracy as shown in below table.

Output Current
Accuracy
(Bus)
Iout > 50% of 2400W +/- 5%

Table 13 : Current Sharing Accuracy

4.2 Concurrent Maintenance

This power supply must be designed to be “hot plugged / unplugged,” including both Standby and Powered-On
modes. Output “OR'ing” diodes (or FETs) are required for all outputs. If a power supply fails, the internal circuitry
must receive power from the parallel power supply (i.e. +12V output) to continue to power the internal fans and logic.
Faults must not be generated in the functioning units during removal or insertion of a supply. During hot-plug
events, the output voltages must remain above the low-side regulation limit. The output voltages must also remain
within regulation. Applications requiring DC input hot unplug capability will be required to turn off the power
supply prior to disconnecting the input line cord to minimize arcing damage.

4.3 Output Isolation

All output voltages shall be diode / MOSFET ‘Ored” to allow for sharing between two supplies in the system.

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 13 OF 74
 4.4 Sharing Bus Voltage
The sharing bus voltage measurement shall exclude fan current and meet below voltage level.

ISHARE 12V Bus Current

Load Condition
[Volt] [Amp]
0% ≤0.3 0

25% 2 +/- 0.2 50

50% 4 +/- 0.2 100

100% 8 +/- 0.2 200

Table 14 : Sharing Bus Voltage Table

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 14 OF 74
 5 FAULT PROTECTIONS
5.1 General Requirements
The power supply shall protect itself and the system from catastrophic failure. Protection circuitry
shall include input under-voltage, output over-voltage, output under-voltage and output over-current. The
+12V and +12Vsb outputs must be protected so that a system short circuit or supply failure does not result
in a power supply catastrophic failure or damage the system. For manufacturing test and verification of
the specifications in this section, the supply outputs shall be considered to be independent supplies.

5.2 Over-Current Protection

The power supply shall have current limit to prevent the outputs from exceeding the values shown in
table below. If the current limits are exceeded the power supply shall shutdown and latch off. The latch
will be cleared by an AC power interruption. The power supply shall not be damaged from repeated
power cycling in this condition. +12Vsb will be auto-recovered after removing OCP limit.

Over-Current Limits
Output
Voltage Min Max Slew Rate Remark
[Amp] [Amp] [A/Sec]
+12Vsb 3.6 4 0.25A/S

+12V(Low line) 114 124 1A/S Low Line

+12V(High Line) 230 240 1A/S High Line

Table 15 : Over-Current Protection Limits

5.3 Over-Voltage Protection

The power supply over voltage protection shall be locally sensed. The power supply shall shutdown

and latch off after an over voltage condition occurs. This latch shall be cleared by toggling the PSON#

signal or by an AC power interruption. The values are measured at the output of the power supply’s
connectors. The voltage shall never exceed the maximum levels when measured at the power

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 15 OF 74
connectors of the power supply connector during any single point of fail. The voltage shall never trip
any lower than the minimum levels when measured at the power connector. +12Vsb will be auto-
recovered after removing OVP limit.

Over-Voltage Limits
Voltage
Min [V] Max [V]

+12Vsb 13.5 14.5

+12V 13.5 14.5
Table 16 : Over-Voltage Protection Limits

5.4 Over Temperature Protection

The power supply will be protected against over temperature conditions caused by loss of fan
cooling or excessive ambient temperature. In an OTP condition the PSU will shutdown. When the
power supply temperature drops to within specified limits, the power supply shall restore power
automatically, while the +12Vsb remains always on. The OTP circuit must have built in margin such that
the power supply will not oscillate on and off due to temperature recovering condition.
Output Temperature [deg. C]
Temperature
Warning Shutdown Recovery

Ambient 60 65 50

Hotspot (SR) 96 102 89

Primary Hotspot (PFC) 104 110 97

Table 17 : Over Temperature Protection

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
Mar 23’2021 Suriyan.P Waralak Waralak ES-TDPS-2400HB A S2
SHEET 16 OF 74
 6 TIMING REQUIREMENTS

Vin

T1: TSB_On_delay T3: TSB_holdup

95% 95%

+12Vsb T3: TSB_Vout

T7: TVout_holdup

95% 95% 95%

+12V
T2: TVout_On_delay T6: TPWOK_Off T9: TPSON_On_delay

T4: TPWOK_On T5: TPWOK_holdup

PWOK

PSON
Vin On/off cycle PSON On/off cycle

Figure 1 : Timing Chart

MIN MAX
ITEM NAME DESCRIPTION
[mS] [mS]
T1 TSB_On_Delay Delay from Vin being applied to 12Vsb being within regulation. - 1500
T2 TVout_On_Delay Delay from Vin being applied to all output voltages being within regulation - 2500

T3 TSB_Vout Delay from 12Vsb being in regulation to O/Ps being in regulation at Vin turn on. 5 1000

T4 TPWOK_On Delay from output voltages within regulation limits to PWOK asserted at turn on. 100 500
T5 TPWOK_holdup Delay from loss of AC to de-assertion of PWOK. (70% loading) 13 -

T6 TPWOK_Off Delay from PWOK de-asserted to output voltages dropping out of regulation limits. 1 -

T7 TVout_holdup Main output voltages stay within regulation after loss of high line (70% loading;1680W) 14 -
T8 TSB_holdup Standby output voltages stay within regulation after loss of Vin. 70 -
T9 TPSON_On_Delay Delay from PSON# active to output voltages within regulation limits. 5 400
T10 TPSON_PWOK Delay from PSON# deactive to PWOK being deasserted. - 5

Table 18 : Timing Requirements

Note: The 100% loading T5, T7 measurement result as supported data.

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 7 I/O DEFINITIONS

All I/O signals must support hot-plugging of the PSU into the system and shall present a high
impedance to the system during installation. ESD diodes etc. internal to the PSU shall not bias any of
these signals in such a way as to cause a false logic state to be presented to the system. In addition,
many of the I/O signals are pulled up outside of the PSU (either on the system mid-plane or on the
canister(s). The PSU design must ensure that the presence of these pull-ups does not cause any back
drive or biasing issues in the system.

7.1 Logic I/O Signals

7.1.1 PSON (Input)

The PSON# signal is required to remotely turn on/off the main output of the power supply.
PSON# is and active low signal that turns on the main output power rail. When this signal is not
pulled low by the system or left open, the outputs (except the Standby output) turn off.
PSON# is pulled to a standby voltage by a pull-up resistor internal to the power supply.
Accepts an open collector/drain input from the system.
Signal Type
Pull up to Vsb located in the PSU
PSON = LOW PSU ON

PSON = HIGH or OPEN PSU OFF

Min. Max.

Logic level Low (PSU On) 0V 1.0V

Logic level High (PSU Off) 2.0V 3.46V

Source current, Vpson=low 4mA

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 7.1.2 PWOK (Output)
PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when input power has been removed for a time sufficiently long so that power supply
operation is no longer guaranteed, PWOK will be de-asserted to a LOW state.
Open collector/drain output from power supply.
Signal Type
Pull-up to VSB located in the power supply.
PWOK = LOW Power not OK

PWOK = HIGH Power OK

Min. Max.

Logic level Low 0V 0.4V

Logic level High 2.4V 3.46V

Source current, PWOK=low 400uA

Sink current, PWOK=high 2mA

A recommended implementation of the Power Ok circuits is shown below.

Note: the Power Ok circuits should be compatible with 5V pull up resistor (>10k) and 3.3V pull up
resistor (>6.8k)

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 7.1.3 SMBAlert (Output)
This signal indicates that the power supply is experiencing a problem that the user should investigate.
This shall be asserted due to Critical events or Warning events. The signal shall activate in the case of
critical component temperature reached a warning threshold, general failure, over-current, over-voltage,
under-voltage, failed fan. This signal may also indicate the power supply is reaching its end of life or is
operating in an environment exceeding the specified limits.
This signal is to be asserted in parallel with LED turning solid Amber or blink Amber.

Open collector / drain output from power supply.

Signal Type
Pull-up to VSB located in system.
SMBAlert = LOW Power Alert to system

SMBAlert = HIGH Power OK

Min. Max.

Logic level Low 0V 0.4V

Logic level High 3.46V

Source current, PWOK=low 4mA

Sink current,PWOK=high 50uA

7.1.4 A0 (Input)
PSU Module Address Line 0. This signal line is provided for determining the address for the specific
PSU FRU and SMBus address. A 10K Ohm pull up resistor pulled up to internal 3.3V.

7.1.5 A1 (Input)
PSU Module Address Line 1. This signal line is provided for determining the address for the specific
PSU FRU and SMBus address. A 10K Ohm pull up resistor pulled up to internal 3.3V.

7.1.6 Smart_On (Pin B22, enable by system)

This pin is used in the smart on mode control which all of Smart_On signals should be tied together.
When the pin is HIGH in the Smart_On mode, the slave power supply will enter the Smart Standby mode if

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system total loading under PSU’s pre-set load level. When the pin is LOW in the Smart_On mode, the
Smart Standby mode power supplies will work in normal redundancy mode.
Smart_On feature supports 1+1, 2+1, and 3+1 redundant configurations. It uses the PMBus
manufacturer specific command area to define PMBus commands for the system to communicate with the
power supplies for enabling, configuration, and monitoring.

7.1.7 RS- (Return Remote Sense, Pin A23)

The power supply has return remote sense (RS-) to regulate out ground drops in the system for the main
output voltage.
The return remote sense is able to regulate out a maximum of 200mV of drop on the ground output.

7.1.8 RS+ (+12V Remote Sense, Pin A24)

The power supply uses +12V remote sense (RS+) to regulate out +12V drops in the system for the main
output voltage. The
+12V remote sense is able to regulate out a maximum of 200mV of drop on the +12V output.

7.1.9 Present_N# (Pin B24)

This signal is an active low type signal and is connected to the power supply’s output ground via
100ohm resistor internally. The mating pin of this signal in system side should have a pull-up resistor which
limit the max. current 4mA to go through from this signal pin to the power supply. A LOW state on this
signal indicates the PSU is physically presents.

7.1.10 SDA (Pin A19)

SMBus Data: A 200K Ohm pull-up resistor pulled to internal +3.3V in the PSU.

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 7.1.11 SCL (Pin A20)
SMBus Clock: A 200K Ohm pull-up resistor pulled to internal +3.3V in the PSU.

7.1.12 Ishare (Pin B23)

This signal connects between the PSUs in the system and controls the current sharing between the
+12V output.

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 8 Power Supply Management Controller
The PMBus features included in this specification are requirements for power supplies use in server
systems. This specification is based on the PMBus specifications parts I and II.

8.1 PMBus Power Sourcing

The circuits inside the PSU shall derive their power from the standby output. For redundant power
supplies the device(s) shall be powered from the system side of the OR’ing device. The PMBus device
shall be on whenever input power is applied to the PSU or a parallel redundant PSU in the system.

8.2 Data Speed

The PMBUS device in the PSU shall operate at the full 100 kHz SMBus speed and avoid using clock
stretching that can slow down the bus. For example, the PSU can clock stretch while parsing a command
or a PSU servicing multiple internal interrupts or NACK may require some use of clock stretching.
Unsupported commands may respond with a NACK but must always set the communication error status
bit in STATUS_CML.
The PMBus device shall support SMBus cumulative clock low extend time (Tlow:sext) if < 25ms. This
requires the device to extend the clock time no more than 25ms between START and STOP for any given
message.

8.3 Bus Errors

The PMBus device shall support SMBus clock-low timeout (Ttimeout). This capability requires the
device to abort any transaction and drop off the bus if it detects the clock being held low for >25ms, and
be able to respond to new transactions 10ms later.
The device must recognize SMBus START and STOP conditions on ANY clock interval. (These are
requirements of the SMBus specifications, but are often missed in first-time hardware designs.) The
device must not hang due to 'runt clocks', 'runt data', or other out-of-spec bus timing. This is defined as
signals, logic-level glitches, setup, or hold times that are shorter than the minimums specified by the
SMBus specification. The device is not required to operate normally, but must return to normal operation

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once 'in spec' clock and data timing is again received.
Note if the device 'misses' a clock from the master due to noise or other bus errors, the device must
continue to accept 'in spec' clocks and re-synch with the master on the next START or STOP condition

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 8.4 Addressing
The PSU PMBus device address locations are shown below. For redundant systems there are up to
three signals.

Used Used Used Used

Address Used Not Used Not Used Not Used Not Used
System Addressing
0/0/0 0/0/1 0/1/0 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1
A2/A1/A0
PMBus device
B0h/B1h B2h/B3h B4h/B5h B6h/B7h B8h/B9h BAh/BBh BCh/BDh BEh/BFh
Read/Write s address
IPMI FRU device
A0h/A1h A2h/A3h A4h/A5h A6h/A7h A8h/A9h AAh/AAh ACh/ADh AEh/AFh
Read/Write address
Table 19 : PMBus and FRU device address

Note1: The addressing method uses the 7 MSB bits to set the address and the LSB to define whether a
device is reading or writing. The addresses defined above use 8 bits including the read/write bit.
Note2: The main pull up/down resistors shall located on system board

8.5 Packet Error Checking (PEC)

Firmware written for the PSMc shall support PEC (CRC-8).
8 2
The PEC shall be calculated based on SMBus Spec. 2.0 and latest PMBus Spec. It shall use the polynomial Y= x +x +x+1.
The slave shall also support Write transactions without PEC, which shall be detected automatically.

8.6 Supported PMBus Command Set

Command
Command Name R/W # of data bytes Comments
Code
00h PAGE R/W 1
01h OPERATION R/W 1 0x80h=On, 0x00h = OFF, default 00h
02h ON_OFF_CONFIG R/W 1 Default 15h
Send
03h CLEAR_FAULTS 0
Byte
05h PAGE_PLUS_WRITE Block Write Variable
06h PAGE_PLUS_READ Block Read Variable
19h CAPABILITY Read Byte 1 90h
BW/BR
1Ah QUERY process 1
call
BW/BR
1Bh SMBALERT_MASK process 2
call
20h VOUT_MODE R 1

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 Command
Command Name R/W # of data bytes Comments
Code
BW/BR
30h COEFFICIENTS process 5 M=01h, b=00h , R=00h
call
3Ah FAN_CONFIG_1_2 R/W 1 Default “duty control mode”
3Bh FAN_COMMAND_1 R/W 2
40h VOUT_OV_FAULT_LIMIT R 2 >14V
44h VOUT_UV_FAULT_LIMIT R 2 <10V
118.875A (low line)
46h IOUT_OC_FAULT_LIMIT R/W 2
234.75A (high line)
109A (low line)
4Ah IOUT_OC_WARN_LIMIT R/W 2
224.75A (high line)
51h OT_WARN_LIMIT R/W 2 60C
13.125 (low line)
5Dh IIN_OC_WARN_LIMIT R/W 2
14.5 (high line)
1308W (low line)
6Ah POUT_OP_WARN_LIMIT R/W 2
2700W (high line)
1450W (low line)
6Bh PIN_OP_WARN_LIMIT R/W 2
2900W (high line)
79h STATUS_WORD R/W 2
7Ah STATUS_VOUT R/W 1
Bit 7 Vout OV fault
Bit 4 Vout UV fault
7Bh STATUS_IOUT R/W 1
Bit 7 Iout OC fault
Bit 5 Iout OC warning
Bit 1 Pout OP fault
Bit 0 Pout OP warning
7Ch STATUS_INPUT R/W 1
Bit 5 Vin UV warning
Bit 4 Vin UV fault
Bit 3 Unit off for insufficient input
Bit 1 Iin OC warning
Bit 0 Pin OP warning
7Dh STATUS_TEMPERATURE R/W 1
Bit 7 OT fault
Bit 6 OT warning
7Eh STATUS_CML R/W 1
Bit 7 Command fault
Bit 6 Data fault
Bit 5 PEC fault
00: No input
80h STATUS_MFR_SPECIFIC R 1 01: AC (Normal Airflow)
02: 240V HVDC (Normal Airflow)
81h STATUS_FANS_1_2 R/W 1
Bit 7 Fan 1 Fault <255 RPM
Bit 6 Fan 2 Fault <255 RPM

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 Command
Command Name R/W # of data bytes Comments
Code
Bit 5 Fan 1 Warning *
Bit 4 Fan 2 Warning *
Bit 3 Fan 1 speed overridden "0" = self control, "1" = overridden
Bit 2 Fan 2 speed overridden "0" = self control, "1" = overridden
86h READ_EIN BR 5
87h READ_EOUT BR 5
88h READ_VIN R 2
89h READ_IIN R 2
8Bh READ_VOUT R 2
8Ch READ_IOUT R 2
8Dh READ_TEMPERATURE_1 R 2 Ambient
8Eh READ_TEMPERATURE_2 R 2 Secondary Hotspot (SR)
8Fh READ_TEMPERATURE_3 R 2 Primary Hotspot (PFC)
90h READ_FAN_SPEED_1 R 2
91h READ_FAN_SPEED_2 R 2
96h READ_POUT R 2
97h READ_PIN R 2
98h PMBUS_REVISION R 1 "22h"
99h MFR_ID BR/BW Variable "Delta "
9Ah MFR_MODEL BR/BW 13 "TDPS2400HBA"
9Bh MFR_REVISION BR/BW 3
9Ch MFR_LOCATION BR/BW Variable "Thailand"
9Dh MFR_DATE BR/BW Variable
9Eh MFR_SERIAL BR/BW 15
9Fh APP_PROFILE_SUPPORT BR Variable "04h"
A0h MFR_VIN_MIN R 2 90Vac
A1h MFR_VIN_MAX R 2 264Vac
15A (low line)
A2h MFR_IIN_MAX R 2
15A (high line)
1250W (low line)
A3h MFR_PIN_MAX R 2
2700W (high line)
A4h MFR_VOUT_MIN R 2 11.4V
A5h MFR_VOUT_MAX R 2 12.6V
83.35A (low line)
A6h MFR_IOUT_MAX R 2
200A (high line)
1000W (low line)
A7h MFR_POUT_MAX R 2
2400W (high line)
A8h MFR_TAMBIENT_MAX R 2 50
A9h MFR_TAMBIENT_MIN R 2 0
AAh MFR_EFFICIENCY_LL BR 14 At 20%/50%/100% loading
C0h MFR_MAX_TEMP_1 R 2 AMB Waring
C1h MFR_MAX_TEMP_2 R 2 Hotspot Warning
D0h SmartOn_Config R/W 1
[LSB] [MSB], 0x64 0x00 means 100%
D1h MFR_FAN_Duty R 2
duty

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 Command
Command Name R/W # of data bytes Comments
Code
D4h MFR_HW_COMPATIBILITY R/W
MFR_FWUPLOAD_CAPBILI
D5h R/W
TY
D6h MFR_FWUPLOAD_MODE R/W
D7h MFR_FWUPLOAD R/W
D8h MFR_FWUPLOAD_STATUS R/W
D9h MFR_FIRMWARE_REV R/W
DCh MFR_BLACKBOX BR
MFR_REAL_TIME_BLACKB
DDh R/W
OX
DEh MFR_SYSTEM_BLACKBOX R/W
E0h MFR_CLEAR_BLACKBOX R/W

Table 20 : Supported PMBus commands Set

8.7 Resetting of Status Bits

The STATUS_ commands shall be reset only by the below methods. If the event is still present that
caused the assertion of the status bit, the bit shall stay assert after clearing.

• Writing a ‘1’ to any given bit location shall reset only that bit of the command.

• Sending a CLEAR_FAULTS command to the PSU shall reset all STATUS_ bits to ‘0’.

CLEAR_FAULTS shall clear all STATUS commands at a given PAGE if PAGE command is supported.
If the PAGE is set to FFh; all STATUS bits in all PAGEs shall be cleared.

• Cycling input power OFF for 1 second or more then ON shall reset all STATUS_ bits to ‘0’.

• Systems with redundant power supplies where only one of the supplies cycle input power OFF/ON;

the power cycled PSU shall reset the STATUS_ bits to ‘0’ only when powered back ON. If the PSU is

kept OFF, the STATUS_ bits shall not be reset.

• Cycling the PSON# signal from de-asserted to asserted shall reset the STATUS_ bits to ‘0’. The bits

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shall be reset only on the assertion of PSON#; not the de-assertion.

Note: exception for Over Current Fault shutdown; PSON# cycling shall NOT reset the over current fault
bit or cause the power supply to restart. Only a cycle of the input power shall reset the over current fault
bit and allow the PSU to power on again.

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 8.8 SMBALERT_MASK (1Bh)
This allows the system to mask events from asserting the SMBAlert# signal and to read back this
information from the PSU. SMBALERT_MASK command can be used with any of the supported
STATUS events. The events are masked from asserting SMBAlert# by writing a ‘1’ to the associated
STATUS bits. The SMBALERT_MASK command is used in conjunction with the PAGE_PLUS
command and STATUS_ commands. It is not supported for masking the Non-PAGE’d STATUS_
commands.

8.8.1 Reading Mask Values using PAGE_PLUS, Block Write Block Read Process Call with
PEC

Figure 2 : SMBALERT_Mask - Read Mark Value

8.8.2 Writing Mask Values using PAGE_PLUS, Block Write with PEC

Figure 3 : SMBALERT_Mask - Write Mark Value

Noted: STATUS_WORD is not used with SMBALERT_MASK. Only the 'root' event biits are used to control the SMBAlert signal.

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 8.9 PMBus Commands Preciseness and Data Format
For the following PMBus commands a minimum preciseness/accuracy for voltage, current and power
readings and settings must be better than ±5% in the 10%-100% load range and must follow the tier 2 EPA
for server guideline. The maximum deviation for the ambient temperature is +/- 4°C. Tested at nominal
voltage and 25°C.
Type Condition Criteria
Pin < 200W +/- 10W
Read_Pin
Pin ≥ 200W +/- 5%
< 10% load +/- 5%
Read_Vin, Read_Vout
> 10% load +/- 5 %
Iin_rms < 1.6A +/- 0.08A
Read_Iin
Iin_rms ≥ 1.6A +/- 5%
10~20% load +/- 10%
Read_Iout
>20% load +/- 5%
10~20% load +/- 10W
Read_Pout
> 20% load +/- 5%
Table 21 : Reporting Accuracy

Preferred data format is the “Linear Data Format” as specified by PMBus specification Part II version 1.2.

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 9 FRU Requirements
The FRU data format shall be compliant with the IPMI ver.1.0 (per rev.1.1 from Sept.25, 1999)
specification. The following is the exact listing of the EEPROM content. During testing this listing shall
be followed and verified.

9.1 FRU Device Protocol

The FRU device will implement the same protocols as the commonly used AT24C02 device, including
the Byte Read, Sequential Read, Byte Write, and Page Read protocols.

9.2 FRU Data Format

The information to be contained in the FRU device is shown in the following table.
Area Type Description
0000h Common Header As defined by the FRU document
0001h Internal Use Area Not required, do not reserve
0004h Chassis Info Area Not applicable, do not reserve
0005h Multi record Area
0008h Internal use Area
001Bh Manufacturer Name DELTA
0021h Product Name TDPS2400HB A
0030h Product part/model number TDPS2400HB A
003Fh Product Version
0045h Product Serial Number {Defined at time of manufacture}
0055h Asset Tag {Not used, code is zero length byte}
0056h FRU File ID {Not required}
0057h PAD Bytes {Address as necessary to allow for 8-byte offset to next area}
0060h Field Name (PS Info) Field Information Definition
0065h Overall Capacity [watts]
0066h Overall Capacity [watts] 2400W
0067h Peak VA– LSB [watts]
0068h Peak VA – MSB [watts] 2400W
0069h Inrush current (Amp) 35A
006Ah Inrush interval (mSec) 10mS
006Bh Low end input voltage range 1-LSB [10mV]
006Ch Low end input voltage range 1-MSB 100Vac
006Dh [10mV]
High end input voltage range 1-LSB
006Eh [10mV]
High end input voltage range 1-MSB 127Vac
006Fh [10mV]
Low end input voltage range 2-LSB [10mV]
0070h Low end input voltage range 2-MSB 200Vac
0071h [10mV]
High end input voltage range 2-LSB 240Vac
0072h [10mV]
High end input voltage range 2-MSB 240Vac
0075h [10mV]
A/C dropout total. [mSec] 10mS
0076h Binary flags Set for. Hot Swap support,Auto switch, and PFC

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ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
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SHEET 32 OF 74
 0077h Peak Watage – LSB [watts]
0078h Peak Watage – MSB [watts] 2600W
0079h Combined wattage None
007Ch Predictive fail tacho support Supported
007Dh Record Type 01 DC Output – 12V Nominal, Min. and Max. Voltage, Ripple noise, Min and Max output current[mA]
008Fh Record Type 01 DC Output – 12Vsb Nominal, Min. and Max. Voltage, Ripple noise, Min and Max output current[mA]

Table 22 : FRU Requirement

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ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
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WITHOUT PERMISSION. TDPS-2400HB A
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 10 COMMON CRPS REQUIREMENTS
10.1 Smart On
Redundant power supplies in a system shall power ON or OFF depending upon loading state. Power supply that or OFF (in the
Cold Standby state) shall power on quickly to maintain full redundancy in the system.

10.1.1 Hardware Connection

Before enabling Smart On function, make sure pin B22 (SMART ON) on output golden finger of each
PSU is connected together.

10.1.2 Configuring SmartOn with SMART_ON_CONFIG (0xD0h)

The manufacturer specific command MFR_SPECIFIC_00 is used to configure the operating state of
the power supply related to SmartOn. We will call the command SMART_ON_CONFIG (D0h).
Below is the definition of the values used with the Read-Write Byte SMBus protocol with PEC.

Value State Description

00h Standard Redundancy Turns the power supply ON into standard redundant load sharing mode.
Defines this power supply to be the one that is always ON in a
01h SmartOn Active
Smart On configuration.

02h Smart Standby 1 Defines the power supply that 1st turn on in a Smart_On configuration as the load increases.

03h Smart Standby 2 Defines the power supply that 2nd turn on in a Smart_On configuration as the load increases.

04h Smart Standby 3 Defines the power supply that 3rd turn on in a Smart_On configuration as the load increases.

Table 23 : Smart On Configuration

The default state of power supply is in Standard Redundancy mode. Power supply need to be re-
specified a state whenever initial power on or any power supply in the system is in fault situation.
The SMART_ON_CONFIG command will reset to 00h (Standard Redundancy) when any fault or
over current happened. The faults include input loss, over hot spot temperature, over ambient temperature,
+12V short internally (under voltage), +12V over voltage, fan locked, D2D controller soft-start short.

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ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
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WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
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 Fixgure 4: 4xPSU Smart On function chart

10.1.3 Smart Standby Power Supply Operating State

A power supply is put into Smart Standby whenever PSON# is asserted, and SMART_ON_CONFIG
value is set to 02h.
In the Smart Standby mode the power supply must:
• Power ON when Smart_On bus is driven LOW
• Keep PWOK asserted
• No PMBus fault or warning conditions reported via STATUS commands
• keep all fans rolling
• LED is green blinking

10.1.4 Powering on Smart Standby supplies to maintain best efficiency

Power supplies in Smart Standby state shall monitor the shared voltage level of the load share signal to
sense when it needs to power on. Depending upon which position the system defines that power supply to
be in the Smart Standby configuration; will slightly change the load share threshold that the power supply
shall power on at.

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MODEL NO. :
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WITHOUT PERMISSION. TDPS-2400HB A
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 10.1.5 Powering on Smart Standby supplies during a fault or over current condition
Some warnings happen or 12V output shutdown due to any fault. When an active power supply
asserts, all parallel power supplies in Smart Standby mode shall power on immediately.
The trigger condition:
 12V OC fault happens
 12V OVP fault
 12V UVP
 OTP warning/fault
 Fan speed warning/ fault
 AC loss (lower than 74V +/-5V)
 Send 00h to PMBus D0h command
 PSON# de-asserted
When an active power supply asserts, all parallel power supplies in Smart Standby mode shall power
on immediately.

10.1.6 The Way to Enable SmartOn Function

Here are the steps (1+1) to put PSU into smart on mode. PSU which is assigned as smart on standby
can operate in a power-off state and turn on main power if necessary.

Step1: Make sure every PSU has AC power cord applied. Use write byte command to set command
0xD0 for each PSU to has it own role (must one PSU as active role).
The command format for Smart On function will be as following example.
 B0 in smart_on_active (S B0 w D0 01 PEC P)
 B2 in smart_on_standby (S B2 w D0 02 PEC P)
Step 2: PSU will enter smart slave mode once the load is lower than the corresponding trigger point.
Step3: If SMART_ON signal falls to low, all PSU will turn on the main power and reset smart_config
to 0x00 (standard redundancy). System needs to re-assign the roles for all PSU to enable smart on
function again.

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MODEL NO. :
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 10.2 SMBAlert#
The SMBAlert# signal may be asserted by the PSU for any of the supported STATUS events. The
events that control SMBAlert# can be masked using the SMBALERT_MASK command.
By default the SMBAlert# signal is asserted for the following cases.
 STATUS_INPUT (UV Fault bit): input voltage drops below the fault threshold for > 2ms.
 STATUS_IOUT (Iout OC Warning bit): Output current exceeds the PSU capability but PSU has
not shutdown.
 STATUS_TEMPERATURE (OT Warning): Thermal sensor for PS inlet temperature or on a hot
spot inside the PSU has exceeded its warning temperature

Item Description PMBus command Min. Max

Talert_input Timing from input voltage dropping to 0VAC STATUS_INPUT UV Fault 2mS 5mS

Tover_temp to SMBAlert#
Hot spot going threshold
temp > warning low 1 Sec
STATUS_TEMPERATURE
Ambient temp > warning threshold Over temp warning

Table 24 : SMBAlert Timing Requirements

10.2.1 Setting and Resetting the SMBAlert# signal

The SMBAlert# signal shall be asserted whenever any un-masked event has occurred. This is a level
detected event. Whenever the event is present SMBAlert# shall be asserted. The SMBAlert# signal shall
not de-assert at any time if the event that has caused the assertion is still present..

The SMBAlert# signal shall be cleared and re-armed by the following methods.
 Clearing STATUS bits causing the asserted SMBAlert# signal.
 Power cycling with PSON or with input power
 Masking the event with SMBALERT_MASK

10.3 In-System Firmware Update

This specification defines the common architecture for in-system power supply firmware updates. It is
required that the FW in the main microcontroller on the secondary side of the power supply must be able to
be updated in the system using the In-System Firmware Update feature while in the ON state (i.e. with AC
power present and PSON# asserted). It is desired that any other microcontroller in the power supply also be
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MODEL NO. :
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WITHOUT PERMISSION. TDPS-2400HB A
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able to be updated with this same process (example: primary side microcontroller); however, this is not a
requirement at this time.

10.3.1 FW Image Mapping

The power supply firmware image shall be made up of two parts; 1)Boot loader; 2) Main program.
The system shall contain a backup of the power supply image in its BMC whenever updating the FW to the
power supply.
1. Boot Loader: This is the part of the power supply firmware that is never updated by the system.
The power supply shall always be able to recover and power ON into the boot loader mode no matter the
state of the power supply’s main program. This code shall support the In-System FW update code and basic
power supply functions to power ON/OFF, fan cooling, and protections (UV, OV, OC).
2. Main Program: This is the fully functional power supply program space. There is no requirement
to keep a backup image of this code in the power supply since a copy of the power support FW image shall
always for kept in the system’s BMC.

10.3.2 Summary of Commands supported in Boot Loader mode

When the power supply is in FW Upload mode the following commands shall be supported.
Code Command SMBus Transaction Type
19h CAPABILITY Read Byte w/PEC
1Ah QUERY (used with any command) Block Write Block Read Process Call w/ PEC
98h PMBUS_REVISION Read Byte w/PEC
9Ah MFR_MODEL Block Read
D4h MFR_HW_COMPATIBILITY Read Word w/PEC
D5h MFR_FWUPLOAD_CAPABILITY Read Byte w/PEC
D6h MFR_FWUPLOAD_MODE Read/Write Byte w/PEC
D7h MFR_FWUPLOAD Bloack Write w/ PEC (size = block size from image header)
D8h MFR_FWUPLOAD_STATUS Read Word w/PEC
D9h MFR_FW_REVISION Block Read w/PEC (3 bytes)
Table 25 : Commands Supported in Boot Loader mode

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MODEL NO. :
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 10.3.3 Summary of Capabilities supported in Boot Loader mode
Basic Function Operating Capability

Fan control Fan can run at a high fixed speed to make sure power supply is cooled in the system for the duration of the FW update.
PWOK The PWOK signal must still function properly during power on / off cycles to reset the system
PSON# The PSON# signal must still be able to power ON/OFF the power supply.
UV Under voltage protection
OV Over voltage protection
OC Over current protection

Table 26 : Capabilities Supported in Boot Loader mode

10.3.4 Operating mode during and after firmware update

Firmware update mode in ON state with no power cycle needed:
Power supply may be able to support FW upload in the ON state. The new FW will take effect once it
is taken out of FW upload load.
Bad image after firmware update:
The power supply must always be able to power on in the boot loader mode with minimal operating
capabilities even if the FW image sent to the power supply is bad or corrupt. If in this mode the power
supply must be able to still enter the FW upload mode to upload a proper FW image to the PSU.

Firmware Image Header

Byte # Description
Byte 1 CRC LowByte
Byte 2 CRC HighByte
Byte 3-10 Image Information
Byte 11~23 TDPS2400HBA
Byte 24 FW_MAJOR (Bit 7: down revision control bit, Bit 0-6: Major version).
Byte 25 FW_MINOR_PRIMARY (not used by system)
Byte 26 FW_MINOR_SECONDARY
Byte 27 HW_COMPATIBILITY_FIRST
Byte 28 HW_COMPATIBILITY_SECOND
Byte 29 BLOCK SIZE LowByte
Byte 30 BLOCK SIZE HighByte
Byte 31 Write Time LowByte
Byte 32 Write Time HighByte
Table 27 : Firmware Image Header

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 10.3.5 Firmware Update Flowchart
IMPORTANT!
· PSU may be in standby mode or ON mode during FW
update process
· If the FW update process is interrupted at any point during
the process; the PSU must always be able to return to the
boot loader code.
BMC uses these commands to
· The PSU must always check that the application program is
determine of FW needs updating:
MFR_FW_REVISION BMC determines PSU stays in not corrupted before starting to run from the application
MFR_MODEL PSU FW needs No application program program
MFR_FW_UPLOAD_MODE
MFR_HW_COMPATIBILITY
updating? mode
· During the FW upload process the PSU must always
MFR_FW_UPLOAD_CAPABILITY respond to any communication on the bus; acknowledging
its address and the supporting commands without holding
Yes the bus. For unsupported boot loader commands the PSU
may respond with Not Acknowledge or 00h.
BMC resets retry · BMC must configure correct addresses into ME at BMC
counter startup to avoid bad PSU address config if AC power is lost
or BMC is reset while the PSU update is in progress

BMC put PSU into Boot Load mode Increment retry

sends 0x01 to MFR_FWUPLOAD_MODE count

Delay 1s to allow PSU to enter

FW update mode

PSU starts to run off of Boot Loader code No

(PSU may erase application memory at this time but it is
preferred to wait for the MFR_FW_UPLOAD command
to start erasing the application program)
EXIT

BMC reads
Max retry reached? Yes
MFR_FWUPLOAD_ No
(default = 3)
MODE = 0x01?

Yes

BMC reads FW
image header in
BMC for block size
and delay time

BMC sends
MFR_FWUPLOAD & 1 st
block of image

PSU writes CRC16 (byte 1 &

2 of image) to memory

PSU erases part of

application memory &
write the 1st image block

Write time delay BMC sets “config

error” offset of PSU
status sensor

BMC sends
MFR_FWUPLOAD &
nextt block of image

PSU erases part of application memory

& writes the next block of image
BMC reads
No MFR_FW_UPLOAD Yes
_MODE = 0
Write time delay

(optional) BMC reads

MFR_FW_UPLOAD_STATUS

(optional) Block
No
received OK?
No
PSU starts running
BMC writes 00h to PSU stays in boot
from application
MFR_FW_UPLOAD_MODE loader mode
Last data program
block?

No No
Yes

Max retry reached? PSU application

Yes Yes
Default = 3 program OK?
PSU verifies that the image has
been transferred properly by
checking the CRC16 value

BMC reads
MFR_FW_UPLOAD_STATUS
PSU verifies Application Program is
not corrupted with CRC16 value

Full image received No

successfully?

Yes
BMC writes 00h to
MFR_FW_UPLOAD_MODE

Figure 5 : PSU Upload Flowchart

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MODEL NO. :
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 PSU verifies Application Program is
PSU starts running
not corrupted using CRC16 value PSU application
PSU powers ON from application
saved in PSU for the application program OK?
program
program image

PSU stays in boot

loader mode

Figure 6 : PSU flow during powering ON

10.3.6 Firmware Update related commands

10.3.6.1 MFR_HW_COMPATIBILITY (0xD4h)

Format: Read Word
Bytes Value Description
ASCII code for first
LSB letter/number of the PSU
HW compatibility. This is a COMPATIBILITY value used to tell if there are
any changes in the FW that create an incompatibility with the
ASCII code for FW. This value only changes when the PSU HW is changed
second letter/number of creating an incompatibility with older versions of FW.
MSB
the PSU HW
compatibility.

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 10.3.6.2 MFR_FWUPLOAD_CAPABILITY (0xD5h)
Format: Read Byte
The system can read the power supply’s FW upload mode capability using this command. For any given
power supply; more than one FW upload mode may be supported. The supported FW upload mode(s)
must support updating all available FW in the power supply.
Bit Value Description
0 1 = PSU support FW uploading in standby
For future use
(for future use) mode only

1 1 = PSU supports FW uploading in ON state;

but all the new FW will not take effect until a For future use
(for future use) power cycle with PSON.
Method used for updating the
1 = PSU supports FW uploading in the ON application program in the power
2
state and no power cycle needed supply

3-7 Reserved

10.3.6.3 MFR_FWUPLOAD_MODE (0xD6h)

Format: Read/Write Byte
Bit Value Description
Writing a 1 puts the power supply into firmware
upload mode and gets it ready to receive the 1st image
block via the MFR_FW_UPLOAD command. The
system can use this command at any time to restart
sending the FW image.
Writing a 0 puts the power supply back into normal
0 = exit firmware upload mode operating mode.
0
1 = firmware upload mode Writing a 1 restarts
This command will put the PSU into standby mode
if the PSU supports FW update in standby mode only.
If the power supply image passed to the PSU is
corrupt the power supply shall stay in firmware upload
mode even if the system requested the PSU to exit the
FW upload mode.
1-7 Reserved

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 10.3.6.4 MFR_FWUPLOAD (0xD7h)
Format: Block Write (block = size as defined by the image header)
Bytes Value Description
Command used to send each block of the FW image.
Block
Header should follow the format described in section 0.
size Image header &
defined in image data The image shall contain block sequencing numbers to
header make sure the PSU puts the right data blocks into the right
memory space on the PSU MCU.

10.3.6.5 MFR_FWUPLOAD_STATUS (0xD8h)

Format: Read Word
At any time during or after the firmware image upload the system can read this command to determine
status of the firmware upload process.
Reset: all bits get reset to ‘0’ when the power supply enters FW upload mode.
Bit Description
0 1 = Full image received successfully
1 = Full image not received yet. The PSU will keep this bit asserted until the full image is
1
received by the PSU.
1 = Full image received but image is bad or corrupt. Power supply can power ON, but only
2
in ‘safe mode’ with minimal operating capability.
3
(for 1 = Full image received but image is bad or corrupt. Power supply can power ON and
future support full features.
use)
1 = FW image not supported by PSU. If the PSU receives the image header and determines
4 that the PSU HW does not support the image being sent by the system; it shall not accept the
image and it shall assert this bit.
5–
Reserved
15

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 10.3.6.6 MFR_FW_REVISION (0xD9h)
Format: Block Read, 3 bytes
Byte Value Description
0 0 - 255 Minor revision; secondary
1 0 - 255 Minor revision; primary
Bit 7:"1"->
Down grading of PSU FW has to be avoided. System
BMC can elect to ignore this bit if needed, but recommended to
follow.
2 0 - 255
Bit 7:"0"
No restriction in downgrading the PSU FW. BMC can
update the PSU FW to be in sync with its known version.
Bit 0-6: Major revision

10.4 Diagnostic “Black Box”

This specification defines the requirements for power supplies with PMBus capability to store PMBus
and other data into non-volatile memory inside the power supply. The data shall be saved to non-volatile
memory upon a critical failure that caused the power supply to shutdown. The data can be accessed via the
PMBus interface by applying power to the +12Vst pins. No AC power need to be applied to the power
supply.

10.4.1 Black Box Data Content

Data is saved to the Black Box for the following fault events:
 General fault
 Over voltage on output
 Over current on output
 Loss of AC input
 Input voltage fault
 Fan failure
 Over temperature

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MODEL NO. :
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 10.4.2 Black Box Events
There are two types of data saved in the black box; 1) System Tracking Data, 2) Power supply event
data.
System tracking data is saved to the Black Box whenever the system powers ON or when a power
supply is added to the system.

10.4.3 Black Box Process

 System writes system tracking data to the power supply RAM at power ON
 System writes the real time clock data to the PSU RAM once every ~5 minutes
 Power supply tracks number of PSON and AC power cycles in EEPROM
 Power supply tracks ON time in EEPROM
 Power supply loads warning and fault event counter data from EEPROM into RAM
 Upon a warning event; the PSU shall increment the associated counter in RAM.
 Upon and fault event the PSU shall increment the associated counter in RAM
 Upon a fault event that causes the PSU to shutdown all event data in the PSU’s RAM is saved to
event data location N in the power supply’s EEPROM. This data includes the real time clock, number of
AC & PSON power cycles, PSU ON time, warning event counters and fault event counters.

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MODEL NO. :
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 10.4.4 BlackBox related Commands

10.4.4.1 MFR_BLACKBOX (0xDCh)

Format: Block Read with PEC (237 bytes)
Number
Type Item Description
of Bytes
The system will write its Intel part
number for the system top assembly to the
System top assembly number 10
power supply when it is powered ON. This
is 9 ASCI characters.
The system shall write the system serial
number to the power supply when it is
System serial number 10
powered ON. This include the serial number
and date code.
The system will write the motherboard
Intel part number for the assembly to the
Motherboard assembly number 10
power supply when it is powered ON. This
is 9 ASCI characters.
The system shall write the
motherboard’s serial number to the power
System Motherboard serial number 10
supply when it is powered ON. This
Tracking
includes the serial number and date code.
Data
Total on time of the power supply with
Present total PSU ON time 3
PSON asserted in minutes. LSB = 1 minute.
Total number of times the power supply
powered OFF then back ON due to loss of AC
power. This is only counted when the power
Present number of AC power cycles 2
supply’s PSON# signal is asserted. This
counter shall stay at FFFFh once the max is
reached.
Total number of times the power supply
is powered OFF then back ON due to the
Present number of PSON power PSON# signal de-asserting. This is only
2
cycles counted when AC power is present to the
power supply. This counter shall stay at
FFFFh once the max is reached.
The power supply shall track these time
and power cycle counters in RAM. When
Time Stamp (11 bytes)
the a black box event occurs the data is saved
into the Black Box.
Total on time of the power supply in
PSU total power on time 3
minutes. LSB = 1 minute.
This time stamp does not need to
generated by the power supply. The system
Event data (N) rights a real time clock value periodically to
Most recent event the power supply using the
MFR_REAL_TIME command.
Real Time Clock Data from
Format is based on IPMI 2.0. Time is
System 4
an unsigned 32-bit value representing the
(reserved for future use)
local time as the number of seconds from
00:00:00, January 1, 1970. This format is
sufficient to maintain time stamping with 1-
second resolution past the year 2100. This is
based on a long standing UNIX-based

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ELECTRONICS, INC. AND SHALL NOT BE REPRODUCED OR USED AS THE
MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
Date Drawn Checked Approved DOCUMENT NO. : REV.
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 Number
Type Item Description
of Bytes
standard for time keeping, which represents
time as the number of seconds from 00:00:00,
January 1, 1970 GMT. Similar time formats
are used in ANSI C
Number of times the power supply
powered OFF then back ON due to loss of AC
Number of AC power cycles 2 power at the time of the event. This is only
counted when the power supply’s PSON#
signal is asserted.
Number of times the power supply is
powered OFF then back ON due to the
Number of PSON power
2 PSON# signal de-asserting at the time of the
cycles
event. This is only counted when AC power
is present to the power supply.
The power supply shall save these
PMBus values into the Black Box when a
PMBus Registors (22 bytes) black box event occurs. Fast events may be
missed due to the filtering effects of the
PMBus sensors.
STATUS_WORD 2
STATUS_IOUT 1
STATUS_INPUT 1
STATUS_TEMPERTATURE 1
STATUS_FAN_1_2 1
READ_VIN 2
READ_IIN 2
READ_IOUT 2
READ_TEMPERATURE_1 2
READ_TEMPERATURE_2 2
READ_FAN_SPEED_1 2
READ_PIN 2
READ_VOUT 2
The power supply shall track the total
number for each of the following events.
These value shall be saved to the black box
Event Counters (5 bytes)
when a black box event occurs. Once a value
has reached 15, it shall stay at 15 and not
reset.
AC shutdown due to under The power supply shall save a count of
Lower ½
voltage on input these critical events to non-volatile memory
Thermal shutdown Upper ½ each time they occur. The counters will
increment each time the associated STATUS
Over current or over power bit is asserted.
Lower ½
shutdown on output
General failure shutdown Upper ½
Fan failure shutdown Lower ½

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MODEL NO. :
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 Number
Type Item Description
of Bytes
Shutdown due to over
Upper ½
voltage on output
The power supply shall save into RAM a count
Input voltage warning; no of these warning events. Events are count
Lower ½
shutdown only at the initial assertion of the event/bit. If
the event persists without clearing the bit the
Thermal warning; no counter will not be incremented. When the
Upper ½
shutdown power supply shuts down it shall save these
warning event counters to non-volatile memory.
Output current power The counters will increment each time the
Lower ½
warning; no shutdown associated STATUS bit is asserted.
Fan slow warning; no
Upper ½
shutdown
Event data (N-1) 38
Event data (N-2) 38
Event data (N-3) 38
Event data (N-4) 38

Table 28 : Blacbox Content

10.4.4.2 MFR_REAL_TIME_BLACK_BOX (0xDDh)

Format: Write/Read Block with PEC (4 bytes)
The system shall use this command to periodically write the real time clock data to the power supply.
Format is based on IPMI 2.0. Time is an unsigned 32-bit value representing the local time as the
number of seconds from 00:00:00, January 1, 1970. This format is sufficient to maintain time stamping with
1-second resolution past the year 2100. This is based on a long standing UNIX-based standard for time
keeping, which represents time as the number of seconds from 00:00:00, January 1, 1970 GMT. Similar
time formats are used in ANSI C.

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MODEL NO. :
BASIS FOR THE MANUFACTURE OR SELL OF APPARATUSES OR DEVICES
WITHOUT PERMISSION. TDPS-2400HB A
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 10.4.4.3 MFR_SYSTEM_BLACK_BOX (0xDEh)
Format: Write/Read Block with PEC (40 bytes). Low byte first.
The system uses this command to write the following data to the PSU.
Byte Value Description
1-10 System top assembly number Low bytes
11-20 System serial number
21-30 Motherboard assembly number
31-40 Motherboard serial number High bytes

10.4.4.4 MFR_BLACKBOX_CONFIG (0xDFh)

Format: Read/Write Byte with PEC
Byte Value Description
Writing a 1 enables the power supply with black box
function. Writing a 0 disables the power supply black box
0 = disable black box function.
function
0 The state of MFR_BLACKBOX_CONFIG shall be saved in
1 = enable black box non-volatile memory so that it is not lost during power cycling.
function
Intel shall receive the power supply with the black box function
enabled; bit 0 = ‘1’.
1-7 reserved

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MODEL NO. :
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 10.4.4.5 MFR_CLEAR_BLACKBOX (0xE0h)
Format: Send Byte with PEC

Figure 7 : Send byte protocol with PEC

The MFR_CLEAR_BLACKBOX command is used to clear all black box records simultaneously.
This command is write only. There is no data byte for this command.

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MODEL NO. :
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 11 MECHANICAL OUTLINE
11.1 Indicator LEDs
The PSU shall support indicator LED on the front of the unit to indicate PSU status.

11.1.1 LED Locations

The indicator LED shall be located next to the power inlet connector and shall be arranged as shown in below:

Figure 8 : Indicator LED Location

11.1.2 LED Wavelength

The power supply shall use a bi-color LED; Amber & Green. Below are table showing the LED states for each power supply
operating state and the LED’s wavelength characteristics. An example bi-color LED that meets the below characteristics is
Kingbright WP59-CN99. (or equivalent)

11.1.3 LED Behaviors

Power Supply Condition LED State
Output ON and OK GREEN
No AC power to all power supplies OFF
PSU standby state AC present / Only 12Vsb on 1Hz Blink GREEN
AC cord unplugged or AC power lost; with a second power supply in parallel still with AC input power. AMBER
Power supply critical event causing a shutdown; failure, over current, short circuit, over voltage, fan failure,
AMBER
over temperature
Power supply warning events where the power supply continues to operate; high temp, high power, high
1Hz Blink Amber
current, slow fan.
Power supply FW updating 2Hz Blink GREEN
Table 29 : LED Behaviors

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 11.2 Handle Retention
The power supply shall have a handle to assist extraction. The module shall be able to be inserted and extracted without the
assistance of tools. The power supply shall have a latch which retains the power supply into the system and prevents the power
supply from being inserted or extracted from the system when the AC power cord is pulled into the power supply. The handle shall
protect the operator from any burn hazard.

11.3 Output Pin Assignment

The power supply shall use a card edge output connection for power and signal that is compatible with a 2x25 Power Card Edge
connector (equivalent to 2x25 pin configuration of the FCI power card connector 10147875-001LF).

Figure 9 : Output Pin assignment

Pin Number Type Signal Name Description

A1-A9 GND GND Output Return - Ground for output.

A10-A18 Power +12V +12V Output – PSU +12V output

A19 Signal SDA I2C Interface Data – bi-directional I2C serial data line.

A20 Signal SCL I2C Interface Clock – serial clock for I2C communications.

A21 Signal PSON_L PSU Enable pin -

A22 Signal SMBAlert_L

A23 Signal Return Remote Sense Return Sense Pin

A24 Signal 12V_Remote Sense+ +12V Output Remote Sense Pin

A25 Signal PWOK Power Good signal

B1-B9 GND GND Output Return - Ground for output.

B10-B18 Power +12V +12V Output – PSU +12V output

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 B19 Signal A0 I2C Addressing pin - pull up/down by system

B20 Signal A1 I2C Addressing pin - pull up/down by system

+12V Standby Power Output – PSU Standby Power output. This
B21 Signal +12Vsb output will be active whenever the input power is within acceptable
range
B22 Signal SMART_ON Smart On – Analog signal between PSUs to for Smart On

B23 Signal 12V Current Share Bus– Analog signal between PSUs to allow
ISHARE for current sharing
B24 Signal LOW state on this signal indicates the PSU is physically presents.
PRESENT_N

B25 Signal Reserved

Table 30 : Output Pin Assignment

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 11.4 Fan Numbering
The PSU shall contains one Delta GFM0412SS-08GP8 series (Or equivalent) 40mm x 56mm dual
counter-rotating fan modules
The fans numbering shall be identified as below (top view)

Figure 10 : PSU Fan Numbering

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 12 PSU LABELLING REQUIREMENTS
12.1 Vendor Labeling
The PSU shall contain a label detailing the details of manufacture (Vendor, Model Number, Date of
Manufacture, etc.) as well as the appropriate safety and compliance markings as described later in this
document.

12.2 Country of Origin Label

The PSU shall incorporate a Country of Origin label applied to the PSU
The correct “country of manufacturing/ assembly” should be substituted in as needed.

12.3 Safety Caution Labels

Power supplies shall be marked with the electric shock hazard, similar to ISO 3864 no. 5036 and with the bar-over-
screwdriver "Do Not Open" icon, in accordance with the artwork provided.

Figure 11 : Safety Caution Labels

12.4 80 Plus certificate Label

The PSU shall complete 80Plus certification according to product requirement and contain a 80Plus
logo.

Figure 42 : Reference 80Plus Logo

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 13 ELECTROMAGNETIC COMMPATIBILITY
13.1 EMC Design Objectives
The PSU is intended to meet world-wide EMC regulatory compliance requirements with the power
subassembly integrated into the final product (system, peripheral, etc).

13.2 EMC Requirements

Characteristic Standard reference Requirements

CISPR 32 Class A limits over freq. range 30 MHz to 1GHz. At least 6 dB margin
Radiated Emissions
EN55032, FCC CFR47 Part 15 below limits. (5 dB margin for DC input)

CISPR 32 Class A limits over freq. range 150 kHz to 30 MHz on power cord and
Conducted Emissions EN55032, FCC CFR47 Part 15 LAN cables.
At least 6 dB margin below limits. (5 dB margin for DC input)
Contact discharge 4 kV (indirect and direct to metal parts).,criteria B;
CISPR 24 / EN55024 Contact discharge 6 KV, criteria B for the telecomm product used in other
Electrostatic
EN61000-4-2 than telecommunication centers;
discharge
EN300386 Air discharge 8 kV, Performance criteria B.
(ESD)
GR1089 For NEBS purpose, 8KV for contact discharge, 15KV for air discharge,
criteria B.
Must pass
CISPR 24 / EN55024 80-690 MHz: 3 V/m; 690-60000MHz: 10V/m with 80% amplitude
Radiated Immunity EN61000-4-3 modulation at 1 kHz.Performance criteria A;with 80% amplitude
EN 300386 modulation at 1 kHz.
Performance criteria A.

Electrical Fast CISPR 24 / EN55024

Must pass 1 kV power-lines. performance criteria A.
Transient Immunity EN61000-4-4

CISPR 24 / EN55024 Must pass 3 Vrms 80% AM, freq. range 150 kHz–80 MHz to power-line.
Conducted Immunity
EN61000-4-6 Performance criteria A .

CISPR 24/
EN55024 Must pass 1kV diff. mode (2Ohm), 2kV comm (12Ohm). mode to power
Surge
EN61000-4-5 lines with performance criteria A
EN 300386

CISPR 24 / >95 % reduction 0. 5 period, B

EN55024 30 % reduction 25 periods, C
Dips
EN61000-4-11 >95 % reduction 250 periods, C
EN300386 100 % reduction 1 periods, B

CISPR 24 / Must pass 1 A/m (r.m.s), frequency 50 Hz, with performance criteria A.
Magnetic
EN55024 Reasonable specification level: 3 A/m (r.m.s) at frequency 50 and 60 Hz,
Susceptibility
EN61000-4-8 with performance criteria A.

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 Characteristic Standard reference Requirements

Harmonics EN61000-3-2 Limits per Table 1 of the standard (class A equipment).

Must pass: Pst =< 1; Plt =< 0.65; Dc=< 3,3%;

Line flicker EN61000-3-3
D(t)=<3,3% up to 500ms; Dmax=<4%

Table 31 : EMC Requirements

13.3 Packaging Requirements

This Power Subassembly will be integrated into a system enclosure which is designed to shield high
frequency emissions. Any part of the Power Subassembly which has an external surface of the system must
have controlled aperture sizes. The aperture diagonal dimensions must be less than 4.0 mm (an exception
shall be the initial exhaust perf. size, which can be 4.7mm). The best configuration would be an array of
holes or honeycombs. This keeps the aperture sizes small and provides the best air flow into the Power
Subassembly.

13.4 EMC Verification Process

Where possible, the developer/supplier should perform the EMC tests prior to shipping the subassembly
to Customer for evaluation. Customer / Supplier will perform EMC tests on the subassembly using either
resistive loads or linear electronic loads with the defined system capacitance. These subassembly tests will
reflect the product (system, peripheral, etc) they are integrated into by providing a chassis connection
between the power subassembly and the loads. If the product has castors, the subassembly test will provide
spacing for castors to any ground planes used for testing. Final verification will be performed with the
power subassembly integrated into the final product (system, peripheral, etc). For external stand-alone
products such as an Uninterruptible Power Supply (UPS), final verification will be performed connected to
actual system loads.

13.5 Grounding of the Output Voltage Return Lines

The output voltage returns, need to be designed so they may be connected to the power supply chassis
ground. This may be done directly or via a capacitor. These methods shall not be changed without prior
approval. There shall be a minimum of two (2) power-ground-to-chassis-ground connection points placed

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near the output connector. Additional power-ground-to-chassis-ground connections are recommended
around the perimeter of the PC board.

13.6 Earth Ground Connection to Power Supply Input Filters

The power supply shall provide redundant connections on the PC board to chassis (green-wire ground),
in the area of the input filters. This includes the grounding screw holes (especially around Y-capacitors). The
grounding screw holes should have plated grounding rings on both sides of the printed circuit board, with
vias and plated holes. Quality issues have been prevalent in this area, due to excess solder left on the ring,
causing cold solder joints. These connections must be approved by Customer / Engineering

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 14 POWER LINE SUSCEPTIBILITY REQUIREMENTS
14.1 Design Objectives
The Power Line Disturbance (PLD) requirements specify how the power supply should function under
defined input power conditions such as under-voltage, over-voltage, input line disturbances, utility
switching (RING), and lightning strike conditions. These design objectives are to meet the system PLD
requirements with the power supply integrated into a finished product (system, peripheral, etc).
The requirements listed are intended to serve as design objectives for the power supply
developer/supplier and to indicate what testing and/or analysis should be performed on the power
subassembly prior to system integration.

14.2 Verification Process

Where possible, the developer/supplier should perform the PLD tests prior to sending the power supply
to Customer for evaluation. Customer / Supplier will perform PLD tests on the power supply using resistive
loads (with some capacitance). These tests are generally performed early in the design process so any
problems identified can be corrected prior to system testing.
Final verification and certifications will be performed with the power supply integrated into the final
product (system, peripheral, etc). For external stand alone products such as Uninterruptible Power Supplies
(UPS), final verification will be performed connected to actual system loads.

14.3 Error-Free Operation

Error-free operation implies that the power supply must remain in regulation, and not power off. There
should be no functional errors or error conditions requiring operator intervention.
These tests are performed at both the lowest and highest nominal operating voltage of the power supply

Duration
Test Condition Voltage Transient (%)
(Seconds)
E2 Over-Voltage +20% 2.0

Table 32 : Error Free Operation

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 Notes:
-A load of 100% of the maximum rated output current for each output applies to this test condition
-Tested at maximum nominal voltage (e.g 240Vac)

14.4 Damage-Free Operation

Damage-Free operation implies that the power supply must not sustain any physical damage to the
assembly or components, including fuses. This also means not creating damage to the final product/system
due to something the power supply does. These tests are performed at both the lowest and highest nominal
operating voltage of the power supply

Voltage Transient Duration

Test Condition
[%] [Seconds]
D1.2 Under-voltage -100% 0.1

D2.2 Under-voltage -65% 0.5

-100% 0.5

D4 Under-voltage -100% 1.5

-100% 3.3

D5.1 Open Circuit +20% 2.0

D5.2 Power Off Remove Power Cord from PSU one time

D5.2 Room Power Drop Room Power (complete system) one time

Table 33 : Damage Free Operation

Notes:
-Surge condition tested at maximum nominal voltage (127Vac/240Vac)
-Sag conditions tested at minimum nominal voltage (100Vac/200Vac)

14.5 Latch-Free Operation

Latched-Free Operation implies that, although the power supply might power off under these conditions, it
must be capable of restarting, either automatically or under program control after the disturbance. At no time
should the input power cord have to be removed to clear an error condition.
Latched-Free Operation conditions are tested from -40% to -100% under-voltage conditions for times

台達電子工業股份有限公司 DESCRIPTION :
DELTA ELECTRONICS, INC. 電氣規格 (Electrical Specification)
THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF DELTA
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MODEL NO. :
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SHEET 60 OF 74
from 0.025 to 2.0 seconds. The table below shows the time intervals and the under-voltage conditions tested.
For each time interval, all of the under-voltage deviations listed will be tested. These tests are performed at
both the lowest and highest nominal operating voltage of the power supply.

Time Intervals (seconds)

0.025, 0.040, 0.060, 0.090, 0.130, 0.200, 0.280, 0.400, 0.600, 0.900, 1.3, 2.0

Under-voltage Deviation from nominal voltage

40%, 50%, 60%, 70%, 80%, 90%, 100%

Voltage input (Vrms)

100Vac, 200Vac

14.6 European Union (EU) Power Line Disturbances (PLD) Requirements

In addition to the above PLD requirements, the European Union (EU) has PLD requirements which are
defined in EN 61000-4-11. The PSU shall designed to operate with low-voltage AC public power
networks (<16A per phase). The power supply must meet the test conditions listed without any power loss
or power failure indicators.

14.6.1 Supply Voltage Variations

The variation and interruption are similar to the "damage-free" and "latched-free operations as defined in
the PLD requirements section. For each time interval, all of the under-voltage deviations listed will be
tested. These tests are performed at both the lowest and highest nominal operating voltage of the power
supply
Time Intervals (seconds)
0.050, 0.100, 0.200, 0.500, 1.0, 5.0
Under-voltage Deviation from nominal voltage
30%, 50%, 100%

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MODEL NO. :
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 14.7 Lightning Surge Susceptibility
The European requirements are based on EN 61000-4-5.The table below shows the Lightning Surge
requirements for power subassemblies prior to being installed into a final product. These tests are performed
as a bench test using electronic or resistive loads. These requirements are 500V higher than required when
installed into a final product.
Outputs that connect to communication circuits might need additional output capacitance or sense circuit
filtering. Communication cable surge testing may apply external energy to outputs due to clamp circuit
design..

Power Line Phases

Test Condition
L N E/G

+2.0KV COMMON
Delta and WYE
Line to Ground
-2.0KV COMMON

+2.0KV
Delta and WYE
Line to Line
-2.0KV

+2.0KV COMMON
Wye
Line to Neutra;
-2.0KV COMMON

Table 34 : Lightning Surge Requirements

Notes:
1) Lightning tests performed at surge voltages of 0.5KV, 1.0KV, 1.5KV, 2.0KV, 2.2KV and 2.5KV and
at AC power phase angles of 0, 90, 180, and 270 degrees
2) COMMON is common return to tester
3) The source impedance for differential mode is 2 Ohm and common mode is 12 Ohm.
4) 1.2uS x 50uS Combination Wave

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 15 ENVIROMENT REQUIREMENT
15.1 Temperature

15.1.1 Operating:
0 °C to +50 °C.

15.1.2 Non-Operating:
– 40 °C to +70 °C.

15.2 Humidity

15.2.1 Operating:
8 to 90% (Non condensing) .

15.2.2 Non-Operating:
5 to 95% (Non condensing)

15.3 Altitude

15.3.1 Operating:
16,500 ft (5000m) maximum

15.3.2 Non-Operating:
39,370 ft (12,000m)

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 16 MECHANICAL SHOCK&VIBRATION
16.1 Operating Shock Test
30G, 11ms, half-sine, three shocks in each of three axes(+/-), 3 axes testing; total 18 shocks.

16.2 Non-Operating Shock Drop Test

When properly packaged, the power supply shall withstand a drop test per D-5276 Standard Test Method
for Drop Test of Loaded Containers by Free Fall. The drop height shall be 90 cm, and the ten drop cycle
according to ASTM D-5276 A.2.2.2 shall be used. This non-operating shock drop test shall follow the
non-operating vibration repetitive shock test of 6.5.3, and the power supply shall be packaged in the same
material that was used in the repetitive shock test of 6.5.3.

16.3 Non-Operating Shock - Unpackaged

142 G ± 5% with pulse duration of 2 msec ± 10% half sine shock, 3 shocks/side, 6 side testing, total 18
shocks.

16.4 Non-Packaged
The power supply shall withstand a 3.9-inch drop test on all sides and corners onto a solid surface
without any physical damage.

16.5 Packaged Drop

The sample shall be dropped once on:
 Each face (6 drops).
 Each edge (12 drops).
 Each corner (8 drops).
The total number of drops is 26 for single packages ≤46 kg in total weight
The drop height shall be 1 m for single packages ≤32 kg total weight. For single packages >32 but ≤46

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kg in total weight,the drop height shall be 0.5 m.
Palletized loads shall be dropped from 0.125 m height for six (6) times plus one (1) additional time from
0.25 m height. All seven drops shall only be done onto the pallet’s bottom surface

16.6 Free Fall Drop

 3.9-inch free drop for practical resting surface. Usually only bottom and top face, total 2 3.9-inch
drops;
 3.9-inch edge drops, 4 edge drops for bottom face, 4 edge drops for top face, total 8 edge drops.

16.7 Operating Random Vibration Test

0.701Grms,5~500Hz,30minutes/axis, 3 axis testing.

16.8 Random Vibration - Packaged

2.379 Grms, 1-500 Hz, 30 minutes/axis, 3 axis testing

16.9 Non-Operating Random Vibration - Unpackaged

2.532 Grms, 2-500 Hz, 15 minutes per side, 6 side testing

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MODEL NO. :
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 17 SAFETY REQUIREMENT
17.1 Safety Requirements
The power supply must comply with below listed standards:
Country Safety Standards
IEC 60950-1 2012 A2-2013
International
IEC 62368 2014, 2nd Edition
UL 60950-1, 2nd Edition, 2014-10-14
US
UL 62368
Canada CAN/CSA C22.2 No. 60950-1-07, 2nd Edition, 2014-10
EN 60950-1/A12:2011 A2: 2013
EU
EN 62368
China GB 4943.1-2011 (Note 1)

Table 35 : Safety Standards

Note 1: Meet tropical climate requirements according section 1.7.2 and 2.9.2 of GB4943

17.2 Certifications Requirements

Below just listed the basic certification requirements requested to power supply for customer products,
but not limited.

Country/Region Certificate Remarks

International CB IEC 60950-1 2012 A2-2013, IEC62368 2014 cover EN 60950-1/A12:2011 A2: 2013 and EN62368

US FCC FCC verification Report

UL 60950-1, 2nd Edition, 2014-10-14, CAN/CSA C22.2 No. 60950-1-07, 2nd Edition, 2014-10;
US/Canada cUL
UL62368
EU CE LVD safety report, EMC report, RoHS CoC

China CCC GB 4943, GB9254

Taiwan BSMI

Korea MSIP

India BIS

Table 36 : Safety Certification Requirement

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MODEL NO. :
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 17.3 Metal Oxide Varistors
Should MOV’s be used as voltage protection devices, the devices will be of an approved type and
identified with the appropriate agency markings. Heat-shrink tubing of an appropriate type and flame rating
will be used to surround the MOV body in a manner acceptable to the product-safety agencies.

17.4 Flammability
Unless otherwise specified, plastic material used in the construction of the item shall be rated
94V-1, or better, per UL 94 with an oxygen index of 28%, or better, per ASTM D 2863. Wire and cable
used in the construction of the item shall be rated VW-1 or better per UL 1581 or rated FT-1 per CSA C22.2,
#0.3, section 4.11.

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MODEL NO. :
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 18 RELIABILITY REQUIREMENTS
18.1 MTBF Calculation
The PSU shall have a target Mean Time Between Failures (MTBF) of 100,000 hours with 75% loading
at 40 Deg.C ambient temperature. This may be demonstrated through a combination of Reliability
Prediction calculations, HALT testing, and / or Demonstrated Reliability Testing. It is recognized that
prediction calculations alone are unlikely to show a number as good as this.

18.2 Cap Life

All capacitors to have predicted life of at least 43,800 hours POL by following two conditions:
 50 Deg.C, 80% output loading , 100Vac/200Vac

Capacitor life prediction for all sources of electrolytic capacitors to be by verified current ripple and
temperature tests, and de-rating analysis.

18.3 Fan Life

All fans to have L10 life of at least 55,000 hours at 50C surface temperature of the fan. Fan life to be
verified by testing on same or similar model by fan supplier.

18.4 On/Off Cycles

The power supply shall be designed to withstand a minimum of 5000 ON/OFF cycles without failure
rate degradation.

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 19 ANTI-SMOKE REQUIREMENTS
This PSU shall be designed to reduce the occurrence of smoke, noise, or smell, such that less than
0.1% of allowed failures, will cause or result in:

 Audible noise during failure of greater than 70 dB

 Visible smoke
 Visible spark or fire
 Burning smell

This unit shall also be designed to have no occurrence of smoke beyond 3% distortion per 1ft of distance
within 6ft of the system. (This is the amount of smoke that would trip a standard smoke detector.)

Anti-smoke fusing required for all switching stages that run on the bulk voltage and all secondary
switching regulator circuits. This includes Control Supplies, regulation stages of the boost input caps (fuse
to be located after the bulk capacitors), and post regulators.

Additional fusing over and above the AC line fuses should be investigated for the Boost FETs; if the
reliability of fuses for the Boost FETs can be shown to be acceptable, fuses there should also be
implemented.

Non-Fused Tantalum ( Ta-MnO2 ) capacitors and Non-Fused ( Nb ) Niobium should be eliminated and
replaced with acceptable technology (e.g., Polymer Tantalums ( Ta-Poly), Polymerized Aluminum ( Ta-AL)
Electrolytic, Niobium/Oxide ( NbO), Fused Tantalums (Ta-MnO2), Fused Niobium ( Nb ), Aluminum
Electrolytic and Ceramics.

Abnormal tests performed as required by Safety shall now be performed with the additional
requirement that failures shall be smoke-free. The tests shall include open and shorts at critical
points within the power supply. The list will be prepared as a joint effort between the Supplier
and customer. An audio/video tape of the testing is required to document the results. The list shall

台達電子工業股份有限公司 DESCRIPTION :
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 include the shorting out of all secondary outputs as well as all MOSFETs.

A Smoke Reduction Protection Block Diagram shall be provided by the supplier. The diagram shall
highlight the key smoke reduction protection circuits for the power supply design.

Changes to the design after qualification by Customer require written approval and proof of smoke-free
compliance.

A separate over–voltage protection circuit shall be added to the power factor correction stage.
PFC/Boost stage OVP detection shall be independent from the feedback regulation resistors and
reference voltage.

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MODEL NO. :
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WITHOUT PERMISSION. TDPS-2400HB A
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 20 PRODUCTION TESTING AND QUALITY
The following test plans are to be supplied by the vendor and approved by Customer before testing
begins:
Manufacturing final test plan and procedure
Quality plan describing manufacturing process

20.1 Functional Testing

Production testing must be incorporated by the supplier to verify that all (100%) of the product shipped
to Customer meets the specifications. Zero defects is the only acceptable quality level, and no material
having any known defect will be accepted for use by Customer. In addition, hi-pot testing must be
performed on all (100%) of the product prior to shipment. Production test data shall be made available to
Customer on request.

20.2 Functional Burn-In

The burn-in plans shall provided by vendor and approved by Customer.

20.3 Hi-Pot and Ground Continuity Tests

100% production testing for Hi-Pot and ground continuity must be performed. Records of test results
shall be maintained as directed by the appropriate safety certification agencies. The vendor information label
is to be affixed to power supplies that have successfully passed these tests. Permanent ink stamps are also
acceptable

20.3.1 Hi-Pot Test (Electric Strength)

The power supply must pass hi-pot test and be maintained at that level without failure.
 Primary to Safety ground : 2500 Vdc
 Ramp up time : 5 seconds
 Test duration : 60 seconds
 Max. steady DC leakage current : 10 uA

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MODEL NO. :
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 20.3.2 Ground Continuity Test
The impedance from the ground pin on the input connector and the power supply assembly chassis must
be less than 0.05 Ohms. This test is required on 100% of all product shipped and shall be a 30 Adc test for 1
second or Customer approved equivalent.

Alternatively this test can be performed using a current of 25 A DC and an impedance of 0.06 Ohms.

20.4 Redundant Operation and Hot-Plug

Every power supply shipped to Customer must be tested and pass a redundant operation test (including
current-sharing) and a hot-plug test, to be defined/approved by Customer and to be performed at the
supplier.

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MODEL NO. :
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 21 GREEN REQUIREMENTS
The Power supply must comply with green requirement listed below.
Country/Region Green Standards
Directive 2012/19/EU on Waste Electrical and Electronic Equipment (WEEE)
European Union ROHS directive: 2011/65/EU

EU SVHC requirements of REACH directive: (EC) No. 1907/2006

Packaging Directive -
The latest revision of the Packaging and Packaging Waste Directive occurred on 29 April 2015 with the
adoption of Directive (EU) 2015/720 of the European Parliament and of the Council amending Directive
94/62/EC as regards the consumption of lightweight plastic carrier bags
China RoHS, comply with <电子信息产品污染控制管理办法>

Table 37 : Green Requirements

22 COMPONENTS
The components used in this power supply are the responsibility of the supplier. There shall be no
Customer consigned parts in this power supply.

23 PROCESS CHANGE NOTICE (PCN)

The power supply is considered a critical part. Any changes in manufacturing process, components or
materials EOL noitification after final qualification shall go through Customer PCN process prior to
implementation.

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 24 MECHANICAL OUTLINE DRAWING

Figure 5 : Mechanical Outline Drawing

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