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BEET 404 Computer Org. Architecture

UTU 2022-23 COA paper

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20 views

BEET 404 Computer Org. Architecture

UTU 2022-23 COA paper

Uploaded by

sashishere107
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sub Code: BEET 404/BITT404 ROLL NO……………..……………..

IV SEMESTER EXAMINATION, 2022 – 23


IInd Year B.Tech. –Computer Science & Engineering/Information Technology
COMPUTER ORGANIZATION & ARCHITECTURE
Duration: 3:00 hrs Max Marks: 100
Note: - Attempt all questions. All Questions carry equal marks. In case of any ambiguity or missing
data, the same may be assumed and state the assumption made in the answer.

Q 1. Answer any four parts of the following. 5x4=20


a) What is bus arbitration? Explain different types of bus arbitration with suitable
diagram.
b) Discuss the importance of instruction format in processor organization, including the
types of instructions commonly used and how they are encoded.
c) Discuss the advantages and disadvantages of using a RISC architecture compared to a
complex instruction set computer (CISC).
d) Discuss the Memory Hierarchy in computer system with regard to Speed, Size and
Cost?
e) Explain the concept of parallel processing and why it is important in computer
architecture.
f) What is pipelining? Draw the diagram for instruction pipelining.
Q 2. Answer any four parts of the following. 5x4=20
a) Represent the number (+46.5)10 as a floating-point binary number with 32 bits format.
b) Explain Virtual address Mapping using Pages with necessary examples.
c) Describe the basic principles of pipelining and give examples of arithmetic, and RISC
pipelining.
d) Discuss the concept of direct memory access (DMA) and how it can be used to
improve I/O performance.
e) Explain the significance of cache memory.
f) Write down the expressions for speedup factor in a pipelined architecture.
Q 3. Answer any two parts of the following. 10x2=
a) Explain the basic organization of a micro programmed control unit and the generation 20
of control signals using micro program.
b) The computer has a main memory access time of 60 ns. We want to reduce this time
to 20 ns by adding cache. Determine how fast the cache must be (access time) if we can
expect a 90% probability of a hit.
c) Design a 4-bit ALU which performs arithmetic, Logical and shift operations. What is
the difference between a micro-processor and a micro program?
Q 4. Answer any two parts of the following. 10x2=
a) Describe the control unit organization with a separate Encoder and Decoder functions 20
in a hardwired control.
b) Describe the different methods of interprocessor arbitration and their suitability for
different types of multiprocessor systems.
c) In a computer with cache, we have the average number of clock periods per instruction
equal to 4, if there are no misses in the cache.
i) What is the real number of clock periods per instruction, if the probability of miss in
the cache is 10%? For the replacement of the block (line) in the cache, we need 5 clock
periods for read and 10 for write accesses. Assume that each instruction requires an
average of 2 memory accesses and that 20% of all are write accesses.
ii) What is the real CPI, if we increase the probability of hit to 95%?
Q 5. Answer any two parts of the following. 10x2=
a) What are the different addressing modes commonly used in processors? Provide 20
examples of each mode and describe its benefits.
b) Discuss the challenges of cache coherence in distributed systems and describe the
techniques used to ensure coherence, such as invalidation-based and update-based
protocols.
c) Write short on
i) Instruction pipelining
ii) I/O Interface

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